CN114003550A - FPGA configuration device in JTAG mode - Google Patents
FPGA configuration device in JTAG mode Download PDFInfo
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- CN114003550A CN114003550A CN202111283731.8A CN202111283731A CN114003550A CN 114003550 A CN114003550 A CN 114003550A CN 202111283731 A CN202111283731 A CN 202111283731A CN 114003550 A CN114003550 A CN 114003550A
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- 239000013078 crystal Substances 0.000 claims abstract description 13
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7885—Runtime interface, e.g. data exchange, runtime control
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Abstract
The invention relates to an FPGA configuration device in a JTAG mode, belonging to the technical field of configuration downloading of a programmable gate array. The device comprises a system controller, a state indicator, a dial switch, a FLASH memory chip, a power supply chip, a crystal oscillator and at least two JTAG interfaces; the state indicator, the dial switch, the FLASH memory chip, the power supply chip, the crystal oscillator and the JTAG interface are all connected with the system controller; the FLASH storage chip is connected with the power supply chip, and the power supply chip is connected with the crystal oscillator. The invention downloads the configuration files of the FPGA through the JTAG mode, supports the simultaneous configuration of a plurality of FPGA chips, and can store a plurality of configuration files, thereby improving the configuration flexibility and convenience.
Description
Technical Field
The invention relates to an FPGA configuration device in a JTAG mode, belonging to the technical field of configuration downloading of a programmable gate array.
Background
The FPGA is a programmable signal processing device, and a user can define the functions of the FPGA by changing configuration information so as to meet design requirements. The FPGA is mainly characterized in that: (1) the module structure has programmable logic function; (2) the system has a programmable input/output module structure; (3) having a programmable interconnect resource structure; (4) it is configured and downloaded with dedicated EDA (Electronic Design Automation) software.
Compared with the traditional digital circuit system, the FPGA has the advantages of programmability, high integration level, high speed, high reliability and the like. By configuring the logic function and the input/output port inside the device, the original circuit board level design work is carried out in the chip, the circuit performance is improved, the workload and the difficulty of the printed circuit board design are greatly reduced, and the flexibility and the efficiency of the design are effectively improved. FPGAs have significant advantages over ASICs (Application Specific Integrated circuits): the development period is short, the early investment risk is small, the product marketing speed is high, the market adaptability is strong, and the hardware upgrading space is large. After the product is finalized and the yield is enlarged, the design realized in the FPGA can be quickly customized to an ASIC for production. The advantages of FPGA are not limited to original design, and the FPGA is used for converting and realizing the existing ASIC product again on a new process node, so that the product is upgraded more easily. The logic function realized by the FPGA is determined by the programming download of a user, and a special configuration file download device is required for programming the FPGA.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: an FPGA configuration device in JTAG mode is provided.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: an FPGA configuration device in a JTAG mode comprises a system controller, a state indicator, a dial switch, a FLASH memory chip, a power supply chip, a crystal oscillator and at least two JTAG interfaces; the state indicator, the dial switch, the FLASH memory chip, the power supply chip, the crystal oscillator and the JTAG interface are all connected with the system controller; the FLASH storage chip is connected with the power supply chip, and the power supply chip is connected with the crystal oscillator; the JTAG interface is used for connecting an FPGA to be configured; the FLASH memory chip is used for storing configuration information; the dial switch is used for selecting configuration information in the FLASH memory chip; the status indicator light is used for displaying the configuration progress and the working state of the system controller.
The further improvement of the scheme is as follows: the system controller comprises an EP1C6Q240 chip, a FLASH chip, a JTAG interface and an active serial AS interface.
The further improvement of the scheme is as follows: the power supply chip is connected with an external power supply.
The invention has the beneficial effects that: the invention downloads the configuration files of the FPGA through the JTAG mode, supports the simultaneous configuration of a plurality of FPGA chips, and can store a plurality of configuration files, thereby improving the configuration flexibility and convenience. The device has the characteristics of low development cost of a hardware system, simple compiling of matched software and high data transmission stability. The device has important significance for external field debugging and application of the FPGA chip.
Drawings
Fig. 1 is a schematic block diagram of an FPGA configuration apparatus in JTAG mode according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a system controller of an FPGA configuration apparatus in JTAG mode according to an embodiment of the present invention.
Detailed Description
Example one
The FPGA configuration device in JTAG mode of this embodiment, as shown in fig. 1, includes a system controller, a status indicator, a dial switch, a FLASH memory chip, a power chip, a crystal oscillator, and at least two JTAG interfaces; the state indicator, the dial switch, the FLASH memory chip, the power supply chip, the crystal oscillator and the JTAG interface are all connected with the system controller; the FLASH storage chip is connected with the power supply chip, and the power supply chip is connected with the crystal oscillator; the JTAG interface is used for connecting an FPGA to be configured; the FLASH memory chip is used for storing configuration information; the dial switch is used for selecting configuration information in the FLASH memory chip; the status indicator light is used for displaying the configuration progress and the working state of the system controller. The system controller, AS shown in fig. 2, includes an EP1C6Q240 chip, a FLASH chip, a JTAG interface, and an active serial AS interface.
The power supply chip is connected with an external power supply. Completing voltage conversion for supplying power to a system controller, a FLASH memory chip and a crystal oscillator;
according to the embodiment, the configuration files of the FPGA are downloaded through the JTAG mode, a plurality of FPGA chips are configured at the same time, a plurality of configuration files can be stored, and configuration flexibility and convenience are improved.
In this embodiment, if the condition allows, that is, under the condition that the FLASH storage capacity permits, the user may store multiple pieces of configuration information, where each piece of configuration information is composed of four parts, that is, an FPGA reset instruction, an FPGA configuration instruction, a configuration file, and an FPGA unfreezing instruction.
The JTAG interface module of this embodiment transmits three JTAG signals (TCK, TMS, TDI) generated by the system controller to the FPGA chip to be configured, and transmits one JTAG signal (TDO) generated by the FPGA chip to be configured to the system controller.
The embodiment has the advantages of simple hardware circuit design, low purchasing cost of required components, friendly man-machine interface and simple and convenient use, and particularly can reconfigure the FPGA under the condition of no power failure.
The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.
Claims (3)
1. An FPGA configuration device in JTAG mode, comprising: the device comprises a system controller, a state indicator, a dial switch, a FLASH memory chip, a power supply chip, a crystal oscillator and at least two JTAG interfaces; the state indicator, the dial switch, the FLASH memory chip, the power supply chip, the crystal oscillator and the JTAG interface are all connected with the system controller; the FLASH storage chip is connected with the power supply chip, and the power supply chip is connected with the crystal oscillator; the JTAG interface is used for connecting an FPGA to be configured; the FLASH memory chip is used for storing configuration information; the dial switch is used for selecting configuration information in the FLASH memory chip; the status indicator light is used for displaying the configuration progress and the working state of the system controller.
2. The JTAG mode FPGA configuration device of claim 1, wherein: the system controller comprises an EP1C6Q240 chip, a FLASH chip, a JTAG interface and an active serial AS interface.
3. The JTAG mode FPGA configuration device of claim 1, wherein: the power supply chip is connected with an external power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111283731.8A CN114003550A (en) | 2021-11-01 | 2021-11-01 | FPGA configuration device in JTAG mode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111283731.8A CN114003550A (en) | 2021-11-01 | 2021-11-01 | FPGA configuration device in JTAG mode |
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| CN114003550A true CN114003550A (en) | 2022-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111283731.8A Pending CN114003550A (en) | 2021-11-01 | 2021-11-01 | FPGA configuration device in JTAG mode |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7685380B1 (en) * | 2005-06-29 | 2010-03-23 | Xilinx, Inc. | Method for using configuration memory for data storage and read operations |
| CN202917070U (en) * | 2012-10-26 | 2013-05-01 | 中国电子科技集团公司第四十七研究所 | Extensible interface type FPGA verification and development board |
| CN103823781A (en) * | 2014-03-03 | 2014-05-28 | 中国科学院电子学研究所 | Downloading device for field-programmable gate array logical code |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN112084125A (en) * | 2020-08-26 | 2020-12-15 | 中科亿海微电子科技（苏州）有限公司 | Device and method for downloading configuration file of field programmable gate array |
-
2021
- 2021-11-01 CN CN202111283731.8A patent/CN114003550A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7685380B1 (en) * | 2005-06-29 | 2010-03-23 | Xilinx, Inc. | Method for using configuration memory for data storage and read operations |
| CN202917070U (en) * | 2012-10-26 | 2013-05-01 | 中国电子科技集团公司第四十七研究所 | Extensible interface type FPGA verification and development board |
| CN103823781A (en) * | 2014-03-03 | 2014-05-28 | 中国科学院电子学研究所 | Downloading device for field-programmable gate array logical code |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN112084125A (en) * | 2020-08-26 | 2020-12-15 | 中科亿海微电子科技（苏州）有限公司 | Device and method for downloading configuration file of field programmable gate array |
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Application publication date: 20220201 |
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