CN112506832B - USB JTAG acquisition and downloading integrated device - Google Patents
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- CN112506832B CN112506832B CN202011440616.2A CN202011440616A CN112506832B CN 112506832 B CN112506832 B CN 112506832B CN 202011440616 A CN202011440616 A CN 202011440616A CN 112506832 B CN112506832 B CN 112506832B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3812—USB port controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a USB JTAG acquisition and downloading integrated device, which consists of 9 parts, namely a USB interface, a power supply module, an interface module, a main control module, a clock module, a signal generation module, a data acquisition module, a level conversion module and a JTAG interface. The invention supports downloading and signal acquisition at the same time, is convenient for JTAG signal analysis and fault location, and has higher practical value.
Description
Technical Field
The invention belongs to the technical field of USB JTAG downloaders, and relates to a USB JTAG acquisition and downloading integrated device.
Background
The USB JTAG downloader is widely used for downloading, debugging and online analysis of devices such as DSP, CPLD and FPGA. Because the existing USB JTAG downloader does not support JTAG signal real-time acquisition, when JTAG communication is in problem, an oscilloscope, a logic analyzer or a special JTAG analysis device is needed for auxiliary analysis. These instruments and equipment often are expensive, the portability is poor, and need many lead wires to connect, not only influenced the troubleshooting efficiency, still caused the trouble to judge by mistake easily because impedance or interference scheduling problem.
Disclosure of Invention
Object of the invention
The purpose of the invention is: aiming at the problem that the existing USB JTAG downloader does not support JTAG signal real-time acquisition, a USB JTAG acquisition and downloading integrated device is provided.
(II) technical scheme
In order to solve the technical problem, the invention provides a USB JTAG acquisition and downloading integrated device which is characterized by comprising 9 parts of a USB interface, a power supply module, an interface module, a main control module, a clock module, a signal generation module, a data acquisition module, a level conversion module and a JTAG interface, wherein the internal modules of the device have the following signal connection relations: one side of the interface module is connected with the USB interface, and the other side of the interface module is respectively connected with the main control module and the data acquisition module; the main control module is respectively connected with the interface module, the clock module, the signal generation module and the data acquisition module; the clock module is respectively connected with the main control module and the data acquisition module; the signal generation module is respectively connected with the main control module, the level conversion module and the data acquisition module; the data acquisition module is respectively connected with the main control module, the clock module, the signal generation module, the level conversion module and the interface module; one side of the level conversion module is connected with the signal generation module and the data acquisition module, and the other side of the level conversion module is connected with the JTAG interface.
The USB interface is a USB2.0, USB3.0 or USB3.1 interface and is used for connecting an upper computer, supplying power for the device and simultaneously transmitting instructions and data.
And the power supply module converts the 5V voltage provided by the USB interface into the voltage required by each module to supply power for each module.
The interface module realizes the mutual conversion of the USB and the internal bus communication protocol, wherein the internal bus can select a serial bus or a parallel bus according to the specific realization mode of the interface module, the master control module and the data acquisition module.
The master control module analyzes the internal bus data to obtain instruction information, and controls the clock module, the signal generation module and the data acquisition module to complete corresponding functions according to the instruction and the data acquired by the data acquisition module; the main control module is internally provided with an analog data storage submodule for storing analog data of the JTAG protocol chip, and can control the output of TDI signals according to the data and TCK, TMS and TDO signals acquired by the data acquisition module, thereby realizing the chip analog function.
The clock module generates a clock signal with specified frequency under the instruction control of the main control module for the data acquisition module to use.
The signal generation module generates TCK, TMS, TDI and GPOx (x =0,1,2, \8230; m, m ∈ N) signals with specified time sequence under the instruction control of the main control module, and the generated TCK signals are simultaneously used by the data acquisition module.
The data acquisition module acquires data by using a clock signal generated by the clock module and a TCK signal generated by the signal generation module under the instruction control of the master control module, and transmits the acquired data to the master control module or transmits the acquired data to the interface module through an internal bus and finally transmits the acquired data to an upper computer through a USB interface; the signals supporting acquisition comprise TCK, TMS, TDI, TDO, GPOx (x =0,1,2, \8230; m, m is N) and GPIy (y =0,1,2, \8230; N, N is N).
The level conversion module realizes the level conversion of the internal input and output signals and the JTAG interface input and output signals; the external output signals of the module comprise TCK, TMS, TDI and GPOx (x =0,1,2, \ 8230;, m, m ∈ N) signals, and the internal input signals comprise TCK, TMS, TDI, TDO, GPOx (x =0,1,2, \ 8230;, m, m ∈ N) and GPIy (y =0,1,2, \ 8230;, N, N ∈ N) signals, relative to the device itself, wherein the TCK, TMS, TDI and GPOx (x =0,1,2, \ 8230;, m, m ∈ N) signals are connected by corresponding leads of the corresponding output signals, and the connection position is located between the level conversion module and the JTAG interface.
The JTAG interfaces are three-way interfaces, namely 3 JTAG interfaces, except one JTAG interface occupied by the device, the other two JTAG interfaces can be respectively connected with a common USB JTAG downloader and a chip supporting a JTAG protocol.
The device supports the following five working modes:
an acquisition mode: the mode is used for JTAG signal acquisition and is suitable for the condition that a JTAG interface is connected with a common USB JTAG downloader and is simultaneously connected with a JTAG protocol supporting chip; in an acquisition mode, the signal control module does not generate TCK, TMS and TDI signals, and the data acquisition module acquires the TCK, TMS, TDI and TDO signals by using the clock signals generated by the clock module.
And (3) downloading mode: the mode is used for downloading, debugging and online analysis of the chip and is suitable for the condition that the JTAG interface connection supports the JTAG protocol chip; in the download mode, the data acquisition module does not acquire TCK, TMS and TDI signals, and only the TCK signal and the clock signal generated by the clock module are used for acquiring the TDO signal.
Collecting a downloading mode: the mode is used for collecting JTAG signals while downloading, debugging and online analyzing the chip, and is suitable for the condition that JTAG interface connection supports a JTAG protocol chip; in the acquisition downloading mode, the data acquisition module acquires the TDO signal by using the TCK, and simultaneously acquires the TCK, TMS, TDI and TDO signals by using the clock signal generated by the clock module.
Simulation mode: the mode is used for simulating a chip supporting a JTAG protocol and is suitable for the condition that a JTAG interface is connected with a common USB JTAG downloader; in the analog mode, the signal control module does not generate TCK and TMS signals, but generates TDI signals, and the generation mode of the TDI signals is determined by analog data; the upper computer sends corresponding analog data to the main control module according to an appointed JTAG protocol chip, the main control module stores the data in the analog data storage submodule, and the main control module controls the TDI signal output of the signal generation module according to the data and TCK, TMS and TDO signals collected by the data collection module, so that a chip analog function is realized; in this mode, the data acquisition module only acquires the TCK, TMS, and TDO signals, and does not acquire the TDI signal, and its acquisition of the TCK, TMS, and TDO signals uses the clock signal generated by the clock module.
Simulating an acquisition mode: the mode is used for collecting JTAG signals while simulating a JTAG protocol chip, and is suitable for the condition that a JTAG interface is connected with a common USB JTAG downloader; in the analog acquisition mode, the signal control module does not generate TCK and TMS signals, but generates TDI signals, and the generation mode of the TDI signals is determined by analog data; the upper computer sends corresponding simulation data to the main control module according to a designated JTAG protocol chip, the main control module stores the data in the simulation data storage submodule, and the main control module controls the TDI signal output of the signal generation module according to the data and TCK, TMS and TDO signals acquired by the data acquisition module, so that the chip simulation function is realized; the device collects JTAG signals while simulating a JTAG protocol chip, namely TCK, TMS, TDI and TDO signals are collected through a data collection module, and clock signals generated by a clock module are used for signal collection.
For the above five modes, when the function needs, the signal generation module can generate GPOx (x =0,1,2, \ 8230;, m, m ∈ N) signals, and the data acquisition module can acquire the GPOx (x =0,1,2, \8230;, m, m ∈ N) and GPIy (y =0,1,2, \ 8230;, N, N ∈ N) signals.
(III) advantageous effects
The USB JTAG acquisition and downloading integrated device provided by the technical scheme supports downloading and signal acquisition, is convenient for JTAG signal analysis and fault location, and has higher practical value.
Drawings
FIG. 1 is a block diagram of an integrated USB JTAG acquisition and download device of the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be made in conjunction with the accompanying drawings and examples.
Referring to fig. 1, the USB JTAG acquisition and download integrated device of the present invention is composed of 9 parts, namely, a USB interface, a power module, an interface module, a master control module, a clock module, a signal generation module, a data acquisition module, a level conversion module, and a JTAG interface, wherein one side of the interface module is connected to the USB interface, and the other side is connected to the master control module and the data acquisition module, respectively; the main control module is respectively connected with the interface module, the clock module, the signal generation module and the data acquisition module; the clock module is respectively connected with the main control module and the data acquisition module; the signal generation module is respectively connected with the main control module, the level conversion module and the data acquisition module; the data acquisition module is respectively connected with the main control module, the clock module, the signal generation module, the level conversion module and the interface module; one side of the level conversion module is connected with the signal generation module and the data acquisition module, and the other side of the level conversion module is connected with the JTAG interface.
The USB interface is a USB2.0 interface and is used for connecting an upper computer, supplying power to the device and simultaneously transmitting instructions and data.
The power module converts 5V voltage provided by the USB interface into 3.3V voltage to supply power for each module, and the LDO is used for realizing the power supply.
The interface module adopts a USB2.0 interface chip to realize the mutual conversion between the USB and the internal bus communication protocol.
The main control module, the clock module, the signal generation module and the data acquisition module are realized by peripheral circuits such as a data logic device and a crystal oscillator, wherein:
the master control module analyzes the internal bus data to obtain instruction information, and controls the clock module, the signal generation module and the data acquisition module to complete corresponding functions according to the instruction and the data acquired by the data acquisition module; the main control module is internally provided with an analog data storage submodule for storing simulation data of the JTAG protocol chip, and can control TDI signal output according to the data and TCK, TMS and TDO signals collected by the data collection module, so that a chip simulation function is realized.
The clock module generates a clock signal with a specified frequency under the instruction control of the main control module for the data acquisition module to use.
The signal generation module generates TCK, TMS, TDI and GPO 1-GPO 4 signals with specified time sequence under the instruction control of the main control module, and the generated TCK signals are used by the data acquisition module at the same time.
The data acquisition module acquires data by using a clock signal CLK generated by the clock module and a TCK signal generated by the signal generation module under the instruction control of the main control module, and transmits the acquired data to the main control module or transmits the acquired data to the interface module through an internal bus and finally transmits the acquired data to an upper computer through a USB interface; the signals which support the collection comprise TCK, TMS, TDI, TDO, GPO 1-GPO 4 and GPI 1-GPI 4 signals.
The level conversion module realizes the level conversion of the internal input and output signals and the JTAG interface input and output signals; relative to the device, the module outputs signals including TCK, TMS, TDI and GPO 1-GPO 4 signals to the outside, inputs signals to the inside include TCK, TMS, TDI, TDO, GPO 1-GPO 4 and GPI 1-GPI 4 signals, wherein the TCK, TMS, TDI and GPO 1-GPO 4 signals are obtained by connecting corresponding lead wires of corresponding output signals, and the connection position is located between the level conversion module and the JTAG interface.
The JTAG interfaces are three-way interfaces, namely 3 JTAG interfaces, except one JTAG interface occupied by the device, the other two JTAG interfaces can be respectively connected with a common USB JTAG downloader and a chip supporting a JTAG protocol.
The device supports five working modes, the JTAG interface of the embodiment is connected with a chip supporting a JTAG protocol, and works in an acquisition downloading mode, namely, the JTAG signal is acquired while the chip is downloaded, debugged and analyzed on line. The data acquisition module acquires TDO signals by using TCK, and simultaneously acquires the TCK, TMS, TDI and TDO signals by using clock signals generated by the clock module and sends the signals to the upper computer through the interface module and the USB interface.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (1)
1. A USB JTAG acquisition and downloading integrated device is characterized by comprising: the device comprises a USB interface, a power supply module, an interface module, a main control module, a clock module, a signal generation module, a data acquisition module, a level conversion module and a JTAG interface; one side of the interface module is connected with the USB interface, and the other side of the interface module is respectively connected with the main control module and the data acquisition module; the master control module is respectively connected with the interface module, the clock module, the signal generation module and the data acquisition module; the clock module is respectively connected with the main control module and the data acquisition module; the signal generation module is respectively connected with the main control module, the level conversion module and the data acquisition module; the data acquisition module is respectively connected with the main control module, the clock module, the signal generation module, the level conversion module and the interface module; one side of the level conversion module is connected with the signal generation module and the data acquisition module, and the other side of the level conversion module is connected with the JTAG interface;
the USB interface is a USB2.0, USB3.0 or USB3.1 interface and is used for connecting an upper computer, supplying power to the integrated device and simultaneously transmitting instructions and data;
the power supply module converts the 5V voltage provided by the USB interface into the voltage required by each module to supply power for each module;
the interface module realizes the mutual conversion of the USB and the communication protocol of the internal bus, wherein the internal bus selects a serial or parallel bus according to the specific realization mode of the interface module, the master control module and the data acquisition module;
the master control module analyzes the internal bus data to obtain instruction information, and controls the clock module, the signal generation module and the data acquisition module to complete corresponding functions according to the instruction and the data acquired by the data acquisition module; the main control module is internally provided with an analog data storage submodule for storing simulation data of the JTAG protocol chip, and controls TDI signal output according to the data and TCK, TMS and TDO signals collected by the data collection module, so that a chip simulation function is realized;
the clock module generates a clock signal with specified frequency under the instruction control of the main control module for the data acquisition module to use;
the signal generation module generates TCK, TMS, TDI and GPOx signals with appointed time sequence under the instruction control of the main control module, the generated TCK signals are simultaneously used by the data acquisition module, and x =0,1,2, \ 8230;, m, m are equal to N;
the data acquisition module acquires data by using a clock signal generated by the clock module and a TCK signal generated by the signal generation module under the instruction control of the master control module, and transmits the acquired data to the master control module or transmits the acquired data to the interface module through an internal bus and finally transmits the acquired data to an upper computer through a USB interface; the signals supporting acquisition comprise TCK, TMS, TDI, TDO, GPOx and GPIy signals, x =0,1,2, \8230, m, m belongs to N, y =0,1,2, \8230, N belongs to N;
the level conversion module realizes the level conversion of the internal input and output signals and the JTAG interface input and output signals; relative to the device, the module outputs signals including TCK, TMS, TDI and GPOx signals to the outside, and inputs signals including TCK, TMS, TDI, TDO, GPOx and GPIy signals to the inside, wherein the TCK, TMS, TDI and GPOx signals are obtained by connecting corresponding lead wires of the corresponding output signals, and the connecting position is located between the level conversion module and the JTAG interface; x =0,1,2, \8230, m, m belongs to N, y =0,1,2, \8230, N, N belongs to N;
the JTAG interfaces are three-way interfaces, namely 3 JTAG interfaces, except one JTAG interface occupied by the device, the other two JTAG interfaces can be respectively connected with a common USB JTAG downloader and a chip supporting a JTAG protocol.
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