CN204808308U

CN204808308U - FPGACPLD procedure downloader based on programmable logic chip

Info

Publication number: CN204808308U
Application number: CN201520251877.8U
Authority: CN
Inventors: 左超
Original assignee: Zircon Opto-Electronic Technology Co Ltd
Current assignee: Zircon Opto-Electronic Technology Co Ltd
Priority date: 2015-04-24
Filing date: 2015-04-24
Publication date: 2015-11-25
Anticipated expiration: 2025-04-24

Abstract

The utility model relates to a FPGACPLD procedure downloader, especially FPGACPLD procedure downloader based on programmable logic chip. It mainly includes: USB interface, USB control chip, memory chip, programmable logic chip, level buffering chip, JTAG download the interface. The utility model discloses support the JTAG mode of debugging on line, the mode is downloaded in the initiative serial and the mode is downloaded in passive serial to support the real -time debugging of embedded logic analyser and embedded soft nuclear treater. Compare with the downloader based on the PC parallel port with traditional USB downloader, this FPGACPLD procedure downloader based on programmable logic chip has obvious advantages such as with low costs, that circuit structure is simple, programming speed is fast, support the hot plug, the voltage compatibility is strong. It is for providing a high speed, stability, low cost, convenient downloader solution based on FPGACPLD electronic system design.

Description

Based on the FPGA/CPLD Program download of programmable logic chip

Technical field

This experiment is novel relates to a kind of FPGA/CPLD Program download, particularly based on the FPGA/CPLD Program download of programmable logic chip.

Background technology

Along with SOC (system on a chip) (SoC, SystemonChip) arrival in epoch, comprise CPLD (CPLD, and field programmable gate array (FPGA ComplexProgrammableLogicDevice), FieldProgrammableGateArray) programmable logic device (PLD) (having the particular advantages at system Reprogrammable), applies more and more extensive.This has higher requirement to the downloader for programmable logic device (PLD) programming.

We can also by downloader by configuration data programming to series arrangement device (EPCS) with strengthen in configuration device (EPC).It is also the instrument of FPGA Debugging hardware and debug processor simultaneously.FPGA/CPLD downloader mainly comprises US downloader and parallel port downloader, wherein parallel port downloader its need to use parallel port interface, and current many notebook computers, even desktop computer is all no longer equipped with parallel port, and now parallel port downloader cannot use.In addition the use of parallel port does not support hot plug, and when using the debugging embedded logic analyser of parallel port downloader downloader and embedded software core processor, if the speed of exchanges data is too fast, all inevitably occurs crashing.For solving the problems of the technologies described above, USB downloader is used to have clear superiority when developing FPGA.On the one hand, the speed that downloads is obviously fast.Nowadays the capacity of FPGA has reached millions of door, even downloaded by JTAG mouth, also need for a long time, USB downloader then obviously can shorten download time.On the other hand, program debug is more convenient, even can make some real-time debugs.This point is very important when using embedded logic analyzer and debugging embedded processor.

Utility model content

FPGA/CPLD Program download based on programmable logic chip is provided, the obvious advantage such as have that cost is low, circuit structure is simple, program speed is fast, support hot plug, voltage compatibility is strong for solving the problems of the technologies described above the utility model.

In order to achieve the above object, the utility model provides following technical scheme:

Based on the FPGA/CPLD Program download of programmable logic chip, hardware system mainly comprises USB interface, USB control chip, storage chip, programmable logic chip, level buffer chip, JTAG download interface.

Wherein, described storage chip is the read-only storage chip of band electrically erasable programmable.It mainly completes function: for storing the customizing messages of USB control chip, can complete data writing and reading by (but being not limited only to) EECS, EESK, EEDATA.Its model can (but being not limited only to) be AT93C46DN chip or AT24C02C chip etc.

Wherein, described programmable logic chip is FPGA or the CPLD chip of disposable type.Mainly completing function is: complete the conversion of USB serial bus data to the programming data and instruction that meet IEEE1149.1 standard.Its model can (but being not limited only to) be XC2C256 chip, EPM3064A chip, XC3S200A chip etc.

Wherein, described its model of level buffer chip can (but being not limited only to) be: 74HC244 chip, 74LVC244 chip, MAX3378 chip, SN74AVC16T245DGGR chip.

The beneficial effects of the utility model are: provide the FPGA/CPLD Program download based on programmable logic chip, support JTAG on-line debugging pattern, initiatively serial download pattern and passive serial downloading mode, and support the real-time debug of SignalTapII or Chipscope embedded logic analyzer and NiosII or Microblaze embedded software core processor.With traditional USB downloader compared with the downloader of Based PC parallel port, this FPGA/CPLD Program download based on programmable logic chip has the obvious advantages such as cost is low, circuit structure is simple, program speed is fast, support hot plug, voltage compatibility is strong.It is for providing a kind of high speed, stable, low cost, easily downloader solution based on FPGA/CPLD electronic system design.

In order to further understand feature of the present utility model and technology contents, refer to following about detailed description of the present utility model and accompanying drawing, but accompanying drawing only provide reference and explanation use, is not used for being limited the utility model.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, by describing in detail embodiment of the present utility model, will make the technical solution of the utility model and other beneficial effect apparent.

Fig. 1 is the structural representation of the utility model based on the FPGA/CPLD Program download of programmable logic chip;

Fig. 2 based on EPM3064 programmable logic chip, FT245BLUSB control chip, the FPGA/CPLD Program download circuit theory diagrams that AT93C46DN storage chip and SN74LVC244 level buffer chip realize;

Fig. 3 is based on XC2C256 programmable logic chip, and CY7C68013USB control chip, AT24C02C storage chip adds the FPGA/CPLD Program download circuit theory diagrams of SN74AVC16T245DGGR level buffer chip.

Embodiment

For further setting forth the technological means and effect thereof that the utility model takes, be described in detail below in conjunction with preferred embodiment of the present utility model and accompanying drawing thereof.

Refer to Fig. 1-3, the first is based on EPM3064 programmable logic chip, FT245BLUSB control chip, AT93C46DN storage chip and SN74LVC244 level buffer chip downloader scheme and the second are based on XC2C256 programmable logic chip, CY7C68013USB control chip, AT24C02C storage chip add SN74AVC16T245DGGR level buffer chip realize FPGA/CPLD downloader scheme as concrete embodiment, the utility model is described in further detail.

Note this example only as wherein a kind of specific embodiments of scheme belonging to the utility model, and the EPM3064/XC2C256 programmable logic chip that it adopts, actual can be FPGA or the CPLD chip of disposable type.And the FT245BL/CY7C68013USB control chip that it adopts also can be the USB control chip comprising USB controller of disposable type.Similarly AT93C46DN/AT24C02C storage chip and SN74LVC244/SN74AVC16T245DGGR level buffer chip also can adopt the chip of other similar functions substitute, as 74HC244, MAX3378 etc.

This specific embodiments circuit theory diagrams as shown in Figure 2.It mainly comprises: USB interface, FT245BL/CY7C68013USB control chip, EPM3064/XC2C256 programmable logic chip, AT93C46DN/AT24C02C storage chip, SN74LVC244/SN74AVC16T245DGGR level buffer chip, JTAG download interface.Certainly, also comprise some peripheral circuits in schematic diagram, as crystal oscillator Y1, overcurrent fuse FUSE, LED light DS1 etc., these peripheral circuits are not the cores of this programme.

The USB interface of downloader is square opening Type B connector, it connects USB interface and the FT245BL/CY7C68013USB control chip of main frame, and FT245BL/CY7C68013USB control chip realizes the parsing of USB Physical layer and link layer protocol: receive data from host computer by USB universal serial bus on the one hand; The instruction of being sent by FPGA/CPLDJTAG interface on the other hand and data are converted to USB serial data format and pass host computer back.

FT245BL/CY7C68013USB control chip is connected to again AT93C46DN/AT24C02C storage chip and EPM3064/XC2C256 programmable logic chip AT93C46DN/AT24C02C storage chip for storing the customizing messages of USB control chip, EPM3064/XC2C256 programmable logic chip mainly comprises to the conversion of the programming data and instruction that meet IEEE1149.1 standard for completing USB serial bus data: USB serial bus data is converted to the programming data and instruction that meet IEEE1149.1 standard on the one hand, from TCK, TMS and TDI Serial output is to the FPGA/CPLD device that will programme, on the other hand, the data meeting IEEE1149.1 standard returned from the FPGA/CPLD device that will programme and instruction, from TDO serial input to USB controller, extract corresponding parallel data, and are converted into USB serial data format.

JTAG FPDP TCK, TMS, TDO and TDI of exporting from EPM3064/XC2C256 programmable logic chip are connected to SN74LVC244/SN74AVC16T245DGGR level buffer chip, and its concrete connected mode refers to the circuit theory diagrams of Fig. 2.SN74LVC244/SN74AVC16T245DGGR level buffer chip can realize from the 5V level conversion of SN74LVC244/SN74AVC16T245DGGR input/output port be 1.8V, 2.5V, 3.3V and 5.0V (determined by external circuit), thus can 1.8V be supported, the FPGA/CPLD device of 2.5V, 3.3V and 5.0V.The power supply (JTAG_Vcc) of level buffer chip is connected to the 4th pin of jtag interface, i.e. the jtag interface power supply of the required Target Board downloaded, thus realizes the Auto-matching of different target plate device voltage.

JTAG download interface adopts standard 10pin and 14pin standard interface, adopts IDC10 and IDC14 joint, and it connects level buffer chip and the required jtag interface downloading FPGA/CPLD Target Board.JTAG on-line debugging pattern supported by the FPGA/CPLD downloader that the program realizes, initiatively serial download pattern, and passive serial downloading mode, and support the real-time debug of SignalTapII or Chipscope embedded logic analyzer and examination NiosII or Microblaze processor.

The above; be only embodiment of the present utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; change can be expected easily or replace, all should be encompassed within protection domain of the present utility model.Therefore, protection domain of the present utility model should described be as the criterion with the protection domain of claim.

Claims

1. based on the FPGA/CPLD Program download of programmable logic chip, it is characterized in that, hardware system mainly comprises USB interface, USB control chip, storage chip, programmable logic chip, level buffer chip, JTAG download interface.

2. the FPGA/CPLD Program download based on programmable logic chip according to claim 1, is characterized in that, described storage chip is the read-only storage chip of band electrically erasable programmable.

3. the FPGA/CPLD Program download based on programmable logic chip according to claim 1, is characterized in that, described programmable logic chip is FPGA or the CPLD chip of disposable type.

4. the FPGA/CPLD Program download based on programmable logic chip according to claim 1, it is characterized in that, described its model of level buffer chip can (but being not limited only to) be: 74HC244 chip, 74LVC244 chip, MAX3378 chip, SN74AVC16T245DGGR chip.