CN110442986B - Method for managing server motherboard based on CPLD logic code generator - Google Patents
Method for managing server motherboard based on CPLD logic code generator Download PDFInfo
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- CN110442986B CN110442986B CN201910736508.0A CN201910736508A CN110442986B CN 110442986 B CN110442986 B CN 110442986B CN 201910736508 A CN201910736508 A CN 201910736508A CN 110442986 B CN110442986 B CN 110442986B
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Abstract
A method for managing a server motherboard based on a CPLD logic code generator, comprising: creating an integrated logical code generator based on a union of logical code generators of several different platforms; inputting parameters for a number of different platforms to an integrated logic code generator; generating, by the integrated logic code generator, standard logic modules and environment configuration parameters based on the parameters; the CPLD executes configuration parameters based on a standard logic module for managing the server motherboard. By using the method provided by the invention, the problems of high labor cost, long debugging and testing time and the like in the traditional hardware development process are solved, and the development efficiency of a hardware development team is improved.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a method for managing a server motherboard based on a CPLD logic code generator.
Background
The main board of the server is powered on, reset and a plurality of functions of partial communication interfaces and hardware management during running are required to be realized on the CPLD, and in addition, in the first test of a novel domestic platform, the debugging test can be assisted by an embedded logic analysis module of an FPGA/CPLD device. However, because the power-on/reset time sequence requirements of the domestic and foreign platforms such as x86, feiteng, shenwei and Loongson are different, and differences exist between different types of numbers under each platform, the logic design of the CPLD is difficult to be unified and standardized, so that a hardware research and development team needs to input more manpower and time cost for the special logic development of each platform, and the debugging and maintenance cost of the CPLD is also high.
In order to solve the above problems, by analyzing and summarizing various CPLD logic codes in recent years, it is found that most logic codes mainly include a power-on timing function, a reset timing function, a clock and built-in reset function, a key detection function, an IIC/SPI low-speed communication function, a PWM generation function, a metastable state coping across clock domains, and a pin parameter configuration function, and logic circuits of these subfunctions are relatively fixed, and only limited parameters have differences. The method comprises the steps of modularizing various subfunctions, optimizing corresponding digital logic circuits, designing GUI software, inputting parameters required by each function module, and directly generating a Verilog HDL code in a comprehensive style according to each parameter.
Disclosure of Invention
Therefore, an objective of the embodiments of the present invention is to provide a method for managing a server motherboard based on a CPLD logic code generator, which solves the problems of high labor cost, long debugging and testing time in the traditional hardware development process, and improves the development efficiency of the hardware development team.
Based on the above object, an aspect of an embodiment of the present invention provides a method for managing a server motherboard based on a CPLD logic code generator, including:
creating an integrated logical code generator based on a union of logical code generators of several different platforms;
inputting parameters for a number of different platforms to an integrated logic code generator;
generating, by the integrated logic code generator, standard logic modules and environment configuration parameters based on the parameters;
the CPLD executes configuration parameters based on a standard logic module for managing the server motherboard.
According to one embodiment of the invention, the number of different platforms includes an X86 platform, a Feiteng platform, a Shenwei platform, a Loongson platform.
According to one embodiment of the invention, the parameters include the number of modules, delay time, input-output logic relationship.
According to one embodiment of the invention, the standard logic module comprises a power-on time sequence control module, a reset time sequence control module, a delay module, a jitter elimination module, a metastable state coping module, an IIC module, an SPI module, a PWM output module, an LPC module and a Debug debugging auxiliary module.
According to one embodiment of the invention, an integrated logic code generator generates configuration parameters in a quick environment.
According to one embodiment of the invention, the configuration parameters include a. Pof file and a. Sof file.
According to one embodiment of the invention, generating configuration parameters based on parameters by an integrated logic code generator includes: and generating a Tcl script based on the pin numbers, the level standards and the device model of the CPLD corresponding to the input and output signals, and obtaining an executable file of the CPLD after running in a quick environment.
According to one embodiment of the invention, the parameters are entered through a GUI software platform.
In another aspect of an embodiment of the present invention, there is also provided a computer apparatus including:
at least one processor; and
a memory storing a computer program executable on a processor, wherein the processor performs any one of the methods described above when the program is executed.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, performs the method of any one of the above.
The invention has the following beneficial technical effects: the CPLD-based logic code generator management server mainboard method provided by the embodiment of the invention creates an integrated logic code generator by a union of logic code generators based on a plurality of different platforms; inputting parameters for a number of different platforms to an integrated logic code generator; generating, by the integrated logic code generator, standard logic modules and environment configuration parameters based on the parameters; the CPLD is based on the technical scheme that the standard logic module executes the configuration parameters for managing the server main board, solves the problems of high labor cost, long debugging and testing time and the like in the traditional hardware development process, and improves the development efficiency of a hardware development team.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart diagram of a method for managing a server motherboard based on a CPLD logic code generator in accordance with one embodiment of the invention;
FIG. 2 is a schematic diagram of a GUI software initial interface diagram of a logical code generator according to one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
With the above object in view, in a first aspect, an embodiment of a method for managing a server motherboard based on a CPLD logic code generator is provided. Fig. 1 shows a schematic flow chart of the method.
As shown in fig. 1, the method comprises the steps of:
creating an integrated logical code generator based on a union of logical code generators of several different platforms;
inputting parameters for a number of different platforms to an integrated logic code generator;
generating, by the integrated logic code generator, standard logic modules and environment configuration parameters based on the parameters;
the CPLD executes configuration parameters based on a standard logic module for managing the server motherboard.
Through the technical scheme, the problems of high labor cost, long debugging and testing time and the like in the traditional hardware development process are solved, and the development efficiency of a hardware development team is improved.
In a preferred embodiment of the invention, the number of different platforms includes an X86 platform, a Feiteng platform, a Shenwei platform, a Loongson platform.
In a preferred embodiment of the invention, the parameters include the number of modules, delay time, input-output logic relationship.
In a preferred embodiment of the present invention, the standard logic module includes a power-on timing control module, a reset timing control module, a delay module, a jitter elimination module, a metastable state coping module, an IIC module, an SPI module, a PWM output module, an LPC module, and a Debug auxiliary module.
In a preferred embodiment of the invention, the integrated logic code generator generates configuration parameters in a quatus environment.
In a preferred embodiment of the invention, the configuration parameters include a. Pof file and a. Sof file.
In a preferred embodiment of the present invention, generating configuration parameters based on parameters by an integrated logic code generator comprises: and generating a Tcl script based on the pin numbers, the level standards and the device model of the CPLD corresponding to the input and output signals, and obtaining an executable file of the CPLD after running in a quick environment.
In a preferred embodiment of the invention, the parameters are entered through a GUI software platform.
According to the invention, through designing the GUI software platform, input data of the graphical interface is converted into parameters of CPLD codes, including the number of modules, delay time, input-output logic relation and the like, so that the Verilog HDL codes with comprehensive styles are generated, and the quick generation of the CPLD logic codes of the server main board is realized.
As shown in fig. 2, at the GUI front end, the GUI interface of the code generator includes the following sub-windows:
clock and reset CLK & RST
Low speed communication interface options
Multiple frequency and duty cycle adjustable PWM outputs
Main board power supply key and reset key
Power-up timing sequence Power on Sequence
Reset timing sequences Sequence
Level shifting
Fixed logic level output
Device selection
Pin assignment
Verilog HDL code generation button
Tcl script code generation button
Based on the CPLD design parameters entered by the hardware engineers and system architects in the code generator GUI interface, the code generation software will generate the following Verilog-HDL standard logic modules based on the inputs:
the power-on time sequence control module: the detection of Powergood feedback signals of an external power supply chip is mainly completed, and a next-stage PowerEN enabling signal is output after accurate time delay. If multiple Powergood signals exist, the next stage of multiple power outputs are determined at the same time, and the multiple power outputs are required to be provided with the capability of logically processing AND, OR and the like, and the multiple power outputs are pushed at the same time.
A reset time sequence control module: the reset output of peripheral chips, bridge pieces and CPU of the main board is mainly completed. Considering that all reset is often finished by the power-on time sequence in an actual main board as a condition, the module mainly finishes the function of resetting peripheral equipment, a bridge piece and a CPU in sequence and strictly controlling the time interval of each path of reset signal output.
And a time delay module: and providing adjustable delay for the power-on and reset time sequence control module according to the detection result.
And the jitter elimination module is used for: the anti-shake processing of the external input (such as a mechanical key and the like) signals is provided for the power-on time sequence control module.
Metastable state handling module: for communication across clock domains, metastability needs to be suppressed as much as possible by adding a dual clock FIFO or a multi-stage shift register. The module is automatically generated when the GUI selects the communication modules of IIC/SPI/LPC and the like.
IIC module: the intelligent interface device mainly comprises an IIC interface sub-module for reading information of a temperature sensor, a sub-module for sharing a dual-port RAM by dual IIC hosts to complete communication among the hosts, a display module for directly uploading IIC information of a bridge or a CPU, and the like.
SPI module: the method is mainly used for data access of external memory chips such as Flash.
PWM output module: the method is mainly used for regulating and controlling the rotating speed of the server cooling fan.
LPC module: the method is mainly used for completing the execution of tasks such as power failure, restarting and the like of the main board in cooperation with soft reset/shutdown instructions of an operating system of a domestic CPU platform such as Shenwei.
Debug auxiliary module: the system mainly comprises a configurable sub-module for generating debugging interfaces such as nixie tube scanning output, serial port debugging information output with adjustable baud rate and level, a SignalTap embedded logic analyzer and the like on a board.
Configuration module of project (Tcl script code): the current-stage code generation tool is mainly oriented to CPLD of Intel Max series and mainly depends on the Quartz software environment provided by the authorities thereof. After the Verilog code is successfully generated, a series of operation steps such as engineering, selecting device and chip model, adding time sequence and pin constraint, logic synthesis, mapping, layout and wiring and the like are also required to generate the files of pof and sof which can be downloaded into the CPLD device. In order to simplify the operation flow of the developer, the pin numbers and level standards corresponding to the input and output signals can be directly input into the GUI interface, meanwhile, the device model of the CPLD is selected from the drop-down list, namely, a Tcl script can be generated by one key, and after the device is operated in a quick environment, the device can be directly compiled into a final file for downloading.
The logic code generator integrates input data in a GUI interface, processes the input data by means of a series of character strings and multidimensional cell arrays, writes the input data into a GUI_Verilog.v file in a parameter transmission mode, instantiates preset submodules according to an input logic relation and completes parameter transmission of the modules, and runs a Tcl script code to finally obtain a CPLD project which can be directly compiled, so that development flow of a hardware engineer is greatly simplified, and time from logic task requirements to logic code realization is shortened.
Through the technical scheme, the problems of high labor cost, long debugging and testing time and the like in the traditional hardware development process are solved, and the development efficiency of a hardware development team is improved.
In a second aspect of embodiments of the present invention, there is provided a computer apparatus comprising:
at least one processor; and
and a memory, wherein a computer program is stored and executable on a processor, and the processor executes the program to perform the method.
In a third aspect of embodiments of the present invention, there is provided a computer program product comprising instructions stored on a computer readable storage medium, which when executed by a computer, cause the computer to perform the above-described method.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
The embodiments described above, and in particular any "preferred" embodiments, are possible examples of implementations and are presented only for clarity of understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the technology described herein. All modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The embodiments described above, and in particular any "preferred" embodiments, are possible examples of implementations and are presented only for clarity of understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the technology described herein. All modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (8)
1. A method for managing a server motherboard based on a CPLD logic code generator, comprising:
creating an integrated logic code generator based on a union of logic code generators of a plurality of different platforms, wherein the plurality of different platforms comprise an X86 platform, a Feiteng platform, a Shenwei platform and a Loongson platform;
inputting parameters for the number of different platforms to the integrated logic code generator;
generating a standard logic module and environment configuration parameters based on the parameters through the integrated logic code generator, wherein the standard logic module comprises a power-on time sequence control module, a reset time sequence control module, a delay module, a jitter elimination module, a metastable state coping module, an IIC module, an SPI module, a PWM output module, an LPC module and a Debug debugging auxiliary module;
and the CPLD executes the configuration parameters based on the standard logic module for managing the server main board.
2. The method of claim 1, wherein the parameters include a number of modules, a delay time, and an input-output logic relationship.
3. The method of claim 1, wherein the integrated logic code generator generates the configuration parameters in a quatus environment.
4. The method of claim 1, wherein the configuration parameters comprise a. Pof file and a. Sof file.
5. The method of claim 1, wherein generating, by the integrated logic code generator, the configuration parameters based on the parameters comprises: and generating a Tcl script based on the pin numbers, the level standards and the device model of the CPLD corresponding to the input and output signals, and obtaining an executable file of the CPLD after running in a quick environment.
6. The method of claim 1, wherein the parameters are entered via a GUI software platform.
7. A computer device, comprising:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor performs the method of any of claims 1-6 when executing the program.
8. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, performs the method of any one of claims 1-6.
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