CN109753673A - A method of automatically generating electrifying timing sequence program - Google Patents
A method of automatically generating electrifying timing sequence program Download PDFInfo
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- CN109753673A CN109753673A CN201711092830.1A CN201711092830A CN109753673A CN 109753673 A CN109753673 A CN 109753673A CN 201711092830 A CN201711092830 A CN 201711092830A CN 109753673 A CN109753673 A CN 109753673A
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- timing sequence
- electrifying timing
- sequence program
- cpu
- automatically generating
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012163 sequencing technique Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 238000004153 renaturation Methods 0.000 description 1
Abstract
A method of automatically generating electrifying timing sequence program, comprising: count and determine using table format and adapt to the enabled sequence for powering on enable signal of CPU, described power on the mutual enabled interval of enable signal；Matlab tool reads the content in the table, according to the information recorded in the table, generates the output of verilog code, and generate corresponding .v file and pin unbound document .qsf；The .v file and pin unbound document .qsf are loaded into Quartus, then generate bit file by compiling, last programming is into CPU.The method of the invention: when electric sequence changes, the sequence of signal in corresponding table need to only be changed, so that it may generate new verilog program, improve work efficiency.Code in the also changeable Matlab implementing procedure of the present invention, generates c program or VHDL program, expands the use scope of this method.
Description
Technical field
The present invention relates to a kind of methods for automatically generating electrifying timing sequence program, belong to the technical field of circuit design control.
Technical background
Recently as the continuous development of China's electronic industry, domestic CPU is more and more widely used.It calculates flat
Platform market shows the trend that domestic CPU and import CPU run neck and neck.The electrifying timing sequence of domestic CPU is generally realized by CPLD.
For different cpu chips, it is also different to power on enabled sequence for it, this, which will cause, produces a kind of computer or clothes using different CPU are every
The problem of business device requires to redesign electrifying timing sequence, and the repeated programing work amount of Digital Logic engineer is significantly increased.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of method for automatically generating electrifying timing sequence program.
The present invention technical problem big for the repeated programing work amount of Digital Logic engineer in the prior art, utilizes
Matlab tool automatically generates electrifying timing sequence program: automatically generating verilog electrifying timing sequence code in Matlab tool, loads
Into CPLD/FPGA, so as to solve different platform, electrifying timing sequence is different, the big problem of repeated programing work amount.
Technical scheme is as follows:
A method of automatically generating electrifying timing sequence program, comprising:
It is counted and is determined using table format and adapted to the enabled sequence for powering on enable signal of CPU, described power on enabled letter
Number mutual enabled interval；
Matlab tool reads the content in the table, according to the information recorded in the table, generates verilog generation
Code output, and generate corresponding .v file and pin unbound document .qsf；
The .v file and pin unbound document .qsf are loaded into Quartus, then generate bit text by compiling
Part, last programming is into CPU.The method of the invention: when electric sequence changes, signal in corresponding table need to only be changed
Sequence, so that it may generate new verilog program, improve work efficiency.The also changeable Matlab implementing procedure of the present invention
Middle code generates c program or VHDL program, expands the use scope of this method.
Preferred according to the present invention, the method for automatically generating electrifying timing sequence program further includes being counted using table format
And determine the unconventional enabled condition of CPU.
Preferred according to the present invention, the method for automatically generating electrifying timing sequence program further includes being counted using table format
And determine pair of the enabled sequence of reset signal for adapting to CPU, the corresponding pin of reset input signal, reset output signal
Answer pin.
Preferred according to the present invention, the table format is excel table format.
Technical advantage of the invention:
The present invention need to only change the sequence of signal in corresponding table, so that it may generate new when electric sequence changes
Verilog program, improves work efficiency.Code in the also changeable Matlab implementing procedure of the present invention, generate c program or
VHDL program expands the use scope of this method.The present invention is compiled for the repeatability of Digital Logic engineer in the prior art
The technical issues of journey heavy workload, automatically generates electrifying timing sequence program using Matlab tool: giving birth to automatically in Matlab tool
It at verilog electrifying timing sequence code, is loaded into CPLD/FPGA, so as to solve different platform, electrifying timing sequence is different, weight
The big problem of renaturation programing work amount.
Detailed description of the invention
Fig. 1 is the flow chart of method described in the embodiment of the present invention；
Fig. 2 is the electrifying timing sequence figure of FT1500 series CPU described in the embodiment of the present invention.
Specific embodiment
The present invention is described in detail below with reference to embodiment and Figure of description, but not limited to this.
As shown in Figure 1, 2.
Embodiment 1,
A method of automatically generating electrifying timing sequence program, comprising:
It is counted and is determined using table format and adapted to the enabled sequence for powering on enable signal of CPU, described power on enabled letter
Number mutual enabled interval；
Matlab tool reads the content in the table, according to the information recorded in the table, generates verilog generation
Code output, and generate corresponding .v file and pin unbound document .qsf；
The .v file and pin unbound document .qsf are loaded into Quartus, then generate bit text by compiling
Part, last programming is into CPU.
Embodiment 2,
A kind of method automatically generating electrifying timing sequence program as described in Example 1, difference is, described to automatically generate
The method of electrifying timing sequence program further includes counting using table format and determining the unconventional enabled condition of CPU.
Embodiment 3,
A kind of method for automatically generating electrifying timing sequence program as described in embodiment 1,2 is distinguished and is, the automatic life
Method at electrifying timing sequence program further include using table format count and determine adaptation CPU reset signal enabled sequence,
The corresponding pin of the corresponding pin of reset input signal, reset output signal.
Embodiment 4,
A kind of method for automatically generating electrifying timing sequence program as described in embodiment 1,2,3 is distinguished and is, the table
Format is excel table format.
Application examples,
The method for automatically generating electrifying timing sequence program as described in embodiment 1-4 will power in the board design stage
In the pins corresponding relation filling excel table of enable signal, reset signal and input/output signal:
It is set to 100ms；
IO_PWR is powered on first；
When IO_PWR_PG set, VDD_CORE is powered on；
When VDD_CORE_PG set, VDDA_PCIE is powered on；
IO_PWR_EN, VDD_CORE_EN, VDDA_PCIE_EN are inserted into the excel table according to sequencing；
Matlab tool reads the excel table, by power on signal according to sequencing in the form of verilog file
Output, solves the problems, such as that repeated programing work amount is big.
Claims (4)
1. a kind of method for automatically generating electrifying timing sequence program, which is characterized in that this method comprises:
It is counted and is determined using table format and adapted to the enabled sequence for powering on enable signal of CPU, described power on enable signal phase
Enabled interval between mutually；
Matlab tool reads the content in the table, and according to the information recorded in the table, it is defeated to generate verilog code
Out, and corresponding .v file and pin unbound document .qsf are generated；
The .v file and pin unbound document .qsf are loaded into Quartus, then generate bit file by compiling, most
Programming is into CPU afterwards.
2. a kind of method for automatically generating electrifying timing sequence program according to claim 1, which is characterized in that the automatic life
Method at electrifying timing sequence program further includes counting using table format and determining the unconventional enabled condition of CPU.
3. a kind of method for automatically generating electrifying timing sequence program according to claim 1 or 2, which is characterized in that it is described from
The dynamic method for generating electrifying timing sequence program further includes that enabling for the reset signal for adapting to CPU is counted and determined using table format
Sequentially, the corresponding pin of reset input signal, reset output signal corresponding pin.
4. a kind of method for automatically generating electrifying timing sequence program according to claim 3, which is characterized in that the table lattice
Formula is excel table format.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711092830.1A CN109753673A (en) | 2017-11-08 | 2017-11-08 | A method of automatically generating electrifying timing sequence program |
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| CN201711092830.1A CN109753673A (en) | 2017-11-08 | 2017-11-08 | A method of automatically generating electrifying timing sequence program |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442986A (en) * | 2019-08-09 | 2019-11-12 | 山东超越数控电子股份有限公司 | A method of based on CPLD logical code generator management server mainboard |
| CN111610744A (en) * | 2020-04-23 | 2020-09-01 | 广州明珞汽车装备有限公司 | Logic control program generation method and system based on process time sequence and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
-
2017
- 2017-11-08 CN CN201711092830.1A patent/CN109753673A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105930186A (en) * | 2016-04-20 | 2016-09-07 | 中车株洲电力机车研究所有限公司 | Multi-CPU (Central Processing Unit) software loading method and multi-CPU-based software loading device |
Non-Patent Citations (3)
| Title |
|---|
| WFZHAOYUWEI: ""关于MATLAB自动代码生成 "", 《MATLAB论坛》 * |
| 爱码网: "》"Matlab中Excel时间序列的读取与组合——维护顺序"", 《爱码网》 * |
| 雷能芳: "DDS的Verilog设计及QuartusⅡ与Matlab联合仿真", 《现代电子技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442986A (en) * | 2019-08-09 | 2019-11-12 | 山东超越数控电子股份有限公司 | A method of based on CPLD logical code generator management server mainboard |
| CN111610744A (en) * | 2020-04-23 | 2020-09-01 | 广州明珞汽车装备有限公司 | Logic control program generation method and system based on process time sequence and storage medium |
| CN111610744B (en) * | 2020-04-23 | 2021-11-09 | 广州明珞汽车装备有限公司 | Logic control program generation method and system based on process time sequence and storage medium |
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Application publication date: 20190514 |