CN205656280U - Chip testing control circuit - Google Patents
Chip testing control circuit Download PDFInfo
- Publication number
- CN205656280U CN205656280U CN201620512448.6U CN201620512448U CN205656280U CN 205656280 U CN205656280 U CN 205656280U CN 201620512448 U CN201620512448 U CN 201620512448U CN 205656280 U CN205656280 U CN 205656280U
- Authority
- CN
- China
- Prior art keywords
- state
- foot
- tst
- chip
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses a chip testing control circuit finds three acquiescence state for the pin foot of input state in numerous pin feet of IC the insides, and an acquiescence state be output state's pin foot, then the button that finds the IC pin foot that resets, utilizes these current IC pin feet, and logic modules is decodeed to the combinatory logic module of deuterogamying, state machine and state, carries out the test control, need not design special test pin foot, do not occupy pin foot resource, be favorable to reducing the IC design cost, through cooperating one set of dedicated code decoding circuit to produce various test modes, and the conversion between the test mode need not be direct conversion through a zero clearing process, and consequently various test modes be safe and reliable, it doesn't matter between test mode production circuit and the IC internal function circuit, can not cause IC information to reveal.
Description
Technical field
This utility model relates to electronic circuit and technical field of measurement and test, is specifically related to a kind of chip testing control circuit.
Background technology
In SoC design, owing to system is more and more huger, integrated level is more and more higher, causes the manufacture of chip to become more and more difficult.Accordingly, chip yield also becomes more and more lower, and cost also becomes more and more higher.So, the most effectively improve production yield, reduce production cost and just become extremely important.Generally while considering chip functions design, also design a set of test system for chip, it is possible to chip production out after test the circuit of the every part of chip quickly and the most normally produce.
At present, being limited to IC design scale, IC test becomes more and more difficult.Generally chip all only just can be able to be used for the test pin of IC test design specialized, these pins when design IC tests when, and IC normally works when, these pins are otiose.So, will result in the waste of IC pin resource, in some instances it may even be possible to cause the increase of IC area because of these test dedicated pin of design, thus increase IC design cost.What is more, and the existence of these IC test pin also brings along some risks and potential safety hazard.
So, design a set of the most easy to use, but also the waste of IC resource will not be brought, also will not bring the IC test mode circuit of the increase of IC cost, just become the most meaningful.
Utility model content
This utility model carrys out this problem of increase of the IC wasting of resources and possible IC cost for special test pin tape present in existing IC measuring technology, it is proposed that a kind of chip testing control circuit.This utility model is realized by techniques below scheme:
A kind of chip testing control circuit, belongs to a part for chip self, and described chip includes that three default conditions are the pin foot of input state, a button reset pin foot and a power-on reset signal end POR；It is characterized in that: this chip testing control circuit includes combination logic module, state machine and state decoding logic module, the pin foot that three default conditions are input state of described chip is multiplexed with the TST_CK foot of testing and control respectively, TST_EN foot, TST_IN foot, a button reset pin foot of described chip is multiplexed with the P_RST foot of testing and control；The reset terminal of combination logic module connects described P_RST foot, controls Enable Pin and connects described TST_EN foot；The electrification reset end of state machine connects described reset signal end POR, and signal input part connects the signal output part of combination logic module, and data input pin connects described TST_IN foot, and input end of clock connects described TST_CK foot；The electrification reset end of state decoding logic module connects described reset signal end POR, the outfan of state output terminal connection status machine, data input pin connects described TST_IN foot, input end of clock connects described TST_CK foot, the feedback signal input terminal of state machine feedback signal output connection status machine, at least one test mode enables in signal output part connects chip respectively and is test for each functional module.
As concrete technical scheme, the outside power-on reset signal pin of that power-on reset signal end POR is chip of described chip.
As concrete technical scheme, the internal power-on reset signal port of that power-on reset signal end POR is chip of described chip.
As further technical scheme, chip includes the pin foot that default conditions are output state, is multiplexed with the TST_OUT foot of testing and control；Described state decoding logic module also has testing and control outfan, connects the described TST_OUT foot of chip.
As concrete technical scheme, the concrete logic of described combination logic module is: when P_RST signal be 1 or TST_EN be 1 time, state machine input signal 1 is a synchronous logic reset signal, by test pattern resets to original state；When P_RST is 0, and when TST_EN is 0, test pattern state machine starts to proceed by State Transferring according to input TST_IN and state machine feedback signal.
As concrete technical scheme, the state decoding logic of described state decoding logic module is: state decoding logic is according to state machine state and input signal TST_IN, by the serial signal sampling of input, obtain the command sequence of test pattern, then judge that any test pattern enables signal according to the value of command sequence effective.
The beneficial effects of the utility model are: utilize existing IC pin foot, it is not necessary to design special test pin foot；It is not take up pin foot resource, advantageously reduces IC design cost；Devising a set of special coding/decoding circuit to produce various test pattern, and the conversion between test pattern needs through a clearing process, be not directly conversion, the most various test patterns are safe and reliable；Between test pattern generation circuit and IC inner function circuit, it doesn't matter, does not results in IC information leakage.
Accompanying drawing explanation
The block diagram of the chip testing control circuit that Fig. 1 provides for this utility model embodiment.
The state transition diagram of state machine in the chip testing control circuit that Fig. 2 provides for this utility model embodiment.
In the test control method that Fig. 3 provides for this utility model embodiment, test pattern enables signal TSTMOD and produces and the schematic diagram of input coding.
The schematic diagram of test pattern readout in the test control method that Fig. 4 provides for this utility model embodiment.
Detailed description of the invention
For an IC, pin foot is the basis realizing IC function, and the power supply of IC is connected to external power source by pin foot, and plug-in device is also to be connected by the pin foot of IC to realize.IC tests when, test signal is also that the pin foot by IC inputs or exports.And the pin foot of IC typically has default conditions, i.e. pin foot is acquiescence input state, or is defaulted as output state, or is defaulted as high-impedance state (neither input state is not output state).For this utility model, need the pin foot finding three default conditions to be input state inside numerous pin feet of IC, one default conditions is the pin foot of output state, then finds the button reset pin foot (general IC can have these pin feet) of an IC.
As shown in Figure 1, the chip testing control circuit that the present embodiment provides, it belongs to a part for chip self, including combination logic module, state machine and state decoding logic module, the pin foot that three default conditions are input state of described chip is multiplexed with the TST_CK foot of testing and control respectively, TST_EN foot, TST_IN foot, one button reset pin foot of described chip is multiplexed with the P_RST foot of testing and control, and default conditions are the TST_OUT foot that the pin foot of output state is multiplexed with testing and control.
The reset terminal of combination logic module connects described P_RST foot, controls Enable Pin and connects described TST_EN foot；The electrification reset end of state machine connects described reset signal end POR, and signal input part connects the signal output part of combination logic module, and data input pin connects described TST_IN foot, and input end of clock connects described TST_CK foot；The electrification reset end of state decoding logic module connects described reset signal end POR, the outfan of state output terminal connection status machine, data input pin connects described TST_IN foot, input end of clock connects described TST_CK foot, the feedback signal input terminal of state machine feedback signal output connection status machine, at least one test mode enables in signal output part connects chip respectively and is test for each functional module, described state decoding logic module also has testing and control outfan, connects the described TST_OUT foot of chip.In the present embodiment, power-on reset signal end POR is an internal power-on reset signal port of chip, and for chip field, this power-on reset signal end POR can also be an outside power-on reset signal pin of chip.
State machine input signal 1 is then produced by combination logic by input pin foot P_RST and TST_EN.The concrete logic of this combination logic module is: when P_RST signal be 1 or TST_EN be 1 time, state machine input signal 1 is a synchronous logic reset signal, by test pattern resets to original state；When P_RST is 0, and when TST_EN is 0, test pattern state machine starts to proceed by State Transferring according to input TST_IN and state machine feedback signal, and the state transition diagram of state machine is as shown in Figure 2.
Wherein, carry out decoding the combination of the multiple signals obtained as it is shown in figure 1, state machine feedback signal is the state according to state machine, be that each different of conversion between different conditions redirect condition for state machine.Meanwhile, each test pattern enables signal is also that the state decoding according to state machine obtains.State decoding logic is described as follows: state decoding logic is according to state machine state and input signal TST_IN, by the serial signal sampling of input, obtain command sequence WR [5:0] of test pattern, then judge that any test pattern enables signal according to the value of WR [5:0] effective.So, it is mutual exclusion that all of test pattern enables between signal, i.e. any instant, and being only possible to a test pattern and having enabled signal is height, represents that effectively, it is all 0 that other test patterns enable signal, represents invalid.After the input of P_RST pin foot becomes 1 from 0, whole chip will enable signal according to these test patterns and start testing of each module.
More than understand, above-described embodiment lists a kind of coded system.It practice, by being adjusted coding circuit, the most multiple different coded system can select, but basic thought is all based on mentioned above existing being defaulted as of IC that utilize and inputs pin, realizes test pattern in conjunction with certain coding circuit and produces circuit.Benefit is to need not special test pin foot, will not bring the increase of IC cost, easily realizes test purpose simultaneously, and owing to test mode circuit and IC inner function circuit do not have any relation, can cause information leakage without worry.
The present embodiment state by the serial input signals on sampling TST_IN and to state machine carries out decoding and judges, state machine just can carry out state transition according to different situations, complete each test pattern and enable clearing (0) or the set (1) of signal, thus allow IC exit or enter certain test pattern.Concrete IC test control method is presented herein below realize.
Button reset pin foot P_RST, default conditions are pull-up high level, represent when low level and reset IC.And TST_CK represents that input clock, TST_EN represent that control enables signal, TST_IN represents input data.When P_RST signal is low, in addition to test pattern state machine, the circuit of other parts of system is in reset state.Being poured into by external clock by TST_CK pin, TST_EN and TST_IN is then sampled input state machine at the rising edge of TST_CK.Shown in Fig. 3, when TST_EN signal is high level, state machine is in IDLE state, and each test mode signal keeps constant.When TST_EN signal is low level, state machine is by sampling TST_IN signal intensity, by different coded combinations, produces different test patterns and enables signal.These test patterns are enabled signal and just can only be cancelled by the specific coding on state machine sampling TST_IN, this guarantees IC stability after entering test pattern.After entering certain test pattern, TST_EN signal is become high level, then by also input high level on P_RST signal, i.e. can start testing of IC function.Illustrate as a example by the coding of a kind of testing scanning chain pattern below.
Fig. 3 lists a kind of test pattern and enables the generation process of signal (representing with signal TSTMOD).Wherein, POR represents power-on reset signal, low effectively；P_RST represents external key reset signal, is also low effectively；TST_EN, TST_CK, TST_IN are respectively above-mentioned input pin foot signal；TST_OUT is output pin foot signal, belongs to debug purposes, only uses validation test pattern enable signal is the most correct when, need not use in practical operation.It will be seen that when input signal TST_IN inputs according to certain encoding law, test pattern state machine is changing according to input signal TST_IN.After a specific complete coded sequence has inputted, test pattern enables signal TSTMOD and decodes according to the value of the WR [5:0] in Fig. 1, high level can be become by low level, represent that IC enters this kind of test pattern, and WR [5:0] is the value of the ad-hoc location in the write sequence intercepted.Then after P_RST signal being become high level input by low level input, it is possible to start the test operation under this kind of test pattern.
It should be noted that the transformational relation between state change and each state of internal state machine is also required to define clear, otherwise, state machine is easily made mistakes, and can make troubles the test of IC.This utility model is presented herein below for some explanations of change between state machine and test pattern:
One, test pattern enables how signal resets:
1.1, removed by POR.POR is a powering up reset signal, and before having powered on, por signal is low level, represents reset state, and it is 0 that all test patterns enable signal；After having powered on, por signal becomes high level, and reset is cancelled.
1.2, by Pin Reset (P_RST) signal and input specific sequence:
1.2a, low level will be pulled under Pin Reset (P_RST).
1.2b, the input of TST_EN is become 0. from 1
1.2c, from TST_IN input 18 ' b101010101010000001 sequences, this can by all of test pattern enable signal reset.
1.2d, release Pin Reset (P_RST), be allowed to become high level.
Two, how to change between different test patterns:
2.1, above a kind of test pattern resets；
2.2, low level will be pulled under Pin Reset (P_RST)；
2.3, the input of TST_EN is become 0 from 1；
2.4, inputting target test mode data sequence from TST_IN, new test pattern enables signal and becomes 1 from 0, enters new test pattern；
2.5, release Pin Reset (P_RST), is allowed to become high level.
Additionally, in order to the test pattern checking write is the most correct, the present embodiment also defines a kind of test pattern and reads status command, reads state as shown in Figure 4.
We may notice that from Fig. 3 and Fig. 4, Fig. 3 is write data sequence, produces test pattern indication signal, Fig. 4 is by input particular data sequence, the state series read-out of test pattern is come, releases from TST_OUT foot and test, enable signal with exact p-value pattern the most correct.Additionally, need to remind especially is, another kind of test pattern (carrying out decoding according to the value of WR Fig. 1 [3:0] to determine) is entered, it is necessary to first the test pattern that former writes is enabled signal removal, write new test pattern sequence more from a kind of test pattern.And also refer to above the mode removed, have a two ways: power-on reset signal POR be 0 or TST_EN signal be 0, P_RST be 0, POR on TST_IN, input 18 ' b101010101010000001 sequences, this data sequence and TST_CK rising edge synch when of being 1.
Embodiment described above only have expressed several exemplary embodiment of the application, and it describes more concrete and detailed, but therefore can not be interpreted as the restriction to the application the scope of the claims.It should be pointed out that, it will be apparent to those skilled in the art that under the concept thereof without departing from the application, the some deformation made or improvement, broadly fall into the protection domain of the application.
Claims (6)
1. a chip testing control circuit, belongs to a part for chip self, and described chip includes that three are write from memory
Recognize the pin foot that state is input state, a button reset pin foot and a power-on reset signal end POR；
It is characterized in that: this chip testing control circuit includes combination logic module, state machine and state decoding logic
Module, the pin foot that three default conditions are input state of described chip is multiplexed with testing and control respectively
TST_CK foot, TST_EN foot, TST_IN foot, a button reset pin foot of described chip is multiplexed with
The P_RST foot of testing and control；The reset terminal of combination logic module connects described P_RST foot, controls to enable
End connects described TST_EN foot；The electrification reset end of state machine connects described reset signal end POR, letter
Number input connects the signal output part of combination logic module, and data input pin connects described TST_IN foot, time
Clock input connects described TST_CK foot；The electrification reset end of state decoding logic module is replied by cable described in connecting
Position signal end POR, the outfan of state output terminal connection status machine, data input pin connects described TST_IN
Foot, input end of clock connects described TST_CK foot, state machine feedback signal output connection status machine anti-
Feedback signal input, at least one test mode enables in signal output part connects chip respectively and is test for respectively
Functional module.
Chip testing control circuit the most according to claim 1, it is characterised in that described chip upper
Reset signal end POR is an outside power-on reset signal pin of chip.
Chip testing control circuit the most according to claim 1, it is characterised in that described chip upper
Reset signal end POR is an internal power-on reset signal port of chip.
Chip testing control circuit the most according to claim 1, it is characterised in that described chip includes
One default conditions is the pin foot of output state, is multiplexed with the TST_OUT foot of testing and control；Described shape
State decoding logic module also has testing and control outfan, connects the described TST_OUT foot of chip.
5. according to the chip testing control circuit described in Claims 1-4 any one, it is characterised in that
The concrete logic of described combination logic module is: when P_RST signal be 1 or TST_EN be 1 time, state
Machine input signal 1 is a synchronous logic reset signal, by test pattern resets to original state；
When P_RST is 0, and when TST_EN is 0, test pattern state machine start according to input TST_IN with
And state machine feedback signal proceeds by State Transferring.
6. according to the chip testing control circuit described in Claims 1-4 any one, it is characterised in that
The state decoding logic of described state decoding logic module is: state decoding logic be according to state machine state with
And input signal TST_IN, by the serial signal sampling of input, obtain the command sequence of test pattern, then
It is effective that value according to command sequence judges that any test pattern enables signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620512448.6U CN205656280U (en) | 2016-05-30 | 2016-05-30 | Chip testing control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620512448.6U CN205656280U (en) | 2016-05-30 | 2016-05-30 | Chip testing control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205656280U true CN205656280U (en) | 2016-10-19 |
Family
ID=57404908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620512448.6U Active CN205656280U (en) | 2016-05-30 | 2016-05-30 | Chip testing control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205656280U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105974299A (en) * | 2016-05-30 | 2016-09-28 | 珠海市微半导体有限公司 | Chip test control circuit and method thereof |
| CN108508352A (en) * | 2018-04-19 | 2018-09-07 | 中国电子科技集团公司第五十八研究所 | A kind of Test code generation circuit |
| CN110941323A (en) * | 2018-09-25 | 2020-03-31 | 广达电脑股份有限公司 | Computer implementation method, computing device and computer readable storage medium |
| CN115078967A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Mode generation method, generator and test circuit for chip test |
-
2016
- 2016-05-30 CN CN201620512448.6U patent/CN205656280U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105974299A (en) * | 2016-05-30 | 2016-09-28 | 珠海市微半导体有限公司 | Chip test control circuit and method thereof |
| CN105974299B (en) * | 2016-05-30 | 2019-08-09 | 珠海市一微半导体有限公司 | Chip testing control circuit and its method |
| CN108508352A (en) * | 2018-04-19 | 2018-09-07 | 中国电子科技集团公司第五十八研究所 | A kind of Test code generation circuit |
| CN110941323A (en) * | 2018-09-25 | 2020-03-31 | 广达电脑股份有限公司 | Computer implementation method, computing device and computer readable storage medium |
| US10921870B2 (en) | 2018-09-25 | 2021-02-16 | Quanta Computer Inc. | System and method for hybrid power supply |
| CN115078967A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Mode generation method, generator and test circuit for chip test |
| CN115078967B (en) * | 2022-06-15 | 2024-02-20 | 上海类比半导体技术有限公司 | Pattern generation method, generator and test circuit for chip test |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105974299B (en) | Chip testing control circuit and its method | |
| CN205656280U (en) | Chip testing control circuit | |
| CN102289419A (en) | Multiplex SOC(system on a chip) integrated circuit for functional interface and debugging interface | |
| CN104657245B (en) | The automatically generating device of module level UVM verification platform based on AMBA bus | |
| CN106531654B (en) | A kind of chip input pin test method and device | |
| CN204884160U (en) | Ammeter data collection station detecting system | |
| CN104809043A (en) | Connection test method and device of motherboard CPU (Central Processing Unit) slot based on boundary scan | |
| CN107688521A (en) | A kind of server power supply detects circuit and detection method in place | |
| CN102520272A (en) | Test system of power down protection function of smart card and method | |
| CN109298266A (en) | Test macro, test method, test device and storage medium | |
| CN110109043A (en) | Electric energy meter detection method, detection terminal and computer readable storage medium | |
| CN208077394U (en) | A kind of the communication test plate and communication test system of concentrator communication module | |
| CN108121842A (en) | The verification method and device of the low energy consumption operation mode of multiprocessor system chip | |
| CN206353192U (en) | A kind of safety circuit for chip testing | |
| CN109709471A (en) | A kind of test fixture, the test method and device of fingerprint mould group | |
| CN203324427U (en) | Wiring harness on-off detector | |
| CN100545816C (en) | Double-interface smart card simulation card | |
| CN102193898B (en) | CPU core unlocking device applied to computer system | |
| CN211352215U (en) | 5G communication module test assembly and computer equipment | |
| CN106200623B (en) | The semi-physical simulation test device of reactor core measuring system logic module | |
| CN109753673A (en) | A method of automatically generating electrifying timing sequence program | |
| CN103345610A (en) | Device and method for quickly verifying data integrity of intelligent card | |
| CN210666782U (en) | System and device for verifying electric energy meter management chip | |
| CN206921076U (en) | Debugging device for M.2 interface | |
| CN102156256B (en) | Burning test method of combination and encapsulation of microprogrammed control unit (MCU) and touch integrated circuit (IC) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |