CN102608517A - Method for rapidly creating integrated circuit test program package - Google Patents
Method for rapidly creating integrated circuit test program package Download PDFInfo
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- CN102608517A CN102608517A CN2012100359636A CN201210035963A CN102608517A CN 102608517 A CN102608517 A CN 102608517A CN 2012100359636 A CN2012100359636 A CN 2012100359636A CN 201210035963 A CN201210035963 A CN 201210035963A CN 102608517 A CN102608517 A CN 102608517A
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Abstract
The invention discloses a method for rapidly creating an integrated circuit test program package, which comprises the following steps of: (1) a step of generating a configuration file; (2) a step of trimming test timing; (3) a step of converting a vector; and (4) a step of compiling a testing file. According to the invention, a signal name can be extracted from the VCD (Video Compact Disc) simulation vector; the error is avoided being introduced by manual input; by timing trimming before conversion, the workload of compiling and debugging is reduced; by adopting a batch conversion mode, the manual intervention is avoided and the interruption time of the conversion process is saved; timing information is extracted in a variable representation mode and the method can be directly used for down debugging or overclock testing of a DUT (Device Under Test).
Description
Technical field
The present invention relates to ic test technique, relate in particular to a kind of fast method of creating the integrated circuit testing routine package.
Background technology
Test is a requisite important step in integrated circuit (Integrated Circuit the is called for short IC) industry, and it is applied in the IC design, makes, encapsulates, tests overall process.Test program development is the condition precedent of test, and any a IC design must first development and testing program be tested, verified after accomplishing, and continues to optimize design according to test result, produces in batches at last and uses.The test program development process of integrated circuit is actually a process of creating test program package; It is one will the side of design the artificial vector that generates of emulation convert the process of the test vector of ATE (Automatic Test Equipment is called for short ATE) professional format to.Artificial vector can have multiple form, and like VCD, EVCD, WGL, TDL, STIL, what the most often adopt at present is the artificial vector of VCD form.Along with the hyundai electronics fast development of information technology, the IC design level makes rapid progress, and IC scale, integrated level, complexity improve constantly, and test program development faces increasing difficulty.A large scale integrated circuit is the test of SOC(system on a chip) (System-on-Chip, be called for short SoC) particularly, generally needs tens even the test vector of hundreds of, and the test program development process is difficult.
The establishment of integrated circuit testing routine package, the ATE platform that need use according to when test is changed, is compiled test vector.If once conversion is unsuccessful, then need carry out conversion second time, get nowhere again, carry out for the third time, up to success or find other solution route.Therefore, creating test program package is a process that wastes time and energy, and possibly influence the test development cycle, and then influence the Time To Market of IC.The test program package of integrated circuit generally comprises following four major parts at least.First is passage setting (configuration), is used to define the sequence number, title, I/O attribute, channel number of each input/output signal of measured device (Device Under Test, be called for short DUT) etc.; Second portion is level setting (level), is used to define the height/low level of DUT input signal, the height/low level of output signal, the load model of output signal etc.; Third part is sequential setting (timing), is used to define the sequential and the waveform of each signal of DUT; The 4th part is that vector is provided with (vector), with sequential mapping is set, and combination generates resolution chart (Test Pattern).
Existing implementation is to adopt manual method to create test program package, specifically is at first to adopt manual input mode in the special software of ATE test macro, to carry out passage setting and level setting; Utilize crossover tool to do the conversion of sequential and vector then; Call compilation tool by hand again, according to the information correction sequential and the vector of real-time prompting in the compilation process, according to the quantity of simulation document; Repeat this transfer process and pass through, form a complete test program package at last until all compilings.Adopt manual method to create the integrated circuit testing routine package, have many shortcomings.The first, when adopting manual input mode that passage and level are set, because the DUT signal pin is numerous, tens three, 400 at most at least, manual mode is very easily made mistakes, and need constantly check, debug, and wastes time and energy.The second, when simulation document is carried out sequential with the vector conversion, can only carry out one by one, and need in the end the procedure file (DVC form) that generates to be carried out manual merging.The 3rd; Procedure file (DVC and AVC form) to conversion generates is carried out compile time; Because the very high and complex time of temporal resolution of simulation document, and the timing of ATE test macro is along quantity and waveform limited amount, as in the field of business belong to high-end Verigy V93000 SOC Series (being called for short V93000) test macro can only have at most 8 drivings along, 6 relatively edges, 256 waveforms; Therefore; Usually can face regularly the problem that exceeds the ATE hardware constraints along quantity and waveform quantity after the conversion, this just requires the slip-stick artist to have abundant test development and commissioning experience, under the prerequisite that does not influence the DUT temporal characteristics; Constantly the DVC file is carried out the edge and merge, compile with vector up to all sequential and pass through.The 4th, the complex time of each signal and having nothing in common with each other in the test program package, corresponding Time Created, retention time are also different, can't be during last ATE on-line debugging to regularly regulating or handle along unifying, test procedure is debugged extremely difficult.The 5th, all signal frequencies all are single fixing during the test procedure operation, and appropriate change DUT frequency of operation can't directly be used for frequency reducing debugging or the overclocking test of DUT as required.Therefore, adopting manual method to create test program package wastes time and energy, and test development efficient is low, is difficult to satisfy the objective demand that the modern IC R&D cycle is short, the test program development difficulty is big.
Summary of the invention
To the shortcoming of prior art, the purpose of this invention is to provide a kind of fast method of creating the integrated circuit testing routine package, solving classic method needs that the Test Engineer constantly carries out manual intervention, test development efficient is low and the problem of test procedure debug difficulties.
To achieve these goals, technical scheme of the present invention is: a kind of fast method of creating the integrated circuit testing routine package, and it comprises: the step that (1) configuration file generates; (2) step of test sequence pruning; (3) step of vector conversion; (4) step of test file compiling.
The step that configuration file generates comprises: from the VCD artificial vector, extract signal name and create profile template; The ATE hardware corridor that uses according to the pin sequence number or when sitting label, I/O attribute and the design of test interface plate; In template, write the configuration file that forms tabular form, utilize configuration file to generate config file and level file that the ATE testing software can directly call at last.
The step that test sequence is pruned comprises: the test period according to input prunes the VCD artificial vector, adopts nearby principle to merge the edge automatically, and the file after the pruning remains the VCD form.
The step of vector conversion comprises: adopt batch processing method during the design of vector conversion top layer; Convert each VCD artificial vector into DVC and AVC file and merging in the end one by one; Discern and processing two-way signaling and bus form signal, and time sequence information is extracted with the variable characteristic manner.
The step of test file compiling comprises: adopt REPEAT-Mode that the AVC file is compressed with back-pressure according to the debugging needs before the compiling and contract; Compile time at first is compiled as the timing file that ATE can directly call with the DVC file after the vector conversion; Through after again the AVC file after the vector conversion is compiled as the vector file that ATE can directly call, form complete test program package.
Compared with prior art, the present invention can extract signal name from the VCD artificial vector, avoids manual input to introduce mistake; Prune through the sequential before changing, reduce the workload of compiling and debugging, through taking conversion regime in batches; Avoid manual intervention; Save the break period of transfer process, the present invention extracts time sequence information with the variable characteristic manner, can directly be used for frequency reducing debugging or the overclocking test of DUT.
Description of drawings
Below in conjunction with accompanying drawing the present invention is done further detailed description.
Fig. 1 is a FB(flow block) of the present invention.
Fig. 2 is a configuration file format synoptic diagram of the present invention.
Embodiment
See also Fig. 1, the step that the present invention creates the fast method of integrated circuit testing routine package comprises following four parts:
First is that configuration file generates.Configuration file generates and at first from the VCD artificial vector, extracts signal name; Create profile template; According to pin sequence number in the DUT product manual (Specification) or sit label, I/O attribute, and the ATE hardware corridor that uses during the design of test interface plate, the formation configuration file in template, write; Form is a tabular form, like mistake! Do not find Reference source.Shown in.At last, utilize configuration file to generate config file and level file that the ATE testing software can directly call.
Second portion is the pruning of test sequence.It mainly is the test period according to input that test sequence is pruned, and adopts four kinds of optional trim modes, and the VCD artificial vector is pruned.Test sequence is pruned and is adopted nearby principle to merge the edge, but does not hinder DUT to keep enough Time Created, retention time and propagation delay times.File after the pruning still remains the VCD form, and convenient electric design automation (Electronic Design Automatic the is called for short EDA) instrument that uses is checked resolution chart.
Third part is the vector conversion.Adopt batch processing method during the design of vector conversion top layer, convert each VCD artificial vector into DVC and AVC file one by one, and in the end merge automatically.Can discern and handle two-way signaling and bus form signal automatically during the vector conversion, and with the variable characteristic manner time sequence information extracted, the frequency of test procedure is adjustable after guaranteeing to convert.
The 4th part is the test file compiling.Before the test file compiling,, adopt REPEAT-Mode that the AVC file is compressed with back-pressure and contract according to the debugging needs.Compile time can be selected the program compiler of 6 kinds of X-Modes mode invocation ATE for use; At first the DVC file after the vector conversion is compiled as the timing file that ATE can directly call; Through after again the AVC file after the vector conversion is compiled as the vector file that ATE can directly call, form complete test program package.
The present invention is directed to the test vector conversion links in the integrated circuit testing program development process; The utilization modular design; Through 4 steps such as configuration file generation, test sequence pruning, vector conversion, test file compilings; Realize of the automatic conversion of VCD form artificial vector, and create test program package automatically to test vector.The method of the application of the invention; Can effectively reduce integrated circuit testing development technique threshold, improve test program development efficient, cost when saving cost of human resources and ATE machine for test company; Also can shorten time to market (TTM) simultaneously for chip design company accelerates test development speed.Method of the present invention can realize through the exploitation wscript.exe.The present invention can use patterned way, is applied to two kinds of operating system platforms of HP-UNIX and LINUX simultaneously.
Be example with the test procedure of developing certain model ASIC circuit below, the beneficial effect that the present invention brings is described.This circuit belongs to totally digital circuit, and about 200,000 of scale adopts the QFP100 encapsulation, 80 of significant figure pins.This circuit adopts the artificial vector of 6 VCD forms to test, and each step consumed time statistics of test program development process is as shown in table 1.
Table 1 statistics that expends time in
Statistics is calculated this test program development improved efficiency (895-627) ÷ 895=29.9% according to expending time in.In addition, adopt batch conversion method of the present invention, the project that, switching time many to the artificial vector file is long can avoid classic method to need manual intervention by workstation uninterrupted conversion in 24 hours, can't make full use of the non-working time uninterruptedly to change.Also have, adopt sequential pruning method of the present invention, the test vector sequential edge of generation is neat, and has adopted the variable characteristic manner, and the test procedure debugging efficiency is high.
Claims (5)
1. a fast method of creating the integrated circuit testing routine package is characterized in that it comprises: the step that (1) configuration file generates; (2) step of test sequence pruning; (3) step of vector conversion; (4) step of test file compiling.
2. the fast method of establishment integrated circuit testing routine package according to claim 1; It is characterized in that; The step that configuration file generates comprises: from the VCD artificial vector, extract signal name and create profile template; The ATE hardware corridor that uses according to the pin sequence number or when sitting label, I/O attribute and the design of test interface plate; In template, write the configuration file that forms tabular form, utilize configuration file to generate config file and level file that the ATE testing software can directly call at last.
3. the fast method of establishment integrated circuit testing routine package according to claim 1; It is characterized in that; The step that test sequence is pruned comprises: the test period according to input prunes the VCD artificial vector, adopts nearby principle to merge the edge automatically, and the file after the pruning remains the VCD form.
4. the fast method of establishment integrated circuit testing routine package according to claim 1; It is characterized in that; The step of vector conversion comprises: adopt batch processing method during the design of vector conversion top layer; Convert each VCD artificial vector into DVC and AVC file and merging in the end one by one, discern and processing two-way signaling and bus form signal, and time sequence information is extracted with the variable characteristic manner.
5. the fast method of establishment integrated circuit testing routine package according to claim 1; It is characterized in that; The step of test file compiling comprises: adopt REPEAT-Mode that the AVC file is compressed with back-pressure according to the debugging needs before the compiling and contract; Compile time at first is compiled as the timing file that ATE can directly call with the DVC file after the vector conversion, through after again the AVC file after the vector conversion is compiled as the vector file that ATE can directly call, form complete test program package.
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Cited By (8)
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| CN102929627A (en) * | 2012-10-29 | 2013-02-13 | 无锡江南计算技术研究所 | Automatic testing program generating method based on ATE (Automatic Test Equipment) and ATE testing method |
| CN109709473A (en) * | 2019-01-29 | 2019-05-03 | 无锡中微腾芯电子有限公司 | A kind of method and system for 3D-SiP chip testing vector compression |
| CN105209925B (en) * | 2013-04-16 | 2019-05-07 | 爱德万测试公司 | For debugging the computer implemented method and system of the program of automation devices test |
| CN110632499A (en) * | 2019-09-23 | 2019-12-31 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN111426945A (en) * | 2020-03-25 | 2020-07-17 | 北京中电华大电子设计有限责任公司 | Test method for improving chip test efficiency |
| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112710947A (en) * | 2020-12-22 | 2021-04-27 | 上海华岭集成电路技术股份有限公司 | ATE-based functional test method and tool |
| CN112949233A (en) * | 2021-03-08 | 2021-06-11 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
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Cited By (12)
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| CN102929627A (en) * | 2012-10-29 | 2013-02-13 | 无锡江南计算技术研究所 | Automatic testing program generating method based on ATE (Automatic Test Equipment) and ATE testing method |
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| CN109709473A (en) * | 2019-01-29 | 2019-05-03 | 无锡中微腾芯电子有限公司 | A kind of method and system for 3D-SiP chip testing vector compression |
| CN109709473B (en) * | 2019-01-29 | 2021-05-28 | 无锡中微腾芯电子有限公司 | Method and system for compressing test vector of 3D-SiP chip |
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| CN110632499B (en) * | 2019-09-23 | 2021-04-23 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN111426945A (en) * | 2020-03-25 | 2020-07-17 | 北京中电华大电子设计有限责任公司 | Test method for improving chip test efficiency |
| CN111596200A (en) * | 2020-05-25 | 2020-08-28 | 上海岱矽集成电路有限公司 | Integrated circuit tester |
| CN112710947A (en) * | 2020-12-22 | 2021-04-27 | 上海华岭集成电路技术股份有限公司 | ATE-based functional test method and tool |
| CN112949233A (en) * | 2021-03-08 | 2021-06-11 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
| CN112949233B (en) * | 2021-03-08 | 2024-02-27 | 北京士昌鼎科技有限公司 | Automatic development method and device of FPGA chip and electronic equipment |
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Application publication date: 20120725 |