CN110968004B - Cable test system based on FPGA prototype verification development board - Google Patents
Cable test system based on FPGA prototype verification development board Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention discloses a Cable test system and a method based on an FPGA prototype verification development board, wherein the system comprises an initial self-test module, a pre-test module and a terminal test module; acquiring and transmitting information of a development board tested by a user through a pre-test module, acquiring an Ethernet IP address, encrypting and transmitting the IP address through the Ethernet; the test of the terminal test module is started, whether data loopback exists or not is detected, whether connection lines are connected or not is judged, if no loopback exists, the interface is not connected through the connection lines, if the test finds a pair of links through representation, a final test result is displayed in a self-test program result list and output to a user, the connection condition of Cable interface connection lines is detected rapidly, the development and design efficiency of the user is improved, and the problem in the background technology can be solved effectively.
Description
Technical Field
The invention relates to the technical field of development board testing, in particular to a Cable testing system and method based on an FPGA prototype verification development board.
Background
The development board (board) is a circuit board for embedded system development, and includes a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, and an external resource interface. The development board is generally customized by an embedded system developer according to development requirements, and can also be researched and designed by a user. The development board is used for a beginner to know and learn hardware and software of the system, and meanwhile, a part of the development board also provides a basic integrated development environment, software source codes, a hardware schematic diagram and the like. Common development boards include 51, ARM, FPGA and DSP development boards.
The development board is a circuit board for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. In a general embedded system development process, hardware is generally divided into two platforms, one is a development platform (host), and the other is a target platform (target), i.e. a development board. The development platform described herein refers to a computer connected to a target platform through a transmission interface, such as a serial port (RS-232), USB, parallel port, or network (Ethernet). Common development boards include 51, ARM, FPGA and DSP development boards.
In the process of developing and designing the board, the connection cable needs to be tested, so that the subsequent work is ensured to be normally carried out, time and labor are wasted through a one-by-one testing mode, and the use requirement cannot be met.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a Cable test system and method based on an FPGA prototype verification development board, which can be used for rapidly detecting the connection condition of Cable interface connecting wires, facilitating a user to rapidly develop design based on a plurality of FPGAs and chip design with high complexity, accelerating the development process of SOC products and effectively solving the problems provided by the background technology.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a Cable test system based on FPGA prototype verification development board includes:
the starting self-testing module is used for providing a display dialog box for a user and displaying a testing result after the connection condition of the connector is preliminarily detected;
the pre-test module is used for acquiring and transmitting information of a development board tested by a user and transmitting the information through Ethernet;
and the terminal test module is used for detecting whether data loopback exists after the communication with the initial self-test module so as to judge whether the connection line is connected or not and outputting a final test result to a user.
Further, the pre-measurement module further comprises:
an acquisition unit configured to acquire an IP address of an ethernet;
the IP address encryption unit is electrically connected with the acquisition unit and is used for encrypting the acquired IP address;
and the uploading transmission unit is electrically connected with the IP address encryption unit and is used for transmitting the IP address encrypted by the IP address encryption unit to the terminal test module.
Further, the specific working process of the terminal test module is as follows:
selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
and (4) adopting a polling algorithm to check subsequent Cable ports until all the Cable ports are polled, and finishing the test.
Further, in the polling algorithm, if there is a pair of Cable interfaces that have passed the link test, the next polling test is skipped.
Further, before testing, the design file of Cable test needs to be downloaded to FPGA.
The invention also discloses a Cable testing method based on the FPGA prototype verification development board, which is characterized by comprising the following steps:
starting a Cable initial self-test module, providing a display dialog box for a user, and displaying a test result after preliminarily detecting the connection condition of the connector;
acquiring and transmitting information of a development board tested by a user through a pre-test module, acquiring an Ethernet IP address, encrypting and transmitting the IP address through the Ethernet;
and starting a terminal test module for testing, detecting whether data loopback exists after the terminal test module is communicated with the starting self-test module so as to judge whether the connection line is connected or not, if no loopback exists, indicating that the interface is not connected through the connection line, and if the test is passed, indicating that a pair of links are found, displaying the result in a self-test program result list and outputting a final test result to a user.
Further, the specific working process of the terminal test module is as follows:
selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
and (4) adopting a polling algorithm to check subsequent Cable ports until all the Cable ports are polled, and completing the test
Further, in the polling algorithm, if there is a pair of Cable interfaces that have passed the link test, the next polling test is skipped, so as to save the test time
Compared with the prior art, the invention has the beneficial effects that:
after a development user selects and configures a development board to be tested, the FPGA design is downloaded into a chip through a network, then a Cable self-test system of the development board is started, the testing is completed, the system can provide the condition of connector link in the current development board for the user, and the user can rapidly and conveniently develop the design based on a plurality of FPGAs and the chip design with high complexity by using the system, thereby accelerating the development process of SOC products.
Drawings
FIG. 1 is a schematic view of the overall working process of the testing method of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a Cable test system based on an FPGA prototype verification development board, which comprises:
the starting self-testing module is used for providing a display dialog box for a user and displaying a testing result after the connection condition of the connector is preliminarily detected;
after the user opens the engineering design of the development board, the initial connection condition of the Cable is initially detected through the initial self-test module, and the current result is displayed.
The pre-test module is used for acquiring and transmitting information of a development board tested by a user and transmitting the information through Ethernet;
the pre-test module further comprises:
an acquisition unit configured to acquire an IP address of an ethernet;
the IP address encryption unit is electrically connected with the acquisition unit and is used for encrypting the acquired IP address;
and the uploading transmission unit is electrically connected with the IP address encryption unit and is used for transmitting the IP address encrypted by the IP address encryption unit to the terminal test module.
And the terminal test module is used for detecting whether data loopback exists after the communication with the initial self-test module so as to judge whether the connection line is connected or not and outputting a final test result to a user.
The specific working process of the terminal test module is as follows:
before testing, downloading a design file of a Cable test into the FPGA, selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
and (4) adopting a polling algorithm to check subsequent Cable ports until all the Cable ports are polled, and finishing the test.
In the polling algorithm, if there is a pair of Cable interfaces that have passed the link test, the next polling test is skipped, which can also reduce the total time of the test.
In the whole process, the system and the development board communicate through the Ethernet, the development board starts to monitor the control message initiated by the software after being started, and the development board performs corresponding processing after receiving the message. Before testing, a design file of a Cable test needs to be downloaded to the FPGA, a Cable self-test project is configured, then a Cable self-test system is started, and the Cable interoperability is tested.
Compared with the prior art, the system and the development board communicate through the Ethernet, the development board starts to monitor the control message initiated by the software after being started, and the development board performs corresponding processing after receiving the message, so that the connection condition of the connecting lines of a plurality of interfaces can be detected quickly and efficiently, and the overall test efficiency is greatly improved.
As shown in fig. 1, the present invention further provides a Cable testing method based on the FPGA prototype verification development board, including:
starting a Cable initial self-test module, providing a display dialog box for a user, and displaying a test result after preliminarily detecting the connection condition of the connector;
acquiring and transmitting information of a development board tested by a user through a pre-test module, acquiring an Ethernet IP address, encrypting and transmitting the IP address through the Ethernet;
and starting a terminal test module for testing, detecting whether data loopback exists after the terminal test module is communicated with the starting self-test module so as to judge whether the connection line is connected or not, if no loopback exists, indicating that the interface is not connected through the connection line, and if the test is passed, indicating that a pair of links are found, displaying the result in a self-test program result list and outputting a final test result to a user.
The specific working process of the terminal test module is as follows:
selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
and (4) adopting a polling algorithm to check subsequent Cable ports until all the Cable ports are polled, and completing the test
In the polling algorithm, if a pair of Cable interfaces which pass the link test already exist, the next polling test is skipped, so that the test time is saved.
After a development user selects and configures a development board to be tested, the FPGA design is downloaded into a chip through a network, then a Cable self-test system of the development board is started, the testing is completed, the system can provide the condition of connector link in the current development board for the user, and the user can rapidly and conveniently develop the design based on a plurality of FPGAs and the chip design with high complexity by using the system, thereby accelerating the development process of SOC products.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (4)
1. A Cable test system based on FPGA prototype verification development board, characterized by comprising:
the starting self-testing module is used for providing a display dialog box for a user and displaying a testing result after the connection condition of the connector is preliminarily detected;
the pre-test module is used for acquiring and transmitting information of a development board tested by a user and transmitting the information through Ethernet;
the terminal testing module is used for detecting whether data loopback exists after the communication with the initial self-testing module so as to judge whether the connection line is connected or not, outputting a final testing result to a user, and the specific working process of the terminal testing module is as follows:
selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
and adopting a polling algorithm to check subsequent Cable ports until all the Cable ports are polled, and finishing the test.
2. The Cable test system based on the FPGA prototype verification development board of claim 1, wherein the pre-test module further comprises:
an acquisition unit configured to acquire an IP address of an ethernet;
the IP address encryption unit is electrically connected with the acquisition unit and is used for encrypting the acquired IP address;
and the uploading transmission unit is electrically connected with the IP address encryption unit and is used for transmitting the IP address encrypted by the IP address encryption unit to the terminal test module.
3. The Cable test system based on the FPGA prototype verification development board of claim 1, wherein before the test, a design file of the Cable test is downloaded to the FPGA.
4. A Cable test method based on an FPGA prototype verification development board is characterized by comprising the following steps:
starting a Cable initial self-test module, providing a display dialog box for a user, and displaying a test result after preliminarily detecting the connection condition of the connector;
acquiring and transmitting information of a development board tested by a user through a pre-test module, acquiring an Ethernet IP address, encrypting and transmitting the IP address through the Ethernet;
starting a terminal test module for testing, detecting whether data loopback exists after the terminal test module is communicated with the starting self-test module so as to judge whether the connection line is connected or not, if no loopback exists, indicating that the interface is not connected through the connection line, and if the test is passed, indicating that a pair of links are found, displaying the result in a self-test program result list and outputting a final test result to a user; the specific working process of the terminal test module is as follows:
selecting a first Cable port and a second Cable port to be tested, and setting the second Cable as a loop;
sending a detection message to a second Cable through a first Cable port, checking whether data loop exists or not, if so, indicating that the Cable connection is normal, and if not, indicating that the Cable connection on the interface is unsuccessful;
checking subsequent Cable ports by adopting a polling algorithm until all the Cable ports are polled, and finishing the test;
in the polling algorithm, if a pair of Cable interfaces which pass the link test already exist, the next polling test is skipped, so that the test time is saved.
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| TR202014255A2 (en) * | 2020-09-09 | 2020-11-23 | Elopar Elektrik Ve Otomotiv Parcalari Sanayi Ve Ticaret Anonim Sirketi | Sub-assembly navigation for electrical cable harnesses |
| CN115269293B (en) * | 2022-07-31 | 2024-05-07 | 北京汤谷软件技术有限公司 | Interconnection interface testing method based on chip FPGA prototype verification equipment |
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