CN104572442A - In-chip program checking system for programmable logic chip - Google Patents
In-chip program checking system for programmable logic chip Download PDFInfo
- Publication number
- CN104572442A CN104572442A CN201410747708.3A CN201410747708A CN104572442A CN 104572442 A CN104572442 A CN 104572442A CN 201410747708 A CN201410747708 A CN 201410747708A CN 104572442 A CN104572442 A CN 104572442A
- Authority
- CN
- China
- Prior art keywords
- chip
- unit
- test
- under test
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses an in-chip program checking system for a programmable logic chip. The in-chip program checking system comprises a PC (personal computer) communication unit, a data fusion data, a core control unit, a level switch unit, a to-be-detected chip, and a supporting circuit unit of the to-be-detected chip, wherein an EPM1270GT144C4N model CPLD (Complex Programmable Logic Device) is taken as a core control chip in the core control unit; an MK60DN512ZVLQ10 model 32-bit embedded microcontroller is taken as the data fusion unit; a TXB01xx series level switch chip is taken as the level switch unit. According to the in-chip program checking system for the programmable logic chip disclosed by the invention, problems of in-chip programs of the programmable logic chip can be effectively checked out, hidden troubles, caused by the problems and brought to the normal working of the system, are solved, shortcomings of electronic products and test instruments are reduced, and the safety and reliability of the system are guaranteed.
Description
Technical field
the present invention relates to a kind of check system, particularly a kind of programmable logic chip sheet internal program check system.
Background technology
its translator of English of programmable logic device (PLD) is Programmable Logic Device, and referred to as PLD, its principal feature is that its logic function can completely by User Defined, for developer provides great freedom and development space.Following period of time in the past, FPGA (Field Programmable Gate Array) supplier achieves huge technical progress, so that programmable logic chip is considered as by numerous designer being certain choosing of logic solutions so far.Programmable logic chip is just entering the dribs and drabs of our life with its function powerful flexibly.Its use and performance history in, basic procedure be use print make model machine, through repeatedly correction after product approval, then produce in batches and be loaded into compiled program, finally weld install on circuit boards shaping.That batch welds on circuit boards, so its plate level reliability must be guaranteed owing to finally playing a role.
the processing of programmable logic chip needs to experience the process procedures such as a series of chemistry, optics, metallurgy, hot-working.The process of per pass technique and the chip concussion extrusion and collision in transportation is the environment reason such as electrostatic in storage process even, all likely cause the generation of unreliable chip, and these unreliable chips not all can distinguish from presentation and program download process, such as certain input and output pin internal sabotage, can not differentiate from presentation, can not when downloading by its identification out, but it is for whole parts and even whole system, be exactly insecure.And after these unreliable chips download, once its program function comes into operation without verification, just likely become the short slab of electronic product, testing tool and even weaponry, for the normal work of system brings hidden danger, therefore the sheet internal program verification of programmable logic chip is just seemed particularly important.
Summary of the invention
the object of this invention is to provide a kind of programmable logic chip sheet internal program check system.
object of the present invention is achieved through the following technical solutions: programmable logic chip sheet internal program check system, and system comprises PC communication unit, data fusion unit, key control unit, level conversion unit, chip under test and support circuit unit thereof; Described key control unit adopts EPM1270GT144C4N model C PLD as kernel control chip; Described data fusion unit adopts MK60DN512ZVLQ10 model 32 embedded microcontrollers; Described level conversion unit adopts TXB01xx series level transferring chip.
described programmable logic chip sheet internal program check system, described key control unit comprises power supply unit, clock unit, download and debugging unit, test interface unit design; Described power supply unit, selects adjusting and voltage-reduction switch stabilized voltage supply chip TPS5420D, completes the voltage transitions of 12V to 5V, then by AMS1117-3.3,5V is transformed into 3.3V; Described clock unit adopts the highly stable and active crystal oscillator of high-precision 50M, adjustment frequency difference is 25PPm, and this crystal oscillator adopts 3.3V to power, and directly adds 104 electric capacity complete decoupling at power positive end and earth terminal, improve the stability of crystal oscillator work, use 0 Europe resistance buffering signals input.
described programmable logic chip sheet internal program check system, described data fusion unit comprises power supply unit, download program and on-line debugging unit, data transmission interface unit, host computer communication unit.
described programmable logic chip sheet internal program check system, the concrete function of system element is as follows:
1, key control unit: its function controls test process and simulate chip under test required input in hardware platform, monitors chip under test and exports and sent to data fusion unit, or when chip under test no-output, complete test overtime control.
2, data fusion unit: its function is the output data processing one or more chip under test, it is organically merged, is responsible for command analysis and task matching and the data upload of PC end simultaneously, realizes data double-way transfer function.
3, chip under test and support circuit unit thereof: its function is for chip under test provides the working environment of nominal, so that it is operated in rated condition, the possible disturbing factor that eliminating brings due to working environment otherness while completing test, ensures the accurately credible of test result.
4, level conversion unit: owing to there is different level normal value in systems in which, so need design level conversion unit to ensure the absolute confidence degree of data in transmitting procedure, ensure that the chip at data transmission two ends is all operated in rated condition simultaneously, system failure and confidence level can not be caused because of non-normal working to reduce.
5, chip under test hardware inverse inserting-preventing unit: the plug due to test chip needs manually to complete; in order to prevent the chip reversal connection caused due to staff's carelessness; devise chip under test hardware inverse inserting-preventing unit; power-off when realizing anti-inserted by hardware inverse inserting-preventing and warning, protection chip under test and test macro.
described programmable logic chip sheet internal program check system, its principle of work is: when system works, is sent the command information of test assignment by host computer to hardware platform; Hardware platform is resolved it after receiving the test command of host computer, draws the chip and concrete test event that will test; Then select chip under test by sheet, transmit different digital signals according to the different data channel that do not coexist of concrete test event, particular level is added again in the special pin of chip under test after level conversion; Start to monitor the output situation of its certain or some pin afterwards and open test time out timer, if in timing not to being that of obtaining output data, then after data processing and fusion packing, upload to PC end, hold upper computer software to judge that whether the sheet internal program function of this chip is normal according to the corresponding relation between input and output by PC, characterize the net result of this sheet internal program verification with this; If outputted in the scope that arrives of test time-out time starting to monitor, do not hear any output of chip under test, the test crash being designated as test time-out and causing, this chip and sheet internal program separated, wait retests.
beneficial effect of the present invention: programmable logic chip sheet internal program check system of the present invention effectively can check out the problem of Programmadle logic chip slapper internal program, solve the hidden danger that its normal work being system brings, reduce the short slab of electronic product, testing tool, ensure the safe and reliable of system.
Accompanying drawing explanation
fig. 1 is system construction drawing of the present invention;
fig. 2 is principle of work process flow diagram of the present invention;
fig. 3 is key control unit power supply unit schematic diagram;
fig. 4 is key control unit clock unit schematic diagram;
fig. 5 is that key control unit is downloaded and debugging unit schematic diagram;
fig. 6 is key control unit test interface unit schematic diagram;
fig. 7 is data fusion unit power supply unit schematic diagram;
fig. 8 is that data fusion unit program is downloaded and on-line debugging unit schematic diagram;
fig. 9 is data fusion cell data transmission interface unit schematic diagram;
figure 10 is data fusion unit host computer communication unit schematic diagram.
Embodiment
embodiment 1
as Fig. 1, programmable logic chip sheet internal program check system, system comprises PC communication unit, data fusion unit, key control unit, level conversion unit, chip under test and support circuit unit thereof; Described key control unit adopts EPM1270GT144C4N model C PLD as kernel control chip; Described data fusion unit adopts MK60DN512ZVLQ10 model 32 embedded microcontrollers; Described level conversion unit adopts TXB01xx series level transferring chip.
as Fig. 2, the principle of work of programmable logic chip sheet internal program check system is: when system works, is sent the command information of test assignment by host computer to hardware platform; Hardware platform is resolved it after receiving the test command of host computer, draws the chip and concrete test event that will test; Then select chip under test by sheet, transmit different digital signals according to the different data channel that do not coexist of concrete test event, particular level is added again in the special pin of chip under test after level conversion; Start to monitor the output situation of its certain or some pin afterwards and open test time out timer, if in timing not to being that of obtaining output data, then after data processing and fusion packing, upload to PC end, hold upper computer software to judge that whether the sheet internal program function of this chip is normal according to the corresponding relation between input and output by PC, characterize the net result of this sheet internal program verification with this; If outputted in the scope that arrives of test time-out time starting to monitor, do not hear any output of chip under test, the test crash being designated as test time-out and causing, this chip and sheet internal program separated, wait retests.
key control unit in described programmable logic chip sheet internal program check system comprises power supply unit, clock unit, download and debugging unit, test interface unit design;
described power supply unit: system general supply is 12V direct supply, and the operating voltage of CPLD is 3.3V, so have selected adjusting and voltage-reduction switch stabilized voltage supply chip TPS5420D, complete the voltage transitions of 12V to 5V, then by AMS1117-3.3,5V is transformed into 3.3V.At the input/output terminal of power supply with all add electrochemical capacitor and common polarity free capacitor between the often group power pins of CPLD and grounding pin as filter capacitor, reduce the ripple of out-put supply, ensure that the working power ripple parameter of CPLD is within the scope of its nominal, circuit theory as shown in Figure 3.
the work clock of described clock unit: CPLD derives from external crystal-controlled oscillation input, although work dominant frequency can be improved by frequency multiplication by inside, but source still depends on the clock signal input of external stabilization, although clock unit principle is simple, but vital effect is played to the work of system, adopt the active crystal oscillator of highly stable and high-precision 50M in design, adjustment frequency difference is 25PPm.This crystal oscillator adopts 3.3V to power, and directly adds 104 electric capacity complete decoupling at power positive end and earth terminal, improves the stability of crystal oscillator work, and use 0 Europe resistance buffering signals input, circuit theory diagrams are as Fig. 4.
described download and debugging unit: be that the program that CPLD writes needs to utilize usb-blaster downloader to download in CPLD with hardware program language, the process of program debug also needs by downloading debugging interface program debug, and the CPLD that the present invention uses uses 10 pins of standard to download debugging interface; Simultaneously in order to debug conveniently, be the reset circuit that CPLD devises capacitance-resistance and button cooperation, in case there is a need, resetted by CPLD by button, impel program to re-execute, download and debugging unit circuit are as Fig. 5.
described test interface unit: using CPLD as kernel control chip, utilizes the test signal of its simulation needed for chip under test, and monitor and gather the output of chip under test, test interface unit is the I/O pin of CPLD for communicating with each chip under test.Interface is divided into data line and address wire, and be respectively used to address signal input and the data input and output of chip under test, test interface circuit schematic diagram is as Fig. 6.
data fusion unit in described programmable logic chip sheet internal program check system comprises power supply unit, download program and on-line debugging unit, data transmission interface unit, host computer communication unit.
the operating voltage of described power supply unit K60 is 3.3V, by AMS1117-3.3 chip, the DC voltage of 5V is converted to 3.3V for K60; Whole chip has the power pins that 7 groups of VDD and VSS are formed, due to it, there is outstanding mixed signal processing capacity simultaneously, therefore also have one group to provide VDDA and the VSSA power pins of reference for internal simulation signal processing module, when powering, the polarity free capacitor often organized all by 100nF between power pins carries out decoupling, to ensure the power quality of each module of chip internal; At VDDA and VSSA place, the electric capacity of multiple varying number level in parallel carries out decoupling to the interference of different frequency, reduces power supply signal ripple further, the quality of Lifting Modules analog signal processing section reference power source.Data fusion unit power supply unit schematic diagram is as Fig. 7.
described download program and on-line debugging unit, K60 operationally, can be held each variable in program and register parameters by the on-line debugging function in programmed environment, improves the efficiency of program development and debugging.The download program of K60 and on-line debugging interface are 10 pin jtag interfaces of standard, with TMS, TCK, TDO and TDI primary data communication passage of 2,4,6 and 8 pins, 7 and 9 pins are as reserved expansion interface, 10 pin are as the input pin of reset signal, 1 pin is VDD pin, 3 and 5 is GND pin, be whether K60 energize portions by JTAG, can be actual demand by JTAG internal jumper and determine, utilize JTAG to power for K60 when debugging, avoiding whole hardware platform when single module is debugged all needs situation about being energized.When designing, pull-up process is carried out to the data channel of three except TDO, improve the stability of data transmission, and between power supply and ground section, be incorporated to 104 decoupling capacitors, ensure that at use JTAG be power quality during system power supply, download program and on-line debugging unit schematic diagram are as Fig. 8.
described data transmission interface unit, K60 is as the core processor of data fusion unit, need test assignment to convey to CPLD after the order of having resolved PC end, need the output signal receiving the chip under test that CPLD listens to simultaneously, therefore data transmission interface is the data communication interface between CPLD, and data fusion cell data transmission interface unit schematic diagram is as Fig. 9.
described host computer communication unit, because test macro needs to hold host computer to coordinate whole test process with PC, the communication therefore between PC and hardware platform is essential.The communication interface of holding host computer due to PC is serial ports UART, therefore host computer communications unit design is that USB turns serial ports, the serial data realizing PC end turns on Serial Port Transmission to hardware platform by USB or the serial port protocol data of standard, and the hardware serial port module utilizing K60 to carry can complete the data interaction between PC and hardware platform.Turn in the design of serial ports at USB, after compared for several solution of PL2303, CH340, CP2102 and FT232, finally determining with FT232 is that the solution of core is as host computer communications unit design thinking.In the design with reference to the chip data handbook of FT232, be external interface with USB interface, make to be connected by double end USB cable between hardware platform and PC; Consider PCB layout and K60 resources of chip, use the UART1 interface of K60 as communication interface, data fusion unit host computer communication unit schematic diagram is as Figure 10.
described programmable logic chip sheet internal program check system, the concrete function of system element is as follows:
1, key control unit: its function controls test process and simulate chip under test required input in hardware platform, monitors chip under test and exports and sent to data fusion unit, or when chip under test no-output, complete test overtime control.
2, data fusion unit: its function is the output data processing one or more chip under test, it is organically merged, is responsible for command analysis and task matching and the data upload of PC end simultaneously, realizes data double-way transfer function.
3, chip under test and support circuit unit thereof: its function is for chip under test provides the working environment of nominal, so that it is operated in rated condition, the possible disturbing factor that eliminating brings due to working environment otherness while completing test, ensures the accurately credible of test result.
4, level conversion unit: owing to there is different level normal value in systems in which, so need design level conversion unit to ensure the absolute confidence degree of data in transmitting procedure, ensure that the chip at data transmission two ends is all operated in rated condition simultaneously, system failure and confidence level can not be caused because of non-normal working to reduce.
5, chip under test hardware inverse inserting-preventing unit: the plug due to test chip needs manually to complete; in order to prevent the chip reversal connection caused due to staff's carelessness; devise chip under test hardware inverse inserting-preventing unit; power-off when realizing anti-inserted by hardware inverse inserting-preventing and warning, protection chip under test and test macro.
Claims (6)
1. programmable logic chip sheet internal program check system, is characterized in that: system comprises PC communication unit, data fusion unit, key control unit, level conversion unit, chip under test and support circuit unit thereof; Described key control unit adopts EPM1270GT144C4N model C PLD as kernel control chip; Described data fusion unit adopts MK60DN512ZVLQ10 model 32 embedded microcontrollers; Described level conversion unit adopts TXB01xx series level transferring chip.
2. programmable logic chip sheet internal program check system according to claim 1, is characterized in that: described key control unit comprises power supply unit, clock unit, download and debugging unit, test interface unit design.
3. programmable logic chip sheet internal program check system according to claim 2, it is characterized in that: described power supply unit, select adjusting and voltage-reduction switch stabilized voltage supply chip TPS5420D, complete the voltage transitions of 12V to 5V, then by AMS1117-3.3,5V is transformed into 3.3V; Described clock unit adopts the highly stable and active crystal oscillator of high-precision 50M, adjustment frequency difference is 25PPm, and this crystal oscillator adopts 3.3V to power, and directly adds 104 electric capacity complete decoupling at power positive end and earth terminal, improve the stability of crystal oscillator work, use 0 Europe resistance buffering signals input.
4. programmable logic chip sheet internal program check system according to claim 1, is characterized in that: described data fusion unit comprises power supply unit, download program and on-line debugging unit, data transmission interface unit, host computer communication unit.
5. programmable logic chip sheet internal program check system according to claim 1, is characterized in that: system element is as follows:
1, key control unit: its function controls test process and simulate chip under test required input in hardware platform, monitors chip under test and exports and sent to data fusion unit, or when chip under test no-output, complete test overtime control;
2, data fusion unit: its function is the output data processing one or more chip under test, it is organically merged, is responsible for command analysis and task matching and the data upload of PC end simultaneously, realizes data double-way transfer function;
3, chip under test and support circuit unit thereof: its function is for chip under test provides the working environment of nominal, so that it is operated in rated condition, the possible disturbing factor that eliminating brings due to working environment otherness while completing test, ensures the accurately credible of test result;
4, level conversion unit: owing to there is different level normal value in systems in which, so need design level conversion unit to ensure the absolute confidence degree of data in transmitting procedure, ensure that the chip at data transmission two ends is all operated in rated condition simultaneously, system failure and confidence level can not be caused because of non-normal working to reduce;
5, chip under test hardware inverse inserting-preventing unit: the plug due to test chip needs manually to complete; in order to prevent the chip reversal connection caused due to staff's carelessness; devise chip under test hardware inverse inserting-preventing unit; power-off when realizing anti-inserted by hardware inverse inserting-preventing and warning, protection chip under test and test macro.
6. programmable logic chip sheet internal program check system according to claim 1, is characterized in that: host computer sends the command information of test assignment to hardware platform; Hardware platform is resolved it after receiving the test command of host computer, draws the chip and concrete test event that will test; Then select chip under test by sheet, transmit different digital signals according to the different data channel that do not coexist of concrete test event, particular level is added again in the special pin of chip under test after level conversion; Start to monitor the output situation of its certain or some pin afterwards and open test time out timer, if in timing not to being that of obtaining output data, then after data processing and fusion packing, upload to PC end, hold upper computer software to judge that whether the sheet internal program function of this chip is normal according to the corresponding relation between input and output by PC, characterize the net result of this sheet internal program verification with this; If outputted in the scope that arrives of test time-out time starting to monitor, do not hear any output of chip under test, the test crash being designated as test time-out and causing, this chip and sheet internal program separated, wait retests.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410747708.3A CN104572442A (en) | 2014-12-10 | 2014-12-10 | In-chip program checking system for programmable logic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410747708.3A CN104572442A (en) | 2014-12-10 | 2014-12-10 | In-chip program checking system for programmable logic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104572442A true CN104572442A (en) | 2015-04-29 |
Family
ID=53088574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410747708.3A Pending CN104572442A (en) | 2014-12-10 | 2014-12-10 | In-chip program checking system for programmable logic chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104572442A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106707143A (en) * | 2017-01-05 | 2017-05-24 | 北京航天自动控制研究所 | Chip internal logic verify system and method |
| CN107526351A (en) * | 2017-07-27 | 2017-12-29 | 中国航空综合技术研究所 | A kind of universal fault filling method and its device based on JTAG |
| CN109522212A (en) * | 2018-09-30 | 2019-03-26 | 广西电网有限责任公司电力科学研究院 | A kind of acquisition terminal software reliability safety half detection system in kind |
| CN113157575A (en) * | 2021-04-19 | 2021-07-23 | 上海湃星信息科技有限公司 | Prototype test verification system of programmable logic device software |
| CN113204508A (en) * | 2021-04-25 | 2021-08-03 | 山东英信计算机技术有限公司 | Complex programmable logic device scanning method and device |
| CN117093437A (en) * | 2023-10-16 | 2023-11-21 | 成都电科星拓科技有限公司 | Method and device for testing chip bus input signal decision level tolerance |
| CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020129338A1 (en) * | 2001-03-07 | 2002-09-12 | Macdonell Kevin | Method and system for on-line submission and debug of software code for a portable computer system or electronic device |
| CN1855043A (en) * | 2005-04-19 | 2006-11-01 | 华为技术有限公司 | Method for checking software edition in programmable logic element |
| CN202659413U (en) * | 2012-04-26 | 2013-01-09 | 嘉兴德瑞纳自动化技术有限公司 | Wind power monitoring device capable of remotely upgrading compression algorithm |
-
2014
- 2014-12-10 CN CN201410747708.3A patent/CN104572442A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020129338A1 (en) * | 2001-03-07 | 2002-09-12 | Macdonell Kevin | Method and system for on-line submission and debug of software code for a portable computer system or electronic device |
| CN1855043A (en) * | 2005-04-19 | 2006-11-01 | 华为技术有限公司 | Method for checking software edition in programmable logic element |
| CN202659413U (en) * | 2012-04-26 | 2013-01-09 | 嘉兴德瑞纳自动化技术有限公司 | Wind power monitoring device capable of remotely upgrading compression algorithm |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106707143A (en) * | 2017-01-05 | 2017-05-24 | 北京航天自动控制研究所 | Chip internal logic verify system and method |
| CN107526351A (en) * | 2017-07-27 | 2017-12-29 | 中国航空综合技术研究所 | A kind of universal fault filling method and its device based on JTAG |
| CN109522212A (en) * | 2018-09-30 | 2019-03-26 | 广西电网有限责任公司电力科学研究院 | A kind of acquisition terminal software reliability safety half detection system in kind |
| CN113157575A (en) * | 2021-04-19 | 2021-07-23 | 上海湃星信息科技有限公司 | Prototype test verification system of programmable logic device software |
| CN113204508A (en) * | 2021-04-25 | 2021-08-03 | 山东英信计算机技术有限公司 | Complex programmable logic device scanning method and device |
| CN117093437A (en) * | 2023-10-16 | 2023-11-21 | 成都电科星拓科技有限公司 | Method and device for testing chip bus input signal decision level tolerance |
| CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104572442A (en) | In-chip program checking system for programmable logic chip | |
| US8281280B2 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| US9836372B1 (en) | Device verification system with firmware universal verification component | |
| KR20110124617A (en) | System-on-chip and debugging method thereof | |
| CN105425201B (en) | metering chip simulation test method for software reliability detection of intelligent electric energy meter | |
| CN202189124U (en) | FPGA multiple real-time reconfiguration adapter based on test system | |
| CN113157501B (en) | ATE (automatic test equipment) tester-based AC (alternating current) parameter testing method for microsystem module | |
| CN103365751A (en) | Main board testing device and changeover module thereof | |
| CN104502832A (en) | Automatic tester and testing method based on hand-held POS machine mainboard | |
| CN103699112A (en) | Aviation electronic self-detection verification equipment based on IO (Input/Output) signal failure simulation, and verification method of equipment | |
| CN107656882A (en) | A kind of USB controller verification method, system and equipment | |
| CN203260029U (en) | System chip prototype verification debugging device based on field programmable gate array (FPGA) | |
| CN204789908U (en) | Circuit board automatic test system based on labVIEW | |
| CN108055674A (en) | SDIO interfaces WiFi module test system and method based on SDIO interface protocols | |
| CN104035023A (en) | Testing method and system of MCU | |
| CN112034330A (en) | Automatic QC method and device for SOC chip | |
| CN204480344U (en) | A kind of coal preparation plant portable wireless logging | |
| CN103376340A (en) | Adapter plate, a multi-platform serial test system and method | |
| CN101114249A (en) | I2C bus testing apparatus of mainboard and method thereof | |
| CN103954946A (en) | T/R module debugging instrument | |
| CN202815170U (en) | Chip test system | |
| CN111090039A (en) | FPGA function test method and device | |
| CN103235254A (en) | Detection method and detection system for programmable logic device | |
| CN111060807B (en) | High-speed integrated circuit test platform based on SoC and test method thereof | |
| CN109472171B (en) | FPGA hardware Trojan horse detection system based on human-computer interface and current monitoring |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |