CN117250483A - Chip test system and method - Google Patents
Chip test system and method Download PDFInfo
- Publication number
- CN117250483A CN117250483A CN202311533564.7A CN202311533564A CN117250483A CN 117250483 A CN117250483 A CN 117250483A CN 202311533564 A CN202311533564 A CN 202311533564A CN 117250483 A CN117250483 A CN 117250483A
- Authority
- CN
- China
- Prior art keywords
- test
- chip
- tested
- control platform
- main control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 259
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000008676 import Effects 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims 1
- 238000012795 verification Methods 0.000 abstract description 11
- 238000004891 communication Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013524 data verification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application discloses a chip testing system and method. The chip test system comprises an upper computer, a main control platform and a tested unit which are sequentially connected, wherein the upper computer is used for loading test instructions according to test engineering, sending the test instructions to the main control platform, receiving test results returned by the main control platform, the main control platform is used for analyzing the received test instructions, configuring test operations corresponding to the test instructions so as to test chips to be tested on a target port in the tested unit, inquiring the test results, the tested unit comprises a plurality of chip connecting plates with unified interfaces, a plurality of chips to be tested are respectively connected into the chip connecting plates, and the tested unit is used for executing corresponding test operations after being electrified. The embodiment of the application constructs the chip test system integrating the functions of downloading a plurality of chips, automatically testing, recording verification results and the like, can be used for various chips and custom operation flows, and greatly shortens the test flow of the chips.
Description
Technical Field
The invention relates to the field of chips, in particular to a chip testing system and method.
Background
Along with the development of electronic industry automation, the demand of each industry for chips is also increasing, along with mass production of chips, detailed tests on the characteristics, functions and the like of the chips are required before the formal sales and application of the chips, the chips produced in the first batch are blind sealing chips for the related work of chip verification, the related configuration and calibration of some chip attributes are not performed, corresponding operation is required to be performed on each chip for verification manually, the number of the chips is hundreds or thousands, and a plurality of configuration items are required for each chip after configuration, and the verification and confirmation are also required for the configured chips.
For mass production of electronic products, a link is to perform program downloading and function verification on a control chip of the electronic product during mass production, and factory downloading generally uses a mass downloader to download programs in advance for welding, so that the applicant finds that a bad chip can be welded to a circuit board without performing data verification work on the chip in the way, and reworking occurs later, so that the problems of high test cost and long period are caused when the chip is subjected to a stage from blind sealing to mass production.
Disclosure of Invention
The invention provides a chip testing system and a chip testing method, which integrate the functions of downloading a plurality of chips, automatically testing, recording verification results and the like, can be used for various chips and custom operation flows, greatly shortens the testing flow of the chips, and solves the problems of high testing cost and long period from blind sealing to mass production of the chips.
In order to achieve the beneficial effects, the embodiment of the invention provides the following technical scheme:
in a first aspect, the present application provides a chip testing system, including an upper computer, a main control platform, and a unit under test, which are sequentially connected;
the upper computer is used for loading a test instruction according to a test project, sending the test instruction to the main control platform and receiving a test result returned by the main control platform;
the main control platform is used for analyzing the received test instruction, configuring the test operation corresponding to the test instruction, testing the chip to be tested on the target port in the tested unit, and inquiring the test result;
the tested unit comprises a plurality of chip connecting plates with unified interfaces, a plurality of chips to be tested are respectively connected into the chip connecting plates, and the tested unit is used for executing corresponding test operation after being electrified.
In one embodiment, the chip test system further comprises:
the measuring instrument is respectively connected with the upper computer and the unit to be measured and is used for detecting the measured value of the chip to be measured in the unit to be measured, and the measuring instrument comprises a temperature box, a frequency meter and a universal meter.
In an embodiment, the upper computer is further configured to import a corresponding test project according to the chip to be tested, and send a test program in the test project to the master control platform;
the main control platform is also used for configuring a downloading mode and controlling the chip to be tested in the tested unit to download the test program according to the downloading mode.
In one embodiment, the upper computer is connected to the master control platform through a universal asynchronous receiver/transmitter.
In an embodiment, the master control platform comprises a relay for controlling the power supply switch of the unit under test and the switch state of the asynchronous transceiver.
In an embodiment, the main control platform is connected to a pin of the chip to be tested in the tested unit through a general input/output port, and adjusts the power supply voltage of the chip to be tested in the tested unit through a voltage adjusting unit.
In an embodiment, the main control platform includes a multiplexer, where the multiplexer is used to select a target chip to be tested from the tested units. And connecting the MCO pin of the target chip to be measured to the measuring instrument.
In a second aspect, the present application provides a chip testing method, the method comprising:
the upper computer leads in a test project according to the specification of the chip to be tested, and sends the test program to the tested unit through the main control platform;
the upper computer loads a test instruction and sends the test instruction to the main control platform;
the main control platform analyzes the received test instruction, configures the test operation corresponding to the test instruction, tests the chip to be tested on the target port in the tested unit, and inquires the test result and returns the test result to the upper computer.
In an embodiment, the tested unit includes a plurality of chip connection boards with unified interfaces, and the step of respectively accessing a plurality of chips to be tested and sending the test program to the tested unit through the main control platform includes:
when a chip to be tested downloads a test program in a safe starting mode, the master control platform configures boot pins of the chip to be tested;
when a chip to be tested downloads a test program through a serial line debugging interface, the master control platform controls the chip to be tested to output an SWD sequence to enter a downloading mode;
when the chip to be tested downloads the test program through the in-system programming, the main control platform controls the chip to be tested to enter a program upgrading mode by using a preset interface and a protocol.
In an embodiment, the method further comprises:
and receiving a measured value of the testing instrument aiming at the chip to be tested in the tested unit, and returning the measured value to the upper computer.
The chip test system provided by the embodiment of the application comprises an upper computer, a main control platform and a tested unit which are sequentially connected, wherein the upper computer is used for loading test instructions according to test engineering, sending the test instructions to the main control platform, receiving test results returned by the main control platform, the main control platform is used for analyzing the received test instructions, configuring test operations corresponding to the test instructions, testing chips to be tested on a target port in the tested unit, inquiring the test results, the tested unit comprises a plurality of chip connecting plates with uniform interfaces, a plurality of chips to be tested are respectively connected into the chip connecting plates, and the tested unit is used for executing corresponding test operations after being electrified. The embodiment of the application constructs the chip test system integrating the functions of downloading a plurality of quantities, automatically testing, recording verification results and the like, can be used for various chips and self-defining operation flows, greatly shortens the test flow of the chips, and solves the problems of high test cost and long period from blind encapsulation to mass production of the chips.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first configuration of a chip test system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a second structure of a chip test system according to an embodiment of the present invention;
fig. 3 is a flow chart of a chip testing method according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip testing system according to an embodiment of the invention. The chip test system comprises an upper computer, a main control platform and a tested unit which are connected in sequence. The upper computer is used for loading the test instruction according to the test engineering, sending the test instruction to the main control platform and receiving the test result returned by the main control platform. Specifically, the upper computer comprises a test project, wherein the test project comprises target test items or configuration item lists, and each list represents an independent test item or configuration item. In each list is a series of test instructions or configuration instructions. When testing, the upper computer automatically loads a test list according to the loaded test engineering, automatically tests according to the command in the test list, automatically records the test result according to the test command and generates a test report in the corresponding table. The specific workflow of the upper computer is to automatically load the test according to the test engineering, send the test command to the main control platform and read the test result of the main control platform.
The main control platform is used for analyzing the received test instruction, configuring the test operation corresponding to the test instruction, testing the chip to be tested on the target port in the tested unit, and inquiring the test result. Specifically, the main control platform may include a series of peripheral circuits and a main control chip, where the peripheral circuits mainly implement functions of gating the unit to be tested through the decoder, and connecting with an interface circuit of the upper computer and a measuring instrument. The main control chip is mainly used for analyzing the command, controlling the tested unit and the running environment of the tested unit according to the command, sending a secondary test command to the tested unit, receiving the return state of the tested unit, and finally feeding back the test result to the upper computer.
Further, the tested unit comprises a plurality of chip connecting plates with uniform interfaces, a plurality of chips to be tested are respectively connected into the chip connecting plates, and the tested unit is used for executing corresponding test operation after being electrified. In the embodiment of the application, the tested unit is defined with the chip connecting plate with the unified interface, the peripheral interface and the command behavior of the tested unit are unified, and when a new chip needs to be verified, the verification period is greatly shortened.
In an embodiment, the chip testing system may further include a measuring instrument, where the measuring instrument is respectively connected to the upper computer and the unit under test and is used for detecting a measured value of the chip under test in the unit under test, and the measuring instrument includes a temperature box, a frequency meter and a multimeter. In this embodiment, the upper computer is also used to control the measuring instrument and read the measured value of the measuring instrument.
In an embodiment, before the chip test system is tested, a test program is further pre-introduced, specifically, the upper computer pre-introduces a test project, for example, according to a series of specifications of the chips to be tested, introduces a corresponding test project, then reads a chip program of a specific application, and reads the chip program into the upper computer as a target program of the unit to be tested, and determines whether to execute the program downloading task of a plurality of chips to be tested to the last chip to be tested. And when judging that the program downloading task of all the chips to be tested is completed, displaying that the downloading is completed by the upper computer. And then translating the instruction into a transmission command on a communication protocol of the upper computer and the main control platform, wherein one instruction is possibly translated into one or more transmission commands which are executed sequentially. And transmitting commands according to communication protocols and interfaces (such as uart/can/spi and the like) of the upper computer and the main control platform, and receiving an execution result of the main control platform by the upper computer after the main control platform finishes the commands.
The main program of the central control platform is to receive data according to a communication protocol connected with an upper computer, operate a command analyzer and execute corresponding operations according to different commands. When a program download command is received, the following operations are performed:
(1) Opening the voltage of the designated unit under test according to the command: and the power-on operation of the specific tested unit is realized through a hardware circuit, and the specific output voltage is set.
(2) And configuring the download mode, and configuring the download mode according to the download mode of the chip to be tested.
(3) Downloading the program according to the upgrade protocol and downloading the program according to the downloading mode.
(4) Downloading is completed, and the voltage of the unit to be tested is specified to be closed: and cutting off the power supply of the tested power supply after the downloading is completed.
In an embodiment, the main control platform can power up the unit to be tested through the peripheral circuit, the unit to be tested enters a downloading mode after power up, for example, enters a specific downloading mode through an external interface, then updates a program in the flash, and the main control platform powers down the unit to be tested through the peripheral circuit after the update is completed.
After the test program is downloaded and enters the chip test stage, the upper computer can import test engineering, such as importing corresponding test engineering according to the specification of the chip to be tested, and then reading in a test item list, wherein the test engineering comprises a test item list, and the test item list comprises test instructions executed in sequence. When all the test instructions are executed, the test is judged to be completed, a test report is generated according to the test instructions and the tested unit ID as indexes, and the upper computer displays the test completion. Furthermore, the upper computer is required to translate the test instruction into a transmission command on a communication protocol between the upper computer and the main control platform. An instruction may be translated into one or more sequentially executed transfer commands. Judging whether the command is the last command corresponding to the instruction, if so, determining that the command is ended. It should be noted that, the above command may be transmitted to the host computer according to a communication protocol and an interface (uart/can/spi, etc.) of the host computer and the main control platform, and different commands may receive different test results. Some of the test results need to be fed back through the main control platform, and some of the test results need to be directly read in frequency values or current values of the test instrument.
The main program of the main control platform is to receive data according to a communication protocol connected with an upper computer, operate a command analyzer and execute corresponding operations according to different commands. The command control platform configures corresponding test operation, and can execute the test operation according to the command, and finally inquire the test result according to the corresponding test operation and feed back the test result to the upper computer through a communication protocol.
The test operation of the tested unit, some of which need to send test commands through ports (uart/spi/can/IIC, etc.); some only need to operate on the IO or power supply of the unit under test. And after the test is completed, feeding back a test result according to the corresponding test operation. Also, some require sending test commands through ports (uart/spi/can/IIC, etc.); some only need IO output test result of tested unit.
The test instrument comprises one or more passive devices, and the control and the data reading are performed through the upper computer.
Further, referring to fig. 2, in this embodiment, the upper computer is connected to the main control platform by a tool on the PC through the UART, and the temperature of the incubator can be controlled by the instruction, so as to read the measured values of the frequency meter and the universal meter. The UART is a universal asynchronous receiver/transmitter, and transmits data through serial communication. It performs parallel-to-serial data conversion at the transmitting end and serial-to-parallel data conversion at the receiving end.
In the embodiment, the main control platform can control the power supply of the unit to be tested and the switching state of the UART through the relay, the main control chip in the main control platform can be connected with the pins of the NRST/Wakeup/EXTI on the unit to be tested through the GPIO, and the voltage regulation unit can regulate the power supply voltage of the unit to be tested, and the power consumption is tested by accessing the universal meter of the test instrument. The GPIO is a general purpose input/output port, and the pin of the GPIO is connected with an external hardware device, so that functions of communicating with the outside, controlling the external hardware, or collecting data of the external hardware can be realized.
In an embodiment, the master control platform may further include a multiplexer, where the multiplexer may be used to select a target chip to be tested from the unit under test. And connecting the MCO pins of the target chip to be measured to a measuring instrument.
The chip test system can reduce manual participation in an automatic test process, automatically control a test environment, automatically generate a test report, improve test verification efficiency before mass production, simultaneously establish a unit interface to be tested of a unified platform, and directly test the new chip by only unifying the unit interface to be tested when the new chip needs to be tested, thereby greatly shortening verification time before mass production.
In summary, the chip test system disclosed in the embodiments of the present application includes an upper computer, a main control platform and a tested unit that are sequentially connected, where the upper computer is configured to load a test instruction according to a test engineering, send the test instruction to the main control platform, receive a test result returned by the main control platform, the main control platform is configured to analyze the received test instruction, configure a test operation corresponding to the test instruction, so as to test a chip to be tested on a target port in the tested unit, query the test result, the tested unit includes a plurality of chip connection boards with unified interfaces, and is respectively connected to the plurality of chips to be tested, and the tested unit is configured to execute a corresponding test operation after being powered on. The embodiment of the application constructs the chip test system integrating the functions of downloading a plurality of chips, automatically testing, recording verification results and the like, can be used for various chips and custom operation flows, and greatly shortens the test flow of the chips.
The embodiment of the invention also provides a chip testing method, the execution main body of which can be a chip testing device or a server integrated with the chip testing device, wherein the chip testing device can be realized in a hardware or software mode.
In the present embodiment, description will be made from the viewpoint of a chip test apparatus which can be integrated in a terminal apparatus which is a terminal apparatus provided with a storage unit and capable of running an application program. According to the chip structure described in the above embodiment, further details will be given below by way of example.
In this embodiment, description will be given taking an example in which the chip test apparatus is specifically integrated in a terminal apparatus.
Referring to fig. 3, fig. 3 is a flow chart of a chip testing method according to an embodiment of the invention. The method flow may include:
step 101, the upper computer imports the test engineering according to the specification of the chip to be tested, and sends the test program to the tested unit through the main control platform.
In an embodiment, the step of sending the test program to the unit under test through the master control platform may include: when the chip to be tested downloads the test program in a safe starting mode, the master control platform configures boot pins of the chip to be tested; when the chip to be tested downloads the test program through the serial line debugging interface, the master control platform controls the chip to be tested to output the SWD sequence to enter a downloading mode; when the chip to be tested downloads the test program through the in-system programming, the main control platform controls the chip to be tested to enter a program upgrading mode by using a preset interface and a protocol.
Step 102, the upper computer load test instruction is sent to the main control platform.
And 103, analyzing the received test instruction by the main control platform, configuring test operation corresponding to the test instruction, testing the chip to be tested on the target port in the tested unit, and inquiring the test result to return to the upper computer.
In an embodiment, the upper computer may be directly connected to the testing instrument to test the chip to be tested in the tested unit in addition to receiving the test result returned by the main control platform, so the method may further include: and receiving the measured value of the testing instrument aiming at the chip to be tested in the tested unit, and returning the measured value to the upper computer.
In an embodiment, the test contents for the chip to be tested may include: short circuit test, open circuit test, maximum current test, propagation delay test, setup and hold time test, functional speed test, etc. The chip test in this embodiment mainly includes two main types, i.e., a parameter test and a functional test, where the parameter test is to determine whether the chip pins conform to various rising and falling times, setup and hold times, high and low voltage thresholds, and high and low current specifications, including DC (Direct Current) parameter test and AC (AlternaTIng Current) parameter test. DC parameter tests include short circuit tests, open circuit tests, maximum current tests, etc. AC parameter tests include transmission delay tests, setup and hold time tests, functional speed tests, and the like. These tests are typically process-related. CMOS output voltage measurement requires no load, while TTL devices require a current load. Functional testing determines whether the behavior of the internal digital logic and analog subsystems of the chip is desirable. These tests consist of inputting the appropriate amount and corresponding response. They check whether a verified design is working by testing the internal nodes of the chip. Functional testing has a high coverage of typical faults of logic circuits.
As can be seen from the above, the chip testing method provided in the embodiment of the present application may guide the test engineering through the upper computer according to the specification of the chip to be tested, and send the test program to the unit to be tested through the main control platform, the upper computer loads the test instruction and sends the test instruction to the main control platform, the main control platform analyzes the received test instruction, configures the test operation corresponding to the test instruction, so as to test the chip to be tested on the target port in the unit to be tested, and queries the test result and returns to the upper computer. The chip testing method can shorten the testing flow of the chip and improve the testing efficiency.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.
Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present invention includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification. Furthermore, while a particular feature of the subject specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for a given or particular application. Moreover, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.
The system and the method for testing the chip provided by the embodiment of the invention are described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.
Claims (10)
1. The chip test system is characterized by comprising an upper computer, a main control platform and a tested unit which are connected in sequence;
the upper computer is used for loading a test instruction according to a test project, sending the test instruction to the main control platform and receiving a test result returned by the main control platform;
the main control platform is used for analyzing the received test instruction, configuring the test operation corresponding to the test instruction, testing the chip to be tested on the target port in the tested unit, and inquiring the test result;
the tested unit comprises a plurality of chip connecting plates with unified interfaces, a plurality of chips to be tested are respectively connected into the chip connecting plates, and the tested unit is used for executing corresponding test operation after being electrified.
2. The chip testing system of claim 1, wherein the chip testing system further comprises:
the measuring instrument is respectively connected with the upper computer and the unit to be measured and is used for detecting the measured value of the chip to be measured in the unit to be measured, and the measuring instrument comprises a temperature box, a frequency meter and a universal meter.
3. The chip test system according to claim 1, wherein the host computer is further configured to import a corresponding test project according to the chip to be tested, and send a test program in the test project to the master control platform;
the main control platform is also used for configuring a downloading mode and controlling the chip to be tested in the tested unit to download the test program according to the downloading mode.
4. The chip test system according to any one of claims 1-3, wherein the host computer is connected to the host platform through a universal asynchronous receiver/transmitter.
5. The chip test system according to claim 4, wherein the master control platform includes a relay for controlling a power supply switch of the unit under test and a switching state of the asynchronous transceiver.
6. The chip test system according to any one of claims 1 to 3, wherein the main control platform is connected to pins of the chip to be tested in the unit to be tested through a general input/output port, and adjusts a power supply voltage of the chip to be tested in the unit to be tested through a voltage adjusting unit.
7. The chip test system according to claim 2, wherein the main control platform includes a multiplexer for selecting a target chip under test from the unit under test and connecting an MCO pin of the target chip under test to the measuring instrument.
8. A method of testing a chip, the method comprising:
the upper computer leads in a test project according to the specification of the chip to be tested, and sends the test program to the tested unit through the main control platform;
the upper computer loads a test instruction and sends the test instruction to the main control platform;
the main control platform analyzes the received test instruction, configures the test operation corresponding to the test instruction, tests the chip to be tested on the target port in the tested unit, and inquires the test result and returns the test result to the upper computer.
9. The chip testing method according to claim 8, wherein the unit under test includes a plurality of chip connection boards with unified interfaces, and a plurality of chips under test are respectively connected thereto, and wherein the step of transmitting the test program to the unit under test through the main control platform includes:
when a chip to be tested downloads a test program in a safe starting mode, the master control platform configures boot pins of the chip to be tested;
when a chip to be tested downloads a test program through a serial line debugging interface, the master control platform controls the chip to be tested to output an SWD sequence to enter a downloading mode;
when the chip to be tested downloads the test program through the in-system programming, the main control platform controls the chip to be tested to enter a program upgrading mode by using a preset interface and a protocol.
10. The chip testing method according to claim 8, further comprising:
and receiving a measured value of the testing instrument aiming at the chip to be tested in the tested unit, and returning the measured value to the upper computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311533564.7A CN117250483A (en) | 2023-11-17 | 2023-11-17 | Chip test system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311533564.7A CN117250483A (en) | 2023-11-17 | 2023-11-17 | Chip test system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117250483A true CN117250483A (en) | 2023-12-19 |
Family
ID=89127979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311533564.7A Pending CN117250483A (en) | 2023-11-17 | 2023-11-17 | Chip test system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117250483A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117572219A (en) * | 2024-01-15 | 2024-02-20 | 深圳市爱普特微电子有限公司 | MCU chip electrical parameter automated testing system and method |
| CN117783835A (en) * | 2024-02-26 | 2024-03-29 | 北京力通通信有限公司 | System and method for rapidly testing batch concurrency of radio frequency transceiver chips |
| CN118858880A (en) * | 2024-06-18 | 2024-10-29 | 航天科工防御技术研究试验中心 | Universal source meter program control system and chip testing method based on ATE |
| CN118897810A (en) * | 2024-10-09 | 2024-11-05 | 北京智芯微电子科技有限公司 | Operating system testing method, device and system integrating multiple chips |
Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202795859U (en) * | 2012-10-08 | 2013-03-13 | 常州信息职业技术学院 | Portable universal 51 one-chip microcomputer teaching experimental instrument |
| CN104461633A (en) * | 2014-12-10 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Single-chip offline programming unit and offline programming method |
| CN104572442A (en) * | 2014-12-10 | 2015-04-29 | 黑龙江真美广播通讯器材有限公司 | In-chip program checking system for programmable logic chip |
| CN204832267U (en) * | 2015-08-14 | 2015-12-02 | 万高(杭州)科技有限公司 | A chip testing platform |
| CN206574350U (en) * | 2016-12-05 | 2017-10-20 | 长沙理工大学 | A kind of teaching experiment board based on double-core |
| CN109633413A (en) * | 2018-12-28 | 2019-04-16 | 芯海科技（深圳）股份有限公司 | 32 MCU core chip test systems of one kind and its test method |
| CN110197699A (en) * | 2019-07-29 | 2019-09-03 | 南京优存科技有限公司 | A kind of multi-chip common wafer test circuit |
| CN110568345A (en) * | 2019-09-27 | 2019-12-13 | 北京中电华大电子设计有限责任公司 | automatic test equipment and control method thereof |
| CN110600071A (en) * | 2018-06-12 | 2019-12-20 | 四川华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| CN111143854A (en) * | 2019-12-25 | 2020-05-12 | 眸芯科技（上海）有限公司 | Device, system and method for starting chip secure download |
| CN111758088A (en) * | 2020-02-07 | 2020-10-09 | 深圳市汇顶科技股份有限公司 | Method and chip for downloading firmware from chip |
| CN113176493A (en) * | 2021-04-22 | 2021-07-27 | 海光信息技术股份有限公司 | Chip test mainboard, test system and test method |
| CN113553081A (en) * | 2021-07-26 | 2021-10-26 | 成都亿凌特科技有限公司 | FPGA loading method based on ZYNQ chip |
| CN113702810A (en) * | 2021-09-01 | 2021-11-26 | 厦门优迅高速芯片有限公司 | MCU-based optical transceiver driver chip function test method and related equipment |
| CN114121140A (en) * | 2022-01-28 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method, system, electronic device and storage medium |
| CN114325314A (en) * | 2021-12-20 | 2022-04-12 | 海光信息技术股份有限公司 | Chip power supply circuit test structure, test method and test system |
| CN217385736U (en) * | 2022-04-26 | 2022-09-06 | 成都极海科技有限公司 | MCU's ATE equipment and system thereof |
| CN115932540A (en) * | 2022-11-25 | 2023-04-07 | 镇江矽佳测试技术有限公司 | A multi-channel multifunctional chip testing machine and testing method |
| CN116647535A (en) * | 2022-02-16 | 2023-08-25 | 合肥格易集成电路有限公司 | Communication forwarding device, control method and electronic equipment |
-
2023
- 2023-11-17 CN CN202311533564.7A patent/CN117250483A/en active Pending
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202795859U (en) * | 2012-10-08 | 2013-03-13 | 常州信息职业技术学院 | Portable universal 51 one-chip microcomputer teaching experimental instrument |
| CN104461633A (en) * | 2014-12-10 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Single-chip offline programming unit and offline programming method |
| CN104572442A (en) * | 2014-12-10 | 2015-04-29 | 黑龙江真美广播通讯器材有限公司 | In-chip program checking system for programmable logic chip |
| CN204832267U (en) * | 2015-08-14 | 2015-12-02 | 万高(杭州)科技有限公司 | A chip testing platform |
| CN206574350U (en) * | 2016-12-05 | 2017-10-20 | 长沙理工大学 | A kind of teaching experiment board based on double-core |
| CN110600071A (en) * | 2018-06-12 | 2019-12-20 | 四川华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| CN109633413A (en) * | 2018-12-28 | 2019-04-16 | 芯海科技（深圳）股份有限公司 | 32 MCU core chip test systems of one kind and its test method |
| CN110197699A (en) * | 2019-07-29 | 2019-09-03 | 南京优存科技有限公司 | A kind of multi-chip common wafer test circuit |
| CN110568345A (en) * | 2019-09-27 | 2019-12-13 | 北京中电华大电子设计有限责任公司 | automatic test equipment and control method thereof |
| CN111143854A (en) * | 2019-12-25 | 2020-05-12 | 眸芯科技（上海）有限公司 | Device, system and method for starting chip secure download |
| CN111758088A (en) * | 2020-02-07 | 2020-10-09 | 深圳市汇顶科技股份有限公司 | Method and chip for downloading firmware from chip |
| CN113176493A (en) * | 2021-04-22 | 2021-07-27 | 海光信息技术股份有限公司 | Chip test mainboard, test system and test method |
| CN113553081A (en) * | 2021-07-26 | 2021-10-26 | 成都亿凌特科技有限公司 | FPGA loading method based on ZYNQ chip |
| CN113702810A (en) * | 2021-09-01 | 2021-11-26 | 厦门优迅高速芯片有限公司 | MCU-based optical transceiver driver chip function test method and related equipment |
| CN114325314A (en) * | 2021-12-20 | 2022-04-12 | 海光信息技术股份有限公司 | Chip power supply circuit test structure, test method and test system |
| CN114121140A (en) * | 2022-01-28 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method, system, electronic device and storage medium |
| CN116647535A (en) * | 2022-02-16 | 2023-08-25 | 合肥格易集成电路有限公司 | Communication forwarding device, control method and electronic equipment |
| CN217385736U (en) * | 2022-04-26 | 2022-09-06 | 成都极海科技有限公司 | MCU's ATE equipment and system thereof |
| CN115932540A (en) * | 2022-11-25 | 2023-04-07 | 镇江矽佳测试技术有限公司 | A multi-channel multifunctional chip testing machine and testing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117572219A (en) * | 2024-01-15 | 2024-02-20 | 深圳市爱普特微电子有限公司 | MCU chip electrical parameter automated testing system and method |
| CN117572219B (en) * | 2024-01-15 | 2024-03-22 | 深圳市爱普特微电子有限公司 | Automatic test system and method for electrical parameters of MCU (micro control Unit) chip |
| CN117783835A (en) * | 2024-02-26 | 2024-03-29 | 北京力通通信有限公司 | System and method for rapidly testing batch concurrency of radio frequency transceiver chips |
| CN117783835B (en) * | 2024-02-26 | 2024-05-31 | 北京力通通信有限公司 | System and method for rapidly testing batch concurrency of radio frequency transceiver chips |
| CN118858880A (en) * | 2024-06-18 | 2024-10-29 | 航天科工防御技术研究试验中心 | Universal source meter program control system and chip testing method based on ATE |
| CN118897810A (en) * | 2024-10-09 | 2024-11-05 | 北京智芯微电子科技有限公司 | Operating system testing method, device and system integrating multiple chips |
| CN118897810B (en) * | 2024-10-09 | 2025-02-28 | 北京智芯微电子科技有限公司 | Operating system testing method, device and system integrating multiple chips |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN117250483A (en) | Chip test system and method | |
| CN115932540B (en) | Multi-channel multifunctional chip testing machine and testing method | |
| CN101915877A (en) | A general-purpose electromagnetic susceptibility test device and test method based on bus technology | |
| CN117572219B (en) | Automatic test system and method for electrical parameters of MCU (micro control Unit) chip | |
| CN115112977B (en) | Multi-channel frequency conversion module calibration and measurement integrated automatic test platform and test method | |
| CN101986278A (en) | Automatic testing method and system for electronic equipment | |
| CN111273153A (en) | Automatic testing method, device and system for chip | |
| CN112416804B (en) | Real-time simulation test system and method | |
| US9971010B2 (en) | Calibration apparatus and method for network analyzer | |
| CN117706322B (en) | Chip testing method and system | |
| CN104539250A (en) | Debugging method, device and system of power amplifier | |
| CN111831553B (en) | Testing system and testing method for multifunctional integrated automatic simulation test | |
| CN110568339A (en) | Instrument automatic testing system and method based on Internet of things | |
| CN114138312B (en) | Upgrade testing method, device, electronic equipment and computer readable storage medium | |
| CN106571841A (en) | Radio frequency matching system and method of realizing radio frequency matching automation | |
| CN117214672A (en) | FPGA-based chip burn-in test-oriented test system and method | |
| CN207232283U (en) | A kind of Auto-Test System of aircraft flap/slat electronic unit component | |
| CN114019357A (en) | Management method of test pin of logic processing module and related assembly | |
| WO2021109049A1 (en) | Pcba intelligent automatic test method and system | |
| CN215813191U (en) | FPGA-based automatic detection device for time delay ASIC circuit | |
| CN118642898A (en) | Automatic configuration test system and method for microcontroller | |
| CN111596203A (en) | A chip testing device, platform and method | |
| CN105356931A (en) | Broadband signal attenuation control equipment and control method | |
| CN113922871B (en) | Integrated comprehensive testing device and testing method based on same | |
| CN117650857A (en) | Bluetooth module testing method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20231219 |