CN112014726B - DSP chip testing device and method - Google Patents

Abstract

The invention discloses a device and a method for testing a Digital Signal Processor (DSP) chip, and provides a device for realizing automatic testing of the DSP chip, aiming at the problems of low testing efficiency and complicated testing process in the existing DSP chip testing method. Based on the device, the test parameters and the test instructions can be changed at any time in one test of powering on the DSP chip. Compared with the current common DSP chip testing method, the DSP chip testing device increases the data transmission channels of the FPGA and the server on the basis of completing the basic DSP chip testing function, so that the testing work and the configuration of each parameter are more flexible. Through the server operation interface, the test parameters can be configured in real time and the test instructions can be updated online in the test process without modifying FPGA test engineering codes.

Description

DSP chip testing device and method

technical field

The invention relates to the technical field of DSP chip testing, in particular to a DSP chip testing device and method.

Background technique

With the development of domestic digital signal processing chips, in the early stage of DSP chip research and development, it is necessary to test the functions of DSP chips before using development tools for complete DSP chips, and it is often necessary to use an FPGA-based test platform to test DSP chips. At present, the commonly used DSP chip test device is: according to the characteristics of the DSP chip, design the FPGA test circuit board to connect with the corresponding DSP chip pins, and communicate with the DSP chip, so as to test the function of the DSP chip.

The specific test steps in the related technology are as follows: first step, the FPGA enters the working state after the power-on reset is completed, and the initial state configuration information of the DSP chip is output according to the predetermined value after the FPGA reset is completed. In the second step, the FPGA is in the master mode during data transmission, and sends the DSP test instruction data to the DSP chip from the data ROM pre-stored in the FPGA according to the data transmission timing. In the third step, the FPGA is in slave mode during data transmission, and receives the DSP test results from the IO port according to the data receiving timing and stores them in the corresponding result RAM. The tester accesses the test result data RAM inside the FPGA through the serial port data channel, and according to The DSP test result data judges the correctness of the corresponding function of the DSP chip.

The DSP chip test method under the technical framework realizes the input of DSP chip test instructions and the collection of test result data, but each test can only test the test cases and test parameters pre-stored in the FPGA data ROM, and the replacement of test cases And changing the test parameters needs to re-modify the FPGA test engineering code, and the test results need to be extracted from the FPGA by using serial communication, the test efficiency is low, and the test process is cumbersome.

Contents of the invention

The purpose of the present invention is to at least solve one of the technical problems existing in the prior art, provide a kind of DSP chip test device and method, solve in the DSP chip test, each test can only test the test cases stored in FPGA data ROM in advance And test parameters, leading to technical problems such as low test efficiency and cumbersome test process.

First aspect, the embodiment of the present invention provides a kind of DSP chip testing device, described testing device comprises server and FPGA chip, and described server and described FPGA chip are connected in communication;

Described FPGA chip is used for: receiving the DSP chip test instruction, DSP chip test parameter from server, with described DSP chip test instruction, DSP chip test parameter input to the DSP chip to be tested to test, and obtains to be tested After the DSP chip test result of the DSP chip is obtained, the DSP chip test result is sent to the server; wherein, the DSP chip test result includes a DSP chip operation result.

As a further improvement, the server and the FPGA chip are connected in communication through a PCIE transmission protocol.

As a further improvement, the FPGA chip includes a DMA control logic module, a PCIE interface logic module, a test instruction data cache module, a DSP parameter configuration processing module, a DSP test result RAM module, the PCIE interface logic module, a test instruction data cache module , DSP parameter configuration processing module, DSP test result RAM module are respectively connected with described DMA control logic module;

The PCIE interface logic module is used to realize the PCIE transmission protocol communication between the FPGA chip and the server;

The test instruction data cache module is used to store the machine code of the DSP chip test instruction;

The DSP parameter configuration processing module is used to store the DSP chip test parameters;

The DSP test result RAM module is used to store the operation result of the DSP chip;

The DMA control logic module is used for coordinating the sending, processing and storage of data of each module according to the instructions issued by the server.

As a further improvement, the FPGA chip also includes a DSP data decoding module, which is connected to the DMA control logic module and the DSP test result RAM module respectively;

The DSP data decoding module is used for: decoding the operation result of the original DSP chip, so as to extract the operation data and save it in the corresponding DSP test result RAM module.

As a further improvement, the test device further includes an FPGA test board, and the FPGA chip is installed on the FPGA test board.

As a further improvement, the test device further includes a DSP test board, and the DSP chip to be tested is installed on the DSP test board.

Second aspect, the embodiment of the present invention provides a kind of DSP chip testing method, is provided with server, FPGA chip, the DSP chip to be tested, server and the DSP chip to be tested are respectively connected with described FPGA chip communication, and described testing method comprises :

Receive the DSP chip test instruction and the DSP chip test parameter from the server, and input the DSP chip test instruction and the DSP chip test parameter to the DSP chip to be tested for testing;

After obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server; wherein, the DSP chip test result includes a DSP chip operation result.

As a further improvement, the server and the FPGA chip are connected in communication through a PCIE transmission protocol.

As a further improvement, the receiving of DSP chip test instructions and DSP chip test parameters from the server specifically includes the following steps:

Use DMA to control the FPGA chip to receive DSP chip test instructions and DSP chip test parameters from the server through the PCIE transmission protocol.

As a further improvement, after obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server, which specifically includes the following steps:

After obtaining the DSP chip test result of the DSP chip to be tested, the original operation result of the DSP chip is decoded, and the decoded DSP chip test result is sent to the server.

Beneficial effects: the above-mentioned DSP chip testing device and method provide a DSP chip automatic test implementation device for the problems of low test efficiency and cumbersome test process in the current DSP chip test method. Based on this device, it is possible to change test parameters and test instructions at any time during a test of DSP chip power-on. Compared with the commonly used DSP chip test method, the DSP chip test device has added the data transmission channel between FPGA and server on the basis of completing the basic DSP chip test function, so that the test work and the configuration of various parameters are more flexible. Through the server operation interface, test parameters can be configured in real time and test instructions can be updated online during the test without modifying the FPGA test engineering code. During the test, the tester only needs to write the DSP test command in the form of digital text into the test command data cache module of the FPGA development board through the server, input the start test command, and then start the DSP chip function test, and wait for the test to be completed and read it through the server The FPGA test result RAM module obtains the DSP return calculation data in the form of data text, and the DS chip developer can judge the test result.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is further described;

Fig. 1 is a block diagram of the DSP chip testing environment of the DSP chip testing device in one embodiment.

Fig. 2 is a schematic flow chart of a method for testing a DSP chip in one embodiment.

Fig. 3 is a schematic flow chart of a method for testing a DSP chip in another embodiment.

Fig. 4 is a schematic diagram of a decoding process for decoding the operation result of the original DSP chip in an embodiment.

Detailed ways

This part will describe the specific embodiment of the present invention in detail, and the preferred embodiment of the present invention is shown in the accompanying drawings. Each technical feature and overall technical solution of the invention, but it should not be understood as a limitation on the protection scope of the present invention.

In the prior art, in each DSP chip test, only the test cases and test parameters pre-stored in the FPGA data ROM can be tested, resulting in low test efficiency and cumbersome test process.

In order to solve the problems of the technologies described above, design concept of the present invention is: DSP chip testing device block diagram as shown in Figure 1, DSP chip automatic testing realization device mainly is made up of X86 testing server, FPGA testing console and DSP chip testing circuit board. The X86 test server uses the machine code file as the test instruction of the DSP chip. The instruction is stored on the test server in the form of a hexadecimal file, and the instruction file is DMAed into the instruction cache inside the FPGA test console through the PCIE interface. According to the working sequence of DSP, FPGA will DMA the test instruction into the instruction cache of DSP chip to start the test. After the DSP operation is completed, the FPGA test console will first store the test result data in the internal cache, and then use the DMA interface through the PCIE interface to start the test. The test results are sent to the chip test server for saving, and compared with the standard results of the test cases.

The X86 server is responsible for loading DSP chip parameter configuration information, test instruction codes, controlling the test process of the FPGA console and the output of test operation results, and printing the test operation results. The FPGA test console is responsible for processing the test instructions of the X86 server and sending them to the DSP chip test board for calculation, collecting the calculation results and sending them back to the X86 test server. During the test, the tester first writes the test instructions in the form of hexadecimal data into the FPGA test bench through the test server, and then the test server controls the FPGA test bench and writes the test instructions into the DSP chip for calculation. The operation of the DSP chip The results are first stored in the cache of the FPGA test bench, and the test server is responsible for controlling and analyzing the test results everywhere.

In order to facilitate those skilled in the art to understand the present invention, the technical terms involved in the present invention are described below.

FPGA (Field Programmable Gate Array, Chinese name: Field Programmable Logic Gate Array) is a product of further development on the basis of programmable devices such as PAL and GAL. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates.

DSP (Digital Signal Processing, Chinese name: Digital Signal Processing) is an emerging discipline that involves many disciplines and is widely used in many fields. Since the 1960s, with the rapid development of computer and information technology, digital signal processing technology has emerged and developed rapidly.

DMA (Direct Memory Access, direct memory access) is an important feature of all modern computers, which allows hardware devices of different speeds to communicate without relying on a large interrupt load of the CPU. Otherwise, the CPU needs to copy each fragment's data from the source to the scratchpad, and then write them back again to the new location.

RAM (English: Random Access Memory, Chinese: Random Access Memory), also called main memory, is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except when refreshing), and the speed is very fast, and it is usually used as a temporary data storage medium for the operating system or other running programs. When RAM is working, information can be written (stored) or read (taken out) from any specified address at any time. The biggest difference between it and ROM is the volatility of data, that is, the stored data will be lost once the power is turned off. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results.

The board card is a printed circuit board, referred to as PCB board, which has a ferrule when it is produced, and can be inserted into the slot of the main circuit board (main board) of the computer to control the operation of hardware, such as monitors, acquisition cards and other equipment. , after installing the driver, the corresponding hardware functions can be realized.

In the following, the DSP chip testing device provided by the embodiment of the present invention will be introduced and illustrated in detail through several specific embodiments.

As shown in FIG. 1 , in one embodiment, a DSP chip testing device is provided. The test device includes a server and an FPGA chip, and the server and the FPGA chip are connected in communication; the FPGA chip is used to: receive DSP chip test instructions and DSP chip test parameters from the server, and input the DSP chip test instructions and DSP chip test parameters to the DSP to be tested The chip is tested, and after obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server; wherein, the DSP chip test result includes the DSP chip operation result.

It can be understood that the data transmission channel between the FPGA and the server is added to the DSP chip test device. After loading the relevant driver, the server can input the relevant test instructions to configure the DSP chip test parameters, test instructions and read test result files. The flexibility of DSP chip test parameter adjustment, test instruction and test result transmission is realized. Without changing the configuration parameters and test instructions of the DSP chip, you only need to input a test instruction to complete a test of the DSP chip. It is very convenient, flexible and fast to repeatedly test the DSP chip in an automated way. test.

Specifically, the communication connection between the server and the FPGA chip is realized through the PCIE transmission protocol. The transmission channel of the DSP chip test configuration parameters, test instructions and test results is based on the data transmission of the PCIE transmission protocol. Compared with the serial data transmission in the traditional test method, the data transmission speed is greatly improved.

With reference to Fig. 1, in some embodiments, FPGA chip comprises DMA control logic module, PCIE interface logic module, test instruction data cache module, DSP parameter configuration processing module, DSP test result RAM module, PCIE interface logic module, test instruction data cache module, DSP parameter configuration processing module, and DSP test result RAM module are respectively connected to the DMA control logic module; the PCIE interface logic module is used to realize the PCIE transmission protocol communication between the FPGA chip and the server; the test instruction data cache module is used to store the DSP chip The machine code of the test instruction; the DSP parameter configuration processing module is used to store the DSP chip test parameters; the DSP test result RAM module is used to store the operation results of the DSP chip; the DMA control logic module is used to coordinate the data of each module according to the instructions issued by the server Send, process and store.

It can be understood that the DMA control logic function in the FPGA test board, the DMA control logic module controls the test process of the DSP chip throughout the process, and is the control center of the entire DSP chip test device, controlling the timing of each signal and the collaborative work of each module The time window ensures the smooth operation of the entire testing process.

With reference to Fig. 1, in some embodiments, FPGA chip also comprises DSP data decoding module, and DSP data decoding module is connected with DMA control logic module and DSP test result RAM module respectively; DSP data decoding module is used for: to the original DSP chip The operation result is decoded so that the operation data can be extracted and saved in the corresponding DSP test result RAM module.

It is understandable that according to the data processing characteristics of the DSP chip, a corresponding data decoding module is developed in the FPGA chip to decode the received DSP chip operation results and extract valid data for storage, which reduces the storage of redundant data and saves data storage space.

Specifically, the test device also includes an FPGA test board, and the FPGA chip is installed on the FPGA test board. The test device also includes a DSP test board, and the DSP chip to be tested is installed on the DSP test board.

It can be understood that by setting the FPGA test board and the DSP test board, the installation of the FPGA chip and the DSP chip is facilitated and the test efficiency is accelerated.

Referring to Fig. 2, the DSP chip testing method is provided with a server, an FPGA chip, and a DSP chip to be tested, and the server and the DSP chip to be tested are respectively connected in communication with the FPGA chip. Specifically, the communication connection between the server and the FPGA chip is realized through the PCIE transmission protocol.

It can be understood that the transmission channel of the DSP chip test configuration parameters, test instructions and test results is based on the data transmission of the PCIE transmission protocol. Compared with the serial port data transmission in the traditional test method, the data transmission speed is greatly improved.

This DSP chip testing method specifically comprises the steps:

Step S102: Receive the DSP chip test command and DSP chip test parameters from the server, and input the DSP chip test command and DSP chip test parameters into the DSP chip to be tested for testing.

It should be noted that receiving the DSP chip test instruction and DSP chip test parameters from the server specifically includes the following steps:

Step S1021: Using DMA to control the FPGA chip to receive the DSP chip test instruction and DSP chip test parameters from the server through the PCIE transmission protocol.

Step S104: After obtaining the DSP chip test result of the DSP chip to be tested, send the DSP chip test result to the server; wherein, the DSP chip test result includes the DSP chip operation result.

It should be noted that after obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server, which specifically includes the following steps:

Step S1041: After obtaining the DSP chip test result of the DSP chip to be tested, decode the original operation result of the DSP chip, and send the decoded DSP chip test result to the server.

It is understandable that according to the data processing characteristics of the DSP chip, a corresponding data decoding module is developed in the FPGA chip to decode the received DSP chip operation results and extract valid data for storage, which reduces the storage of redundant data and saves data storage space.

As shown in Figure 1, the operation provided by this method is mainly on the server side, and a whole set of test software and related drivers dedicated to the DSP chip test hardware platform have been developed on the server side. Chip test parameter configuration, DSP test command input and DSP test result return control, so that the server can control the test process of the entire DSP chip. The FPGA test board is mainly composed of test hardware circuits based on the FPGA chip. The main function of the PCIE interface logic module in the internal logic of the FPGA chip is to exchange information with the server; the test command data cache module stores the machine code of the DSP chip test command for the system Real-time call; the DSP parameter configuration processing module stores the DSP chip test parameters that need to be configured, and controls the configuration of the DSP chip parameters; the DMA control logic module is the top module of the FPGA project, and coordinates the sending and processing of data of each module according to the instructions issued by the server and storage; the DSP data decoding module is responsible for decoding the original DSP chip operation results, so as to extract effective operation data and store them in the corresponding storage module; the DSP test result RAM module is responsible for storing the operation results of the DSP chip.

Referring to Fig. 3, a preferred implementation of the DSP testing method of the present invention is provided, comprising the following steps:

Step 1: DSP chip test preparation. Before the chip test starts, the system needs to be deployed with the software package. The software package deployment includes: FPGA configuration file curing and deployment of PCIE driver. The FPGA test project does not need to be updated due to changes in the DSP chip test instructions and configuration parameters. code, so the developed FPGA configuration file has been saved on the flash chip on the FPGA test board, and it can be loaded automatically after power-on, which greatly improves the test efficiency of the DSP chip. Upload the pcie_driver file to the test server and compile The deployment of the PCIE driver can be completed under the xdma and tools files.

Step 2: Write the DSP chip test instruction into the DSP instruction cache in the FPGA. First, store the prepared 256-bit test instruction machine code file in the specified directory of the server (under any storage directory on the server hard disk), and enter in the server Load the DSP chip test instruction command, and the test instruction file will be imported into the FPGA instruction cache through the PCIE channel for real-time calling during the DSP chip test process.

Step 3: Write the DSP chip test parameters into the FPGA parameter configuration cache, import the test instruction file into the FPGA instruction cache, and before testing the DSP chip, according to the test requirements of the imported test instructions, the Various parameters are configured, and the specific parameters include: DSP chip PLL and basic parameter configuration, DSP test command base address configuration, DSP test command data quantity and command quantity configuration.

Step 4: Input the start test command to start testing the DSP chip. After the start test command is input, the FPGA first calls the configuration parameters in the configuration parameter module, assigns them to the relevant pins of the DSP chip, and configures the relevant internal parameters of the DSP chip as required for the test. value, and then switch to master mode to send the test command in the test command data cache module to the DSP chip according to the timing of the wishbone bus protocol. The operation result is decoded and stored in the corresponding storage module. The decoding and storage process is shown in Figure 4.

Step 5: Obtain the test results of the DSP chip. Obtaining the DSP test results is completed in two steps: first write the result buffer data received by the FPGA into the server cache: after the DSP test is completed, enter the command to read the results in the command window, and the FPGA Send the content in the result cache to the server cache; then, generate the result file from the server cache data: After sending the data in the FPGA result cache to the server, enter the command to generate the result file in the command window to generate the DSP operation result document.

Step 6: After the test is completed, compare the output operation result file with the correct value to judge whether the operation of the DSP chip is correct or not and related performance. So far, a DSP chip test is completed.

The key modules and technical descriptions involved in the embodiments of the present invention are as follows:

1. PCIE channel driver and control instructions between the server and the FPGA test board

The channel driver and control instructions based on the PCIE protocol are the key parts to realize the automatic test. The driver in the service and the PCIE interface logic control module in the FPGA jointly build the channel for the real-time information interaction of the entire DSP chip test device.

2. DMA control logic module

In the realization of this method, the DMA control logic module plays a crucial role, which controls the transmission and interaction of test data between the server and the DSP chip, and executes the test instructions issued by the server and the storage of related data in the FPGA cache. Pick.

3. Decoding storage module for DSP operation results

The design of the DSP chip generally supports 64-bit, 32-bit, 16-bit, 8-bit and other bit-width data operations. The DSP operation result decoding module is based on the DSP chip test instructions issued by the server and the relevant parameter information of the operation results returned by the DSP chip. The data is decoded, and only the valid data is stored in the storage RAM, avoiding the storage of invalid data, effectively improving the utilization rate of the storage space, so that the system supports DSP chip test instructions with a greater amount of calculation.

In summary, a DSP chip testing device and method provided by the embodiments of the present invention have the following advantages:

1. DSP chip automatic test and test parameter real-time configuration function, support real-time change of test cases and test parameters, without changing the test, by configuring test parameters, the DSP chip can work in different working modes and working frequencies, greatly Enhanced the flexibility of DSP chip testing.

2. The channel driver between the server and the FPGA test board and the matching control instructions. The development and use of this functional module enables the testers to realize the human-computer interaction in the DSP test process through the computer screen, to a large extent Improved working environment for testers.

3. The DMA control logic function in the FPGA test board, the DMA control logic module controls the test process of the DSP chip in the whole process, and is the control center of the entire DSP chip test device, controlling the timing between each signal and the time window for the cooperative work of each module , to ensure the smooth running of the testing process.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

Claims (8)

1. a DSP chip testing device, is characterized in that, described testing device comprises server and FPGA chip, and described server and described FPGA chip are communicatively connected; Described FPGA chip is used for: receiving the DSP chip test instruction, DSP chip test parameter from server, with described DSP chip test instruction, DSP chip test parameter input to the DSP chip to be tested to test, and obtains to be tested After the DSP chip test result of DSP chip, described DSP chip test result is sent to described server; Wherein, described DSP chip test result comprises DSP chip operation result; The FPGA chip includes a DMA control logic module, a PCIE interface logic module, a test instruction data cache module, a DSP parameter configuration processing module, a DSP test result RAM module, and the PCIE interface logic module, a test instruction data cache module, and a DSP parameter configuration process Module, DSP test result RAM module are respectively connected with described DMA control logic module; The PCIE interface logic module is used to realize the PCIE transmission protocol communication between the FPGA chip and the server; The test instruction data cache module is used to store the machine code of the DSP chip test instruction; The DSP parameter configuration processing module is used to store the DSP chip test parameters; The DSP test result RAM module is used to store the operation result of the DSP chip; The DMA control logic module is used to coordinate the sending, processing and storage of data of each module according to the instructions issued by the server; Through the server operation interface, test parameters can be configured in real time and test instructions can be updated online during the test without modifying the FPGA test engineering code. 2. DSP chip testing device as claimed in claim 1, is characterized in that, described server and described FPGA chip realize communication connection by PCIE transmission protocol. 3. DSP chip testing device as claimed in claim 1, is characterized in that, described FPGA chip also comprises DSP data decoding module, and described DSP data decoding module is connected with described DMA control logic module and DSP test result RAM module respectively ; The DSP data decoding module is used for: decoding the operation result of the original DSP chip, so as to extract the operation data and save it in the corresponding DSP test result RAM module. 4. DSP chip test device as claimed in claim 1, is characterized in that, described test device also comprises FPGA test board, and described FPGA chip is installed on the described FPGA test board. 5. DSP chip test device as claimed in claim 1, is characterized in that, described test device also comprises DSP test board card, and described DSP chip to be tested is installed on described DSP test board card. 6. a kind of DSP chip test method is characterized in that, server, FPGA chip, the DSP chip to be tested are provided with, and server and the DSP chip to be tested are connected with described FPGA chip communication respectively, and described test method comprises: Receive the DSP chip test instruction and the DSP chip test parameter from the server, and input the DSP chip test instruction and the DSP chip test parameter to the DSP chip to be tested for testing; After obtaining the DSP chip test result of the DSP chip to be tested, the DSP chip test result is sent to the server; wherein, the DSP chip test result includes a DSP chip operation result; Described receiving DSP chip test instruction, DSP chip test parameter from server, specifically comprise the following steps: Use DMA to control the FPGA chip to receive DSP chip test instructions and DSP chip test parameters from the server through the PCIE transmission protocol; Through the server operation interface, test parameters can be configured in real time and test instructions can be updated online during the test without modifying the FPGA test engineering code. 7. a kind of DSP chip testing method according to claim 6 is characterized in that, described server and described FPGA chip realize communication connection by PCIE transmission protocol. 8. a kind of DSP chip test method according to claim 6, is characterized in that, described after obtaining the DSP chip test result of DSP chip to be tested, described DSP chip test result is sent to described server, Specifically include the following steps: After obtaining the DSP chip test result of the DSP chip to be tested, the original operation result of the DSP chip is decoded, and the decoded DSP chip test result is sent to the server.