CN113505030A - Digital signal processor testing device - Google Patents
Digital signal processor testing device Download PDFInfo
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- CN113505030A CN113505030A CN202110667191.7A CN202110667191A CN113505030A CN 113505030 A CN113505030 A CN 113505030A CN 202110667191 A CN202110667191 A CN 202110667191A CN 113505030 A CN113505030 A CN 113505030A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a digital signal processor testing device, comprising: the automatic test platform module is used for sending a control instruction and receiving and uploading a test result; the digital signal processor single-board module is used for being connected with the digital signal processor, leading out a host interface of the digital signal processor, serving as a host test interface and being connected with the test tool module; and one end of the test tool module is connected with the digital signal processor single-board module through the host test interface, and the other end of the test tool module is connected with the automatic test platform module and is used for receiving and analyzing the control instruction sent by the automatic test platform module. The digital signal processor testing device of the invention has the advantages that through the arrangement of the digital signal processor single-board module and the testing tool module, and the testing tool module is communicated with the automatic testing platform module, redundant design requirements are not required in the program, the automatic testing steps are greatly simplified, and the automatic testing strength is improved.
Description
Technical Field
The invention belongs to the technical field of digital signal processor testing, and particularly relates to a digital signal processor testing method and device.
Background
Digital Signal Processors (DSPs) are suitable for performing real-time digital signal processing operations, and are mainly used to quickly implement various digital signal processing algorithms. Its advantages are: the method has the advantages of strong data processing, high operation speed, capability of completing complex calculation, single-cycle multiple-instruction (SIMD), on-chip large-capacity storage, multi-machine interconnection and the like in real time. Therefore, in the background of the modern digital age, the DSP has been widely used in many scientific and engineering fields and becomes a fundamental device in the fields of communication, computers, consumer electronics, and the like.
In order to improve the processing performance of the system, the single board often adopts an array formed by tightly coupling a plurality of DSPs or a plurality of single boards cascaded by a complete machine to meet a large amount of data processing requirements. In the initial stage of product delivery, high-strength automatic test is required, and the test aims at reading and writing verification of a DSP internal memory and an external memory, configuration of a general register and state reading; the automatic test usually needs test tools and scripts to generate related test item reports, and how to conveniently and quickly access internal resources of the DSP is an urgent problem to be solved.
At present, most of loosely-coupled link ports are used for data communication, as shown in fig. 1, the link ports have the advantages of high communication speed, interference resistance and the like, but are relatively limited, a plurality of DSPs are required to be matched, hardware links are complex, and the programming is complex.
Disclosure of Invention
The invention provides a digital signal processor testing device aiming at the technical problems that in the prior art, a digital signal processor testing device adopts a mode of communicating with a digital signal processor at a link, a plurality of DSPs are required to be matched, a hardware link is complex, and the design on a program is complicated, and the digital signal processor testing device can solve the problems.
In order to realize the purpose of the invention, the invention is realized by adopting the following technical scheme:
a digital signal processor testing apparatus, comprising:
the automatic test platform module is used for sending a control instruction, receiving and uploading a test result and generating a test report according to the test result;
the digital signal processor single-board module is used for being connected with the digital signal processor, leading out a host interface of the digital signal processor, serving as a host test interface and being connected with the test tool module;
and one end of the test tool module is connected with the single board module of the digital signal processor through the test interface of the host computer, and the other end of the test tool module is connected with the automatic test platform module and is used for receiving and analyzing the control instruction sent by the automatic test platform module, sending the control instruction to the digital signal processor through the single board module of the digital signal processor, receiving the test result sent by the digital signal processor and sending the test result to the automatic test platform module through the single board module of the digital signal processor.
Further, the automated testing platform module encapsulates the control command into a protocol frame with a self-defined serial interface, and the automated testing platform module includes:
the serial interface is used for carrying out protocol frame communication with the test tool module and carrying out transceiving operation on a protocol frame;
and the serial interface driver can drive the serial interface to carry out bottom layer calling.
Further, the serial interface is a UART interface.
Further, the test tool module also generates a test record in html format, and stores the test record in a database in real time.
Further, the automated testing platform module comprises:
and the test script is used for packing the control instruction of the digital signal processor into an effective data load of a protocol frame and sending the effective data load to the test tool module by calling downlink through application, and the control instruction at least comprises a test item or a test instruction.
Further, the automatic test platform module comprises an industrial personal computer.
Further, the test tool module includes:
the serial port receiving and transmitting module is a serial port communication protocol realized based on a programmable logic device and is used for connecting the serial interface;
the host interface module is connected with the host test interface;
the protocol frame analysis module is used for analyzing the protocol frame;
the state controller module can jump to the functional state according to the functional words in the protocol frame, extract the specific functional words in the data stream, and send the data or the instruction to the single board module of the digital signal processor through the host interface module.
Further, the host interface module is a host interface protocol realized based on a programmable logic device and communicates with the digital signal processor through a bus.
Further, the digital signal processor may be a single-machine digital signal processor, a multi-machine digital signal processor, or a heterogeneous digital signal processor, and when the digital signal processor is a multi-machine digital signal processor, the single board module of the digital signal processor tightly couples the multi-machine digital signal processors together through a bus.
Furthermore, the control instruction also comprises an instruction for uploading a test result, and the digital signal processor returns the test result after receiving the instruction for uploading the test result.
Compared with the prior art, the invention has the advantages and positive effects that:
according to the digital signal processor testing device, the digital signal processor single board module is arranged, the host interface of the digital signal processor is led out to be used as the host testing interface, the digital signal processor can be communicated with the testing tool module through the bus, and the testing tool module is communicated with the automatic testing platform module, so that the automatic testing platform module can conveniently and quickly access the single-core, multi-core and heterogeneous digital signal processors. The test tool module can receive and forward communication signals between the automatic test platform module and the digital signal processor, and compared with a traditional access mode passing through a link port, redundant design requirements are not required in the process, the automatic test steps are greatly simplified, and the automatic test strength is improved.
Other features and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a communication schematic diagram of a prior art DSP test apparatus;
FIG. 2 is a schematic block diagram of a prior art digital signal processor testing apparatus;
FIG. 3 is a schematic block diagram of the automated test platform module of FIG. 2;
FIG. 4 is a schematic block diagram of the test tool module of FIG. 2;
fig. 5 is a schematic view of a communication principle between the test tool module and the single board digital signal processor module in fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that in the description of the present invention, the terms of direction or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example one
The embodiment provides a digital signal processor testing device, as shown in fig. 2, including an automated testing platform module, a digital signal processor single board module, and a testing tool module. Wherein:
the automatic test platform module is used for sending a control instruction, receiving and uploading a test result and generating a test report according to the test result.
The digital signal processor single-board module is used for being connected with the digital signal processor, leading out a host interface of the digital signal processor, and serving as a host test interface for being connected with the test tool module.
The digital signal processor single board module is arranged to lead out a host interface of the digital signal processor to be used as a host test interface, so that the digital signal processor and the test tool module can communicate through a bus, and the test tool module can conveniently and quickly access the single-core, multi-core and heterogeneous digital signal processors.
One end of the test tool module is connected with the single board module of the digital signal processor through the test interface of the host computer, and the other end is connected with the automatic test platform module, and the test tool module is used for receiving and analyzing the control instruction sent by the automatic test platform module, sending the control instruction to the digital signal processor through the single board module of the digital signal processor, receiving the test result sent by the digital signal processor, and sending the test result to the automatic test platform module through the single board module of the digital signal processor.
The test tool module is communicated with the automatic test platform module, so that the automatic test platform module can quickly access single-core, multi-core and heterogeneous digital signal processors, compared with the traditional access mode through a link port, redundant design requirements are not required in the program, the automatic test steps are greatly simplified, and the automatic test strength is improved.
The digital signal processor to be tested of the digital signal processor testing device of the embodiment may be a single digital signal processor, a multi-machine digital signal processor, or a heterogeneous digital signal processor, and particularly, when the digital signal processor is directed to a multi-machine digital signal processor and a heterogeneous digital signal processor, the digital signal processors transmit and receive data independently from each other, and the effect is particularly remarkable.
When the dsp is a multi-machine dsp, as shown in fig. 5, the dsp board module tightly couples the multi-machine dsp together through the bus. Therefore, the test tool module can access the internal general register and the internal and external storage of each digital signal processor through the bus, and independently access each digital signal processor, so that the transmission efficiency is improved, the test strength of the single board and the whole machine can be improved, and the final stability and reliability of the product can be ensured.
The single-machine or multi-machine digital signal processor is tightly coupled together through an external bus and used for receiving instructions or data from the test tool and returning a specific test result.
As shown in fig. 3, the automatic test platform module in this embodiment encapsulates the control command into a protocol frame with a self-defined serial interface, and the automatic test platform module includes a serial interface and a serial interface driver, where:
the serial interface is used for carrying out protocol frame communication with the test tool module and carrying out transceiving operation on the protocol frame;
the serial interface driver can drive the serial interface to perform bottom layer calling.
The main hardware platform of the automatic test platform module is an industrial personal computer, the test function is developed based on a script language, and a relevant test report can be generated aiming at each function and performance of the digital signal processor. Through serial interface on the industrial computer, can dock with the serial interface on the test fixture module. The test tool module can analyze a self-defined protocol frame of the serial interface, the frame is used for indicating whether to send a test instruction or upload a test result, and the format of the specific protocol frame is shown in table 1.
TABLE 1
The serial interface in this embodiment may be, but is not limited to, a UART interface.
The corresponding serial interface drive is a serial interface UART drive, and the drive is loaded in an industrial personal computer system and can call the bottom layer of the physical serial interface; the application calling is an upper computer operation interface developed based on an industrial personal computer system, and is mainly used for calling a bottom-layer serial port drive through an API (application programming interface) interface and performing transceiving operation on a protocol frame.
The automated testing platform module of this embodiment further comprises:
and the test script is used for packing the control instruction of the digital signal processor into an effective data load of a protocol frame and sending the effective data load to the test tool module by calling downlink through application, and the control instruction at least comprises a test item or a test instruction.
The test tool module also generates a test record in an html format, and stores the test record in a database in real time so that a tester can call and check the test record at any time.
As shown in fig. 4, the test fixture module includes a serial port transceiver module, a host interface module, a protocol frame analysis module and a state controller module, wherein:
the serial port receiving and transmitting module is a serial port communication protocol realized based on a programmable logic device, is used for connecting the serial port and can be seamlessly butted with the serial port of the automatic test platform.
The host interface module is connected with the host test interface.
The host interface module is preferably a host interface protocol implemented based on a programmable logic device and communicates with the digital signal processor via a bus.
In this embodiment, the host interface protocol may be, but is not limited to, a write-read-four mode, that is, the pipe depth of a write operation is 1, and the pipe depth of a read operation is 4.
The programmable logic device realizes related control logic and host interface protocol, switches state of the state machine according to the analyzed function, and is in butt joint with the single board module of the digital signal processor through the host interface sub-module to send data or instructions to the digital signal processor through the host interface. On the other hand, the test result instruction frame from the digital signal processor is received through the host interface and is sent to the automatic test platform module through the UART interface.
The protocol frame analyzing module is used for analyzing the protocol frame to obtain the related functions.
The state controller module can jump to the functional state according to the functional words in the protocol frame, extract the specific functional words in the data stream, and send the data or the instruction to the single board module of the digital signal processor through the host interface module.
The control instruction also comprises an instruction for uploading a test result, and the digital signal processor returns the test result after receiving the instruction for uploading the test result.
The method and the device for accessing the digital signal processor through the host interface can conveniently and quickly access the digital signal processor with single core, multiple cores and heterogeneous structure, do not need redundant design requirements on a program compared with the traditional mode of passing through a link, greatly simplify the automatic testing steps and improve the automatic testing strength.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. A digital signal processor testing apparatus, comprising:
the automatic test platform module is used for sending a control instruction, receiving and uploading a test result and generating a test report according to the test result;
the digital signal processor single-board module is used for being connected with the digital signal processor, leading out a host interface of the digital signal processor, serving as a host test interface and being connected with the test tool module;
and one end of the test tool module is connected with the single board module of the digital signal processor through the test interface of the host computer, and the other end of the test tool module is connected with the automatic test platform module and is used for receiving and analyzing the control instruction sent by the automatic test platform module, sending the control instruction to the digital signal processor through the single board module of the digital signal processor, receiving the test result sent by the digital signal processor and sending the test result to the automatic test platform module through the single board module of the digital signal processor.
2. The digital signal processor testing device of claim 1,
the automatic test platform module encapsulates the control instruction into a protocol frame with a self-defined serial interface, and comprises:
the serial interface is used for carrying out protocol frame communication with the test tool module and carrying out transceiving operation on a protocol frame;
and the serial interface driver can drive the serial interface to carry out bottom layer calling.
3. The digital signal processor testing device of claim 2, wherein the serial interface is a UART interface.
4. The digital signal processor testing device of claim 2, wherein the test fixture module further comprises a means for generating a test record in html format and storing the test record in the database in real time.
5. The digital signal processor testing device of claim 4, wherein the automated test platform module comprises:
and the test script is used for packing the control instruction of the digital signal processor into an effective data load of a protocol frame and sending the effective data load to the test tool module by calling downlink through application, and the control instruction at least comprises a test item or a test instruction.
6. The digital signal processor testing device of claim 4, wherein the automated testing platform module comprises an industrial personal computer.
7. The digital signal processor testing device of claim 1, wherein the test fixture module comprises:
the serial port receiving and transmitting module is a serial port communication protocol realized based on a programmable logic device and is used for connecting the serial interface;
the host interface module is connected with the host test interface;
the protocol frame analysis module is used for analyzing the protocol frame;
the state controller module can jump to the functional state according to the functional words in the protocol frame, extract the specific functional words in the data stream, and send the data or the instruction to the single board module of the digital signal processor through the host interface module.
8. The dsp testing apparatus of claim 7, wherein the host interface module is a host interface protocol implemented based on a programmable logic device and communicates with the dsp through a bus.
9. The dsp test apparatus as set forth in any one of claims 1 to 8, wherein the dsp can be a single-machine dsp, a multi-machine dsp or a heterogeneous dsp, and when the dsp is a multi-machine dsp, the dsp board module tightly couples the multi-machine dsp through a bus.
10. The digital signal processor testing device of any one of claims 1-8, wherein the control instructions further comprise instructions to upload test results, and the digital signal processor returns the test results after receiving the instructions to upload the test results.
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| US5541862A (en) * | 1994-04-28 | 1996-07-30 | Wandel & Goltermann Ate Systems Ltd. | Emulator and digital signal analyzer |
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| CN102448098A (en) * | 2010-09-30 | 2012-05-09 | 重庆重邮信科通信技术有限公司 | Physical layer test system and method based on ARM (advanced RISC (reduced instruction set computer) machine) and DSP (digital signal processing) multi-core structure |
| CN106680697A (en) * | 2016-12-08 | 2017-05-17 | 西安电子科技大学 | Test detector of digital signal processor |
| CN112014726A (en) * | 2020-08-05 | 2020-12-01 | 广东省新一代通信与网络创新研究院 | DSP chip testing device and method |
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- 2021-06-16 CN CN202110667191.7A patent/CN113505030A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541862A (en) * | 1994-04-28 | 1996-07-30 | Wandel & Goltermann Ate Systems Ltd. | Emulator and digital signal analyzer |
| CN102375778A (en) * | 2010-08-17 | 2012-03-14 | 中兴通讯股份有限公司 | Method and system for automatically testing digital signal processor (DSP) |
| CN102448098A (en) * | 2010-09-30 | 2012-05-09 | 重庆重邮信科通信技术有限公司 | Physical layer test system and method based on ARM (advanced RISC (reduced instruction set computer) machine) and DSP (digital signal processing) multi-core structure |
| CN106680697A (en) * | 2016-12-08 | 2017-05-17 | 西安电子科技大学 | Test detector of digital signal processor |
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