CN101770416B - Bus testing method for new generation of peripheral connecting interface - Google Patents
Bus testing method for new generation of peripheral connecting interface Download PDFInfo
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- CN101770416B CN101770416B CN200910003438A CN200910003438A CN101770416B CN 101770416 B CN101770416 B CN 101770416B CN 200910003438 A CN200910003438 A CN 200910003438A CN 200910003438 A CN200910003438 A CN 200910003438A CN 101770416 B CN101770416 B CN 101770416B
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Abstract
A bus testing method for a new generation of peripheral connecting interface is used for monitoring a bus pressure test for the new generation of peripheral connecting interface (Peripheral Component Interconnect Express). The method comprises the following steps of: installing a peripheral device and electrically connecting the peripheral device to the new generation of peripheral connecting interface of a host machine to be tested; initializing the host machine to be tested and loading a test program; executing the test program, calling a reliable driving (program) module (PCIE PAS Service)by the host machine to be tested through the bus of the new generation of peripheral connecting interface to drive the peripheral device and transmitting a test signal to the peripheral device; receiving reply information transmitted by the peripheral device by a monitoring interface; when the reply information is wrong information, calling a corresponding error processing program; and adjusting test parameters of the test program until all test parameters are completed.
Description
Technical field
A kind of bus test method is particularly to a kind of method of bus test process that can real time monitoring new generation of peripheral connecting interface (PCIE).
Background technology
(Peripheral Component Interconnect Express, PCIE) bus is that its quality good or not of the important system bus of motherboard is determining stability and the high efficiency between system and the chipset (chipset) to new generation of peripheral connecting interface.Particularly, very high to the function and the requirements such as performance and long-time pressure load of bus to the advanced server product.
Testing scheme in the past roughly can reduce following two kinds of patterns:
1. memory read-write pattern, this method just are to use software program to order about new generation of peripheral to connect peripheral equipment and carry out data transmission, and one section physical memory of promptly in program, the equipment of some new generation of peripheral connecting interface being videoed is done read-write operation.
2. direct access internal memory (Direct Memory Access; DMA) read-write mode; This method is more near the operation of bottom than first kind; Its method of mainly using is exactly on the new generation of peripheral connecting interface slot of correspondence, equipment under test to be installed, and then carries out the test of DMA data carrying through software arrangements and driving arrangement.
Above two kinds of method of testings have certain effect, especially aspect functional test, but along with accurate testing degree and data flow can be improved constantly in handling requirement, above the deficiency of two kinds of methods just come out, concrete manifestation is following:
1. the data flow of test is too loaded down with trivial details for test purpose.
2. can't keep the volume of transmitted data that continues exactly within a certain period of time.
3. can consume certain system resource in the test process.
4. test target can not clearly embody.
Therefore; Existing new generation of peripheral connecting interface testing scheme is slightly inadequate to server; Too lay particular stress on new generation of peripheral connecting interface slot and new generation of peripheral connecting interface apparatus function (PCI Device Function); This does not have actual help for the monitoring and error trapping in real time of new generation of peripheral connecting interface bus efficiency.
Summary of the invention
In view of above problem, fundamental purpose of the present invention is to provide a kind of method of bus test process that can the real time monitoring new generation of peripheral connecting interface, is used for keeping watch on the pressure test of the bus of new generation of peripheral connecting interface.
For reaching above-mentioned purpose, the disclosed method of the present invention may further comprise the steps: peripheral equipment is set, it is electrically connected at the new generation of peripheral connecting interface bus of main frame to be measured; Initialization main frame to be measured, and load test procedure; Carry out test procedure, make main frame to be measured call the reliability driver module and be used for driving peripheral equipment, and send test massage to peripheral equipment through the new generation of peripheral connecting interface bus; The return information that reception is passed back by peripheral equipment; Monitoring interface receives the return information of being passed back by peripheral equipment; When return information is error message, then call the corresponding error handling procedure; The test parameter of adjustment test procedure is till accomplishing all test parameters.
The present invention provides a kind of bus test method of new generation of peripheral connecting interface, and it is used for diagnosing the operating state of new generation of peripheral connecting interface bus.Send various test parameters according to test procedure, thereby test new generation of peripheral connecting interface bus is to the support of each item module.
About technical characterictic of the present invention and specific embodiment, at length most preferred embodiment is explained as follows with reference to accompanying drawing.
Description of drawings
Figure 1A is a configuration diagram of the present invention;
Figure 1B is a new generation of peripheral connecting interface transmission architecture synoptic diagram;
Fig. 2 is a configuration diagram of the present invention;
Fig. 3 reliability driver module calls the synoptic diagram of each module.
Wherein, Reference numeral
110 main frames to be measured
120 peripheral equipments
130 new generation of peripheral connecting interface buses
131 device cores
132 core logic interfaces
133 exchange layers
134 datalink layer connections
135 Physical layers
140 test procedures
300 reliability driver modules
310 new generation of peripheral connecting interface people having the same aspiration and interest detection modules
320 new generation of peripheral connecting interface are provided with the inspection module
330 new generation of peripheral connecting interface degradation detection module
340 new generation of peripheral connecting interface usefulness distribution module
350 error detection module
360 log files
370 monitor-interfaces
Embodiment
Please refer to shown in Figure 1A, it is a configuration diagram of the present invention.In test macro of the present invention, include: main frame 110 to be measured and peripheral equipment 120.In main frame 110 to be measured, comprise at least one new generation of peripheral connecting interface bus 130.Peripheral equipment 120 has a new generation of peripheral connecting interface and test procedure 140, and is electrically connected at main frame 110 to be measured through its bus.Please refer to shown in Figure 1B, it is a new generation of peripheral connecting interface transmission architecture synoptic diagram.
Be respectively different new generation of peripheral connecting interface devices at Figure 1B right and left.From top to bottom be respectively device core 131, core logic interface 132, exchange layer 133, datalink layer connection 134 and Physical layer 135 at Figure 1B.
The connection of new generation of peripheral connecting interface is to be based upon on (1-bit) point-to-point connection basis of a two-way sequence, and this is referred to as transmission channel.Physical layer makes aspect the power consumption, and every group of streamline uses two unidirectional low-voltage differential signals, so delivery flow rate can reach 2.5 megabyte.Transmit and receive different pieces of information and can use different distribution channel, each passage can operate four association.Two new generation of peripheral connect the binding that is connected to become between the peripheral equipment, and this has formed 1 group or more transmission channel.The connection of minimum support 1 transmission channel of each equipment (x1).Also can have 2,4,8,16, the connection of 32 passages.
Datalink layer connection adopts exchange layer packets of information (Transaction Layer Packets is called for short TLPs) according to priority, and it is to be generated by the exchange layer.TLPs can be through 32 CRCs and continuity verification be called Ack (ACK); Be not called Nak (not replying) through verification.The TLPs that does not reply or the TLPs of wait timeout can be by transmission again.These content stores are in the buffer memory of datalink layer connection.The transmission that can guarantee TLPs is not like this disturbed by electronic noise.
Please with reference to shown in Figure 2, it is a configuration diagram of the present invention.The bus test method of new generation of peripheral connecting interface of the present invention may further comprise the steps:
At first, peripheral equipment (step S210) is set, it is electrically connected at the new generation of peripheral connecting interface bus 130 of main frame 110 to be measured;
Initialization main frame to be measured (step S220), and load test procedure 140;
Set the interval between diagnosis (step S230) of test procedure; Wherein, interval between diagnosis can be set at five minutes, ten minutes or 30 minutes.
Carry out test procedure (step S240), make main frame 110 to be measured call the reliability driver module and be used for driving peripheral equipment 120, and send test massage to peripheral equipment 120 through new generation of peripheral connecting interface bus 130;
The return information that reception is passed back by peripheral equipment (step S250);
Judge the content (step S260) of return information;
When return information is during for error message, then call corresponding error handling procedure (step S270);
The test parameter of adjustment test procedure is till accomplishing all test parameters (step S280); And
At last, record log file (step S290), parameters when being used for writing down main frame 110 to be measured and carrying out test procedures 140 or result's record.
The reliability driver module can call new generation of peripheral connecting interface people having the same aspiration and interest detection module (PCIE Coherent Check Module) 310 in step S230, new generation of peripheral connecting interface is provided with inspection module (PCIE Configuration Check Module) 320, new generation of peripheral connecting interface degradation detection module (PCIE Degrade Check Module) 330 or new generation of peripheral connecting interface usefulness distribution module (PCIE performance Dispatch Trap Module) 340; Wherein, new generation of peripheral connecting interface usefulness distribution module (PCIE performance Dispatch Trap Module) 340 is connected with error detection module (Fault Handler Module) 350.
In step S240, test procedure 140 is the new generation of peripheral connecting interface buses 130 that device core 131, core logic interface 132, exchange layer 133, datalink layer connection 134 and Physical layer 135 are sent to each item test signal in main frame 110 to be measured of passing through successively.
Please refer to shown in Figure 3ly, it is that reliability drives the synoptic diagram of each module of (program) module invokes.Test parameter is the address searching scope of faults type, pressure rank and new generation of peripheral connecting interface bus.Drive in the operation of (program) module 300 in reliability, test procedure 140 can be provided with electromagnetism mistake (ECC Error inQPI), the same bit-errors of new generation of peripheral connecting interface header file (PCIE Header Parity Error) checking wrong (PCIE Config Error), express passway and connect to new generation of peripheral connecting interface people having the same aspiration and interest faults (PCIE Bus coherent error), new generation of peripheral connecting interface respectively and with new generation of peripheral connecting interface same bit-errors each item mistakes such as (PCIE Configuration Error Parity) is set and detect.After the test of accomplishing each bout, its record is write in the log file 360.When testing each time, monitor-interface 370 can receive the return information of being passed back by peripheral equipment, and return information is offered the user in real time.
In step 270, when return information is the usefulness assignment error, then make the wrong pin in the new generation of peripheral connecting interface bus 130 not produce effect (disable) by test procedure 140 call error calling programs.
The present invention provides a kind of bus test method of new generation of peripheral connecting interface, and it is used for diagnosing the operating state of new generation of peripheral connecting interface bus 130.Send various test parameters according to test procedure 140, thus the support of 130 pairs of each item modules of test new generation of peripheral connecting interface bus.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (8)
1. the bus test method of a new generation of peripheral connecting interface, the bus that is used for testing new generation of peripheral connecting interface is carried out the pressure test of data transmission, it is characterized in that this bus test method may further comprise the steps:
A) peripheral equipment is set, it is electrically connected at a new generation of peripheral connecting interface bus of a main frame to be measured;
B) this main frame to be measured of initialization, and load a test procedure;
C) carry out this test procedure, make this main frame to be measured call a reliability driver module and be used for driving this peripheral equipment, and send a test signal to this peripheral equipment through this new generation of peripheral connecting interface bus;
D) receive a return information of passing back by this peripheral equipment;
E) judge the content of this return information;
F) when this return information be when being an error message, then call a corresponding error handler; And
G) adjust a test parameter of this test procedure, till accomplishing this all test parameters.
2. the bus test method of new generation of peripheral connecting interface according to claim 1; It is characterized in that this reliability driver module calls new generation of peripheral connecting interface people having the same aspiration and interest detection module respectively, new generation of peripheral connecting interface is provided with inspection module, new generation of peripheral connecting interface degradation detection module, new generation of peripheral connecting interface usefulness distribution module or error detection module.
3. the bus test method of new generation of peripheral connecting interface according to claim 1 is characterized in that, said step f more may further comprise the steps:
When this return information is during for the usefulness assignment error, then call an error calls program and be used for making the wrong pin in this new generation of peripheral connecting interface bus not produce effect by this test procedure.
4. the bus test method of new generation of peripheral connecting interface according to claim 1 is characterized in that, this test parameter includes: a faults type, a pressure rank, a new generation of peripheral connecting interface bus address search area.
5. the bus test method of new generation of peripheral connecting interface according to claim 1 is characterized in that, in carrying out this test procedure, more may further comprise the steps:
Set the interval between diagnosis of this test procedure.
6. the bus test method of new generation of peripheral connecting interface according to claim 5 is characterized in that, the interval between diagnosis of this test procedure was respectively five minutes, ten minutes or 30 minutes.
7. the bus test method of new generation of peripheral connecting interface according to claim 1 is characterized in that, more comprises the step that writes down log file, to be used for writing down each item record that this main frame to be measured is carried out this test procedure.
8. the bus test method of new generation of peripheral connecting interface according to claim 1 is characterized in that, more comprises the step that receives the return information of being passed back by this peripheral equipment through a monitor-interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910003438A CN101770416B (en) | 2009-01-05 | 2009-01-05 | Bus testing method for new generation of peripheral connecting interface |
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| CN200910003438A CN101770416B (en) | 2009-01-05 | 2009-01-05 | Bus testing method for new generation of peripheral connecting interface |
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| CN101770416A CN101770416A (en) | 2010-07-07 |
| CN101770416B true CN101770416B (en) | 2012-09-05 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103533045B (en) * | 2013-10-12 | 2017-12-29 | 丁贤根 | A kind of method fault-tolerant for PCIE data link layer high-performance |
| CN104699584A (en) * | 2015-03-20 | 2015-06-10 | 浪潮集团有限公司 | PCIE non-transparent bridge performance testing method |
| CN106445751A (en) * | 2016-08-30 | 2017-02-22 | 大唐微电子技术有限公司 | Debugging board, debugging system and debugging method |
| CN112000533B (en) * | 2020-08-14 | 2023-03-31 | 北京浪潮数据技术有限公司 | PCIE equipment bus test method and test tool |
| CN112416682B (en) * | 2020-11-28 | 2022-02-25 | 郑州信大捷安信息技术股份有限公司 | Method and system for supporting simultaneous testing of multiple PCIE cards |
| CN112416683B (en) * | 2020-11-28 | 2022-02-11 | 郑州信大捷安信息技术股份有限公司 | Asynchronous high-performance test method and system for PCIE card |
| CN112416684B (en) * | 2020-11-28 | 2022-02-11 | 郑州信大捷安信息技术股份有限公司 | Asynchronous test method and system based on multiple virtual PCIE cards |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200944233Y (en) * | 2006-07-31 | 2007-09-05 | 英业达股份有限公司 | Universal serial bus testing device |
| CN101105764A (en) * | 2006-07-12 | 2008-01-16 | 华硕电脑股份有限公司 | Computer element fault-detecting method before prosecution of computer operation system and module |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105764A (en) * | 2006-07-12 | 2008-01-16 | 华硕电脑股份有限公司 | Computer element fault-detecting method before prosecution of computer operation system and module |
| CN200944233Y (en) * | 2006-07-31 | 2007-09-05 | 英业达股份有限公司 | Universal serial bus testing device |
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