CN112804443A - Image processing method and high-speed intelligent camera applying same - Google Patents
Image processing method and high-speed intelligent camera applying same Download PDFInfo
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Abstract
An image processing method and a high-speed intelligent camera using the same are provided, wherein the image processing method comprises the following steps: the image sensor converts the acquired optical signal into original image data and transmits the original image data to the FPGA; the FPGA preprocesses the original image data to generate preprocessed image data; the FPGA transmits the preprocessed image data to an image processing chip; and the image processing chip processes the preprocessed image data to generate image data. The image processing method realizes high-speed and low-power consumption real-time image processing through the cooperative work of the image processing chip and the FPGA, and provides a technical basis for the application of a high-speed intelligent camera.
Description
Technical Field
The invention relates to the technical field of imaging, in particular to an image processing method and a high-speed intelligent camera applying the same.
Background
With the improvement of the integrated circuit technology level and the sensor design level, the development of high-speed image sensors is rapid. The high-speed image sensor has a high frame rate and generates a large amount of data, and thus, a higher requirement is placed on real-time image processing. The existing high-speed image processing means generally has the characteristics of high power consumption and large volume, and limits the application scene of a high-speed camera system. Therefore, how to design an image processing method applied to a high-speed smart camera is a problem that needs to be solved urgently in the industry at present.
Disclosure of Invention
In view of the above, the present invention provides an image processing method and a high-speed smart camera using the same, so as to at least partially solve at least one of the above-mentioned technical problems.
In order to achieve the purpose, the technical scheme of the invention comprises the following steps:
as an aspect of the present invention, there is provided an image processing method applied to a high-speed smart camera, including:
the image sensor converts the collected optical signals into original image data and transmits the original image data to the FPGA;
the FPGA preprocesses the original image data to generate preprocessed image data;
the FPGA transmits the preprocessed image data to an image processing chip; and
the image processing chip processes the preprocessed image data to generate image data.
As another aspect of the present invention, there is also provided a high-speed smart camera including:
the image sensor is used for converting the collected optical signals into original image data and transmitting the original image data to the FPGA;
the FPGA is used for preprocessing the original image data to generate preprocessed image data; transmitting the preprocessed image data to an image processing chip;
and the image processing chip is used for processing the preprocessed image data to generate an image data image.
Based on the technical scheme, compared with the prior art, the invention has at least one or one part of the following beneficial effects:
the image processing method provided by the invention realizes high-speed and low-power consumption real-time image processing through the cooperative work of the image processing chip and the FPGA (Field Programmable Gate Array), and provides a technical basis for the application of a high-speed intelligent camera;
the FPGA is respectively connected with an HDMI (High Definition Multimedia Interface) and an optical fiber Interface, so that real-time display and High-speed storage of image data are realized;
when the FPGA and the image processing chip prepare image data and the memories are idle, the image data are transmitted, so that the loss of the image data is avoided to the maximum extent;
the algorithm instructions and parameters for image processing of the image processing chip are configured by the FPGA, and the configuration mode can be manual configuration or automatic configuration, is more flexible and can adapt to the requirements of different application scenes;
before the FPGA transmits the preprocessed image data to the image processing chip, the FPGA preprocesses the original image data so as to improve the processing precision of the subsequent image processing chip.
Drawings
Fig. 1 schematically shows a flow chart of an image processing method provided by an embodiment of the present invention;
FIG. 2 schematically illustrates a block diagram of a high-speed smart camera provided by an embodiment of the invention;
fig. 3 is a diagram schematically illustrating a structure of an image sensor sub-board provided by an embodiment of the present invention;
fig. 4 schematically shows a structural diagram of an image processing motherboard provided by an embodiment of the present invention.
[ description of reference ]
1. Optical lens 2, housing
3. Image processing motherboard 4 and image sensing daughter board
5. HDMI 6, ten thousand million optic fibre interface
7. Motherboard connector 8 and image processing chip
9. FPGA 10 and motherboard body
11. Daughter board connector 12 and image sensor
13. Daughter board body
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
As an aspect of the present invention, there is provided an image processing method applied to a high-speed smart camera, referring to fig. 1, including operations S101 to S104.
The image sensor converts the collected optical signal into raw image data and transmits the raw image data to the FPGA in operation S101.
In operation S102, the FPGA preprocesses the original image data to generate preprocessed image data.
According to other embodiments of the present invention, after the image sensor generates the original image data, the original image data is transmitted to the FPGA, the original image data is cached inside the FPGA, and after one complete image data is cached, the original image data is preprocessed.
According to the embodiment of the invention, the preprocessing of the original image data by the FPGA may include one or more of image brightness adjustment, image dead pixel restoration, and image noise suppression of the original image data by the FPGA.
According to the embodiment of the invention, the FPGA is used for preprocessing the original image data to enhance the original image, for example, the contrast, the brightness and the like of the original image are enhanced, the signal to noise ratio is improved, and the display quality and the accuracy of a subsequent algorithm are improved.
According to the embodiment of the invention, the image sensor adopting the CMOS process has high integration level, the distances between the photoelectric sensing elements and circuits are very close, and the mutual optical, electrical and magnetic interference is serious, so that the influence of noise on the image quality is great. After the image sensor converts the optical signal into the original image data, the original image data is sent to the FPGA for preprocessing, and the FPGA performs noise point suppression on the original image data, so that the preprocessed image data is generated.
In operation S103, the FPGA transmits the preprocessed image data to the image processing chip.
According to the embodiment of the invention, the FPGA can transmit the preprocessed image data to the image processing chip for further processing, so that the preprocessed image data can better meet the requirements of practical application.
In operation S104, the image processing chip processes the pre-processed image data to generate image data.
According to the embodiment of the invention, the image processing chip performs actual image processing calculation after receiving the pre-processed image data from the FPGA. The process has the characteristics of high speed, high parallelism, configurability and low power consumption.
According to the embodiment of the invention, the original image data generated by the image sensor is subjected to the cooperative processing of the FPGA and the image processing chip, namely, the original image data is transmitted to the FPGA after the original image data is collected by the image sensor, and the original image data is subjected to the preprocessing of the FPGA and the further processing of the image processing chip to generate the image data, so that the high-speed generation and processing of the image data are realized.
According to the embodiment of the invention, the image processing method may further include the image processing chip transmitting the image data to the FPGA; the FPGA transmits the image data to an image display device through the HDMI interface, and simultaneously transmits the image data to an image storage device through the optical fiber interface.
According to the embodiment of the invention, the image processing chip receives the pre-processed image data from the FPGA, performs image processing according to the algorithm instruction and the parameter pre-configured in the image processing chip, generates the image data, and then transmits the image data to the FPGA, and the FPGA forwards the received image data.
According to an embodiment of the present invention, the FPGA forwarding the received image data may include forwarding the image data to an image display device and forwarding the received image data to an image storage device. Due to the fact that formats and rules of data transmission between different devices are different, smooth transmission of image data between different devices can be guaranteed by adopting the FPGA to forward the image data.
According to the embodiment of the invention, the FPGA forwards the received image data to the image display device and the FPGA forwards the image data to the image storage device simultaneously, so that the real-time display and storage of the image data are realized.
According to the embodiment of the invention, the image processing method further comprises the step that the FPGA configures the algorithm instruction and the parameter operated by the image processing chip. The configuration mode can comprise manual configuration and automatic configuration.
According to the embodiment of the invention, the algorithm instructions and parameters can be manually configured for the image processing chip through the FPGA debugging interface by manual configuration.
According to other embodiments of the invention, automatic configuration can be realized by fixing the algorithm instruction and the parameters into the nonvolatile memory of the FPGA for a user, reading the algorithm instruction and the parameters from the nonvolatile memory by the FPGA after the power is turned on, and transmitting the algorithm instruction and the parameters to the image processing chip, so that the algorithm instruction and the parameters for automatic configuration and operation of the image processing chip are realized.
According to the embodiment of the invention, the algorithm instructions and parameters operated by the image processing chip are configured through the FPGA. The configuration information is stored in a Static Random-Access Memory (SRAM) inside the image processing chip. The algorithm instructions and parameters operated by the image processing chip are configured through the FPGA, so that the algorithm instructions and parameters can be flexibly configured for the image processing chip aiming at an actual scene, and different application requirements can be met.
According to the embodiment of the invention, the image enhancement algorithm can be configured for the image processing chip through the FPGA. For example, when the algorithm configured in the image processing chip is an image enhancement algorithm, the algorithm processing result is an image with the same resolution as the original image data. And the FPGA transmits the image data processed by the image processing chip into the image storage equipment through the optical fiber interface. Meanwhile, the FPGA transmits the image with the image quality enhanced by the image processing chip to the image display equipment through the HDMI interface.
But not limited to this, can also dispose target detection, discernment, pursuit class algorithm to the image processing chip through FPGA. For example, when the algorithm configured in the image processing chip is an object detection, identification, and tracking algorithm, a series of data tags may be output after the processing of the image processing chip, and the FPGA transmits the tag information and the image information output by the image processing chip to the image storage device through the gigabit optical fiber interface. Meanwhile, the FPGA firstly marks original image data by using a data tag, and then inputs the marked original image data into the image display equipment through the HDMI interface
According to the embodiment of the invention, before the FPGA transmits the preprocessed image data to the image processing chip, the FPGA generates the preprocessed image data, and an internal memory of the image processing chip is idle; before the image processing chip transmits the image data to the FPGA, the image processing chip generates the image data, and a receiving end memory of the FPGA is idle.
According to an embodiment of the present invention, the data transmission between the image processing chip and the FPGA may include the FPGA transmitting the pre-processed image data to the image processing chip, and the image processing chip writing back the processed image data to the FPGA.
According to the embodiment of the invention, when the FPGA generates the preprocessed image data and the internal memory of the image processing chip is idle, the FPGA and the image processing chip successfully handshake, and the FPGA transmits the preprocessed image data to the image processing chip through the wiring of a Printed Circuit Board (PCB).
According to the embodiment of the invention, when the image processing chip finishes algorithm processing and prepares a processing result and the storage of the FPGA receiving end is idle, the image processing chip successfully handshakes with the FPGA, and the image processing chip transmits image data to the FPGA through PCB routing.
According to the embodiment of the invention, the image processing chip and the FPGA carry out data transmission under the condition of successful mutual handshake, thereby avoiding image data loss caused by unexpected conditions to the maximum extent.
According to the embodiment of the invention, the image processing method provided by the invention realizes high-speed and low-power-consumption real-time image processing through the cooperative work of the image processing chip and the FPGA.
Referring to fig. 2, 3 and 4, as another aspect of the present invention, there is also provided a high-speed smart camera applying the image processing method, including an image sensor 12, an FPGA9 and an image processing chip 8.
According to the embodiment of the present invention, the image sensor 12 is configured to convert the collected optical signal into raw image data and transmit the raw image data to the FPGA 9;
the FPGA9 is used for preprocessing the original image data to generate preprocessed image data; and transmits the preprocessed image data to the image processing chip 8;
and the image processing chip 8 is used for processing the preprocessed image data to generate image data.
According to the embodiment of the invention, the image sensor can be prepared by adopting a CMOS (Complementary Metal Oxide Semiconductor) process, a parallel digital-analog mixed signal processing circuit, 4T-APS pixels and improved process conditions.
According to the embodiment of the invention, under the condition of full image resolution of 816 × 600, the working frame rate of the image sensor can reach 1000 fps. The original image data generated by the image sensor is output in parallel by 8 paths, 8 pixel data can be output in one clock cycle, the bit width of each pixel is 12 bits, and the clock frequency is 80 Mhz.
According to the embodiment of the invention, the image sensor can realize high-speed image acquisition and high-speed image data output, and has the characteristics of low power consumption, self calibration and the like.
According to an embodiment of the present invention, the high-speed smart camera may further include an image sensing daughter board 4 and an image processing mother board 3.
The image sensing daughter board 4 comprises a daughter board body 13 and a daughter board plug connector 11; the image sensor 12 and the daughter board plug connector 11 are arranged on the daughter board body 13;
the image processing motherboard 3, the image processing motherboard 3 includes the motherboard body 10 and motherboard plug 7; the image processing chip 8, the FPGA9 and the motherboard plug-in connector 7 are arranged on the motherboard body 10;
the daughter board connector 11 is plugged to the motherboard connector 7.
According to the embodiment of the invention, the image sensing daughter board 4 can be vertically plugged onto the motherboard plug-in connector 7 of the image processing motherboard 3 through the daughter board plug-in connector 11, so as to reduce the space occupied by the whole image processing system.
Furthermore, because the image sensing daughter board 4 is connected with the image processing motherboard 3 through the matching of the daughter board connector 11 and the motherboard connector 7, the image sensing daughter board 4 can be replaced according to the actual application scene to adapt to the requirement of the actual application scene, thereby realizing the optimal imaging effect.
According to the embodiment of the invention, the image processing motherboard 3 can be a printed circuit board which is integrally formed and comprises a motherboard body 10, a functional module and a motherboard connector 7 matched with the image sensing daughter board 4. According to an embodiment of the present invention, the motherboard body 10 may be a rigid substrate.
According to an embodiment of the present invention, referring to fig. 3, the functional modules of the image processing motherboard 3 may include three parts, a power management module, an input/output port, and an image processing module.
The power management module may be configured to filter the input power and convert the filtered input power into power for use by the image processing motherboard 3 and other modules and the image sensor daughter board 4. The image processing motherboard 3 can be accessed with 5V power supply from outside, and 3.3V, 2.5V and 1.8V power supply can be obtained through the power conversion chip.
The input/output port can be used for outputting a power supply control signal of the image sensing sub-board, receiving an imaging result of the image sensing sub-board, outputting the imaging result of the image sensing sub-board and outputting a processing result of the image processing chip. And the system can also be used for communication and data transmission between a high-speed intelligent camera and an upper computer, other cameras, image storage equipment and the image sensing daughter board 4. The input/output ports may include JTAG (not shown), gigabit fiber interface 6, HDMI interface 5, and motherboard connector 7, among other interfaces. The JTAG interface may be used to communicate configuration information of the FPGA9 and to monitor the operating status of the FPGA 9. The gigabit optical fiber interface 6 can be used for connecting the FPGA9 with an image storage device and transmitting raw image data of the image sensor 12 and processing results of the image processing chip 8. The HDMI interface 5 can be used to transmit image information that is forwarded by the FPGA9 for display. The motherboard connector 7 can be used for connecting with the daughter board connector 11 and carrying out signal transmission, and the transmitted signals comprise three types of power supply, control and data.
According to the preferred embodiment of the present invention, the gigabit optical fiber interface 6 can adopt the gigabit optical fiber interface 6 supporting the 10G-BASER communication protocol; the data transmission rate of the gigabit optical fiber interface 6 adopting the 10G-BASER communication protocol can reach 10Gbps, so that high-speed storage and real-time result output of image data can be realized.
The image processing module is used for processing the original image data generated by the image sensor sub-board 4, including generating an HDMI signal for display, and performing algorithm processing such as filtering, histogram statistics or convolution neural network on the image to realize high-speed target detection or tracking.
The image processing module comprises an image processing chip 8 and an FPGA 9. The image processing chip 8 can be used for actual image processing calculation, and has the characteristics of high speed, high parallelism, configurability and low power consumption. The algorithm run by the image processing chip 8 may be configured by the FPGA 9. The configuration information is stored in the SRAM inside the image processing chip 8, and can be flexibly configured for an actual scene to meet different application requirements. In addition, through the cooperation of the image processing chip 8 and the FPGA9, the image processing module can achieve the following two technical effects, firstly, the image data generated by the image sensor 12 is encoded, so that the real-time display output can be realized; second, the imaging result of the image sensor 12 is processed in real time, so that high-speed target detection or tracking can be performed.
The FPGA9 may be used to pre-process and forward image data generated by the image sensor 12. Image data preprocessing refers to processing performed on raw image data generated by the image sensor 12, such as image brightness adjustment, image dead pixel restoration, image noise suppression, and the like, and can be selected as needed. The original image can be enhanced through image data preprocessing, for example, the contrast, the brightness and the like of the original image are enhanced, the signal to noise ratio can be improved, and the display quality and the accuracy of a subsequent intelligent algorithm are improved. The image data forwarding includes forwarding image data from the image sensor 12 to the HDMI interface 5, forwarding image data from the image sensor 12 to the image processing chip 8, and forwarding the image processing result from the image processing chip 8 to the gigabit optical fiber interface 6. The reason why the FPGA9 is used for forwarding is that the formats and rules of the output data of different devices are different, so the FPGA9 needs to be used for synchronization to ensure the communication. It should be noted that, in order to ensure the display quality of the image data and the effect of the image processing algorithm, the image forwarded from the FPGA9 to the image processing chip 8 and the HDMI interface 5 is an image after being preprocessed.
According to an embodiment of the present invention, referring to fig. 4, the image sensor daughter board 4 may be an integrally molded printed circuit board, wherein the image sensor daughter board 4 is integrally molded by the image sensor 12, the daughter board body 13, and the daughter board connector 11.
According to the embodiment of the present invention, the daughter board connector 11 of the image sensor daughter board 4 is connected to the motherboard connector 7 of the image processing motherboard 3. The power supply and control commands of the image sensor are provided by the image processing motherboard through the inter-board connector. Raw image data generated by the image sensor is also transmitted to the image processing motherboard through the inter-board connector.
The lines of the image sensor daughter board 4 connected to the daughter board plug 11 may be classified into three types, a power line, a control line, and a data line. The power supply line is the power supply line of the image sensor 12, and the power supply is generated by a power conversion chip in the image processing motherboard 3. In order to ensure the quality of the power supply of the image sensor 12, a filter capacitor network is designed and used on the image sensor daughter board 4, so as to ensure stable power supply. The control line is connected with the FPGA9 of the image processing motherboard 3 through the daughter board plug connector 11, thereby realizing the configuration of state information such as the shutter mode, the output frame rate, the image resolution and the like of the image sensor 12. The data line can also be connected with the FPGA9 of the image processing motherboard 3, and the FPGA9 divides the original image data generated by the image sensor 12 into two paths and forwards the two paths in real time. One path is forwarded to the video signal output port to realize the real-time display of the signals of the image sensor 12, and the other path is forwarded to the image processing chip 8 to realize the real-time processing of the high-speed image information.
As shown in fig. 2, the high-speed smart camera further includes an optical lens 1 and a housing 2.
According to the preferred embodiment of the present invention, the optical lens 1 can be a focus-adjustable lens, and the focal length can be adjusted according to the environment and application requirements, so as to achieve the best imaging effect.
According to an embodiment of the present invention, the housing 2 includes a front panel, a middle cylinder, and a rear panel; the front panel and the rear panel are connected with the middle cylinder through screws. The space formed by the front panel, the middle barrel and the rear panel is an accommodating space, and the image sensing daughter board 4 and the image processing mother board 3 are arranged in the accommodating space. In the invention, each component in the camera can be protected by the shell 2, and the camera is dustproof and rainproof.
According to the embodiment of the invention, the front panel is provided with a lens opening for the optical lens 1 to pass through, and the optical lens 1 can pass through the lens opening to be connected to the image sensor sub-board 4.
According to the embodiment of the invention, the middle cylinder is also provided with a fiber opening for the ten-gigabit fiber interface 6 to pass through.
According to the embodiment of the invention, heat dissipation hole arrays (not shown) are symmetrically arranged right above and below the middle cylinder, and heat dissipation strip arrays (not shown) are respectively arranged at symmetrical positions on two sides of the middle cylinder. The shell 2 in the invention realizes good ventilation and heat dissipation by arranging the heat dissipation hole array, and prevents the problem of component loss caused by overhigh temperature of the high-speed intelligent camera.
According to an alternative embodiment of the present invention, a fixing screw hole for fixing a high-speed smart camera is provided under the middle cylinder of the housing 2.
In conclusion, the invention provides a high-speed, low-power-consumption and miniaturized high-speed intelligent camera through the cooperative work of the high-speed image sensor, the artificial intelligent image processing chip and the FPGA, and lays a technical foundation for the application and popularization of the high-speed intelligent camera.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An image processing method applied to a high-speed intelligent camera includes:
the image sensor converts the collected optical signals into original image data and transmits the original image data to the FPGA;
the FPGA preprocesses the original image data to generate preprocessed image data;
the FPGA transmits the preprocessed image data to an image processing chip; and
and the image processing chip processes the preprocessed image data to generate image data.
2. The image processing method according to claim 1, further comprising:
the image processing chip transmits the image data to the FPGA;
the FPGA transmits the image data to an image display device through an HDMI interface, and simultaneously transmits the image data to an image storage device through an optical fiber interface.
3. The image processing method of claim 2, wherein the FPGA has generated the pre-processed image data and an internal memory of the image processing chip is free before the FPGA transmits the pre-processed image data to the image processing chip;
before the image processing chip transmits the image data to the FPGA, the image processing chip generates the image data, and a receiving end memory of the FPGA is idle.
4. The image processing method according to claim 1, further comprising:
the FPGA configures algorithm instructions and parameters for operation for the image processing chip through a debugging interface; or
The FPGA reads the algorithm instruction and the parameters from the nonvolatile memory and transmits the algorithm instruction and the parameters to the image processing chip, so that the algorithm instruction and the parameters for the automatic configuration and operation of the image processing chip are realized.
5. The image processing method of claim 1, wherein the FPGA pre-processing the raw image data comprises:
and the FPGA carries out one or more of image brightness adjustment, image dead pixel restoration and image noise suppression on the original image data.
6. The image processing method according to claim 2,
the image data includes image information and label information;
the FPGA transmits the image data to an image display device through an HDMI interface, and simultaneously the FPGA transmits the image data to an image storage device through an optical fiber interface, the FPGA comprises:
the FPGA labels the image information by using the label information to generate labeled data; the FPGA transmits the marked data to an image display device through an HDMI (high-definition multimedia interface);
and meanwhile, the FPGA transmits the image information and the label information to an image storage device through an optical fiber interface.
7. The image processing method according to claim 1, further comprising:
the FPGA receives the original image data transmitted by the image sensor and caches the received original image data at the same time; and
after buffering the complete raw image data, preprocessing the complete raw image data.
8. A high-speed smart camera, comprising:
the image sensor is used for converting the collected optical signals into original image data and transmitting the original image data to the FPGA;
the FPGA is used for preprocessing the original image data to generate preprocessed image data; and transmitting the preprocessed image data to an image processing chip;
and the image processing chip is used for processing the preprocessed image data to generate image data.
9. A high speed smart camera as recited in claim 8, further comprising:
the image sensing daughter board comprises a daughter board body and a daughter board plug connector; the image sensor and the daughter board plug connector are arranged on the daughter board body;
the image processing motherboard comprises a motherboard body and a motherboard plug connector; the image processing chip, the FPGA and the motherboard plug connector are arranged on the motherboard body;
the daughter board plug connector is connected with the motherboard plug connector in a plugging mode.
10. A high speed smart camera as recited in claim 9, wherein the high speed smart camera further comprises an HDMI interface and an optical fiber interface; wherein the content of the first and second substances,
the HDMI is arranged on the motherboard body and is used for realizing the connection between the FPGA and an image display device;
the optical fiber interface is arranged on the motherboard body and used for realizing the connection between the FPGA and an image storage device.
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| CN113630586A (en) * | 2021-07-28 | 2021-11-09 | 英特灵达信息技术(深圳)有限公司 | Single-light-source full-color camera |
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