CN212278335U - Video processor - Google Patents

Abstract

The embodiment of the utility model discloses video processor, include: a back plate; an input card connected to the backplane; an output card connected to the backplane; an image processing card connected to the backplane; a master control card connected to the backplane, the input card, the output card, and the image processing card; wherein the input card includes: a video input interface; the first programmable logic device is connected with the video input interface; the first microcontroller is connected with the first programmable logic device; the video artificial intelligence processing circuit is connected with the first programmable logic device; and the first connector is connected with the first programmable logic device, and the input card is connected with the backboard through the first connector. The embodiment of the utility model provides a can promote video display effect, promote user experience degree.

Description

Video processor

Technical Field

The utility model relates to a video display field especially relates to a video processor.

Background

With the rapid development of the video processing industry, people have higher and higher requirements on video display effects. Generally, the image quality of the input video source is good. However, in some cases, there are problems in the video data to be output in the video processor such as image noise, video jitter, inappropriate brightness, contrast, and the like. However, for the problem of the video data to be output, the current video processor cannot adaptively process the video data, and cannot meet the demand of people for higher and higher display effect of the video image.

SUMMERY OF THE UTILITY MODEL

For solving at least partial problem among the above-mentioned problem, the embodiment of the utility model provides a video processor to the video display effect of output has been promoted, user experience degree has been promoted.

In one aspect, an embodiment of the present invention provides a video processor, including: a back plate; an input card connected to the backplane; an output card connected to the backplane; an image processing card connected to the backplane; a master control card connected to the backplane, the input card, the output card, and the image processing card; wherein the output card includes: a video output interface; the first programmable logic device is connected with the video output interface; the first microcontroller is connected with the first programmable logic device; the video artificial intelligence processing circuit is connected with the first programmable logic device; and the first connector is connected with the first programmable logic device, and the output card is connected with the backboard through the first connector.

According to the technical scheme, the video artificial intelligence processing circuit is arranged on the output card, artificial intelligence self-adaptive processing can be carried out on the video data to be output, the video display effect is improved, and the user experience degree and the product competitiveness are improved.

In an embodiment of the present invention, the back plate includes: a matrix switching circuit; an input card connector connected to the matrix switching circuit; the output card connector is connected with the matrix switching circuit; a graphic processing card connector connected to the matrix switching circuit; and a master control card connector for connecting the matrix switching circuit, the input card connector, the output card connector and the image processing card connector; wherein the output card connector is connected to the first connector of the output card.

In an embodiment of the present invention, the matrix switch circuit includes a matrix switch chip, the matrix switch chip connects the input card connector, the output card connector, the image processing card connector and the master control card connector.

In an embodiment of the present invention, the input card connector, the output card connector, the image processing card connector and the main control card connector are plug connectors, respectively.

In an embodiment of the present invention, the input card is inserted into the input card connector of the back plate, the main control card is inserted into the main control card connector of the back plate, the image processing card is inserted into the image processing card connector of the back plate

In an embodiment of the present invention, the video artificial intelligence processing circuit includes an AI processing chip, and the AI processing chip is connected to the first programmable logic device; the video artificial intelligence processing circuit further comprises a database memory, and the database memory is connected with the AI processing chip; the video artificial intelligence processing circuit further comprises a sensing circuit, and the sensing circuit is connected with the AI chip.

In an embodiment of the present invention, the input card includes a video input interface, a second programmable logic device, a second microprocessor and a second connector, the second programmable logic device is connected to the video output interface and the second microcontroller, the second connector is connected to the second programmable logic device, and the input card is connected to the back board through the second connector.

In an embodiment of the present invention, the image processing card includes a third programmable logic device and a third microprocessor, and a third connector, the third programmable logic device connects the third microcontroller and the third connector, and the image processing card passes through the third connector to connect to the backplane.

In an embodiment of the present invention, the master control card includes an embedded processor and a fourth connector, the embedded processor is connected to the fourth connector, and the master control card is connected to the backplane through the fourth connector.

In an embodiment of the present invention, the video processor further includes a cascade card, the cascade card includes a fourth programmable logic device, a fourth microprocessor, a fifth connector, a first data interface and a second data interface, the fourth microprocessor the fifth connector the first data interface and the second data interface are respectively connected to the fourth programmable logic device, the cascade card passes through the sixth connector is connected to the backplane.

The technical scheme can have one or more of the following advantages or beneficial effects: through set up video artificial intelligence processing circuit in the output card, can treat the video data of output and carry out artificial intelligence self-adaptation and handle, promote video display effect, promoted user experience degree and product competitiveness. In addition, the input card, the output card, the image processing card and the main control card are all connected by adopting a connector, so that a user can conveniently and quickly connect and disassemble, and the working efficiency is improved. In addition, the expansion capacity of the video processor can be improved by adding the cascade cards.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a video processor according to an embodiment of the present invention.

Fig. 2 shows a schematic structural diagram of the back plate in fig. 1.

Fig. 3 shows a schematic structure of the input card in fig. 1.

Fig. 4 shows a schematic diagram of the structure of the image processing card in fig. 1.

Fig. 5 illustrates a schematic diagram of the structure of the output card of fig. 1.

Fig. 6 is a schematic diagram of the video artificial intelligence processing circuit in fig. 5.

Fig. 7 shows a schematic structural diagram of the master control card in fig. 1.

Fig. 8 is a schematic structural diagram of another video processor according to an embodiment of the present invention.

Fig. 9 shows a schematic diagram of the structure of the cascade card in fig. 8.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

As shown in fig. 1, an embodiment of the present invention provides a video processor 800. The video processor 800 includes, for example: the backplane 100, the input card 200, the output card 300, the image processing card 400 and the master control card 500. The input card 200, the output card 300, the image processing card 400 and the master control card 500 are respectively connected to the backplane 100.

Specifically, the back plate 100 is a PCB circuit board. As shown in fig. 2, the backplane 100 includes, for example, a matrix switch circuit 11, an input card connector 13, an output card connector 15, an image processing card connector 19, and a main control card connector 17. The matrix switching circuit 11 is connected between the input card connector 13 and the output card connector 15; the graphic processing card connector 19 is connected with the matrix switching circuit 11; the main control card connector connects the matrix switching circuit 11, the input card connector 13, the output card connector 15, and the image processing card connector 19. In addition, the input card connector 13 can be connected to at least one input card; the output card connector 15 is connectable to at least one output card.

As described above, the matrix Switch circuit 11 includes, for example, a matrix Switch chip such as a CrossPoint Switch chip. The matrix switching chip is connected to the input card connector 13, the output card connector 15, the image processing card connector 19 and the main control card connector 17, and switches the output data of the corresponding input card to the corresponding output card for output according to a control instruction issued by the main control card plugged into the main control card connector 17. In order to improve the utilization rate of the matrix switch chip of the backplane, reduce the channel requirement of the switch chip, and improve the switching capability, it is preferable that the matrix switch circuit 11 connects the input card connector 13 and the output card connector 15, and the image processing card connector 19 via a serial bus such as a high-speed serial bus like a SERDES bus, so that the input card, the output card, and the image processing card, etc. can perform video image data transmission with the matrix switch circuit 11 via the high-speed serial bus like the SERDES, respectively.

The input card connector 13, the output card connector 15, the image processing card connector 19, and the main control card connector 17 are plug connectors, such as a pin header connector, a box header connector, and a high-contact plug. Therefore, the input card, the output card, the image processing card, the main control card and other board cards can be conveniently and quickly inserted into corresponding connectors on the back board, and the connection efficiency is improved.

As shown in fig. 1, the input card 200 is inserted into the input card connector 13 of the backplane 100, and is mainly used for preprocessing an input video source. The input card 200 is connected to the interconnection board 110. Specifically, as shown in fig. 3, the input card 200 is provided thereon with, for example, a video input interface 210, a programmable logic device 220, a microcontroller 230, and a connector 240. The programmable logic device 220 is connected to the video input interface 210, the connector 240 and the microcontroller 230. The video input interface 210 is used for receiving an externally input video source signal. The video input interface 210 may be, for example, a standard video interface, such as an HDMI interface, a DVI interface, a DP interface or an SDI interface, and the video input interface 210 may also be an optical fiber interface or other interfaces for transmitting video or image data, which is not limited to this. Further, the number of the video input interfaces 210 may be multiple, and the multiple video input interfaces 210 are respectively selected from a part or all of an HDMI interface, a DVI interface, a DP interface, and an SDI interface, for example, the video input interfaces 210 may include two HDMI interfaces and two DP interfaces. Therefore, a user can set a plurality of video input interfaces 210 on the video preprocessing card 150 as required to further meet the requirements of the user for more diversified video input interfaces. The Programmable logic device 220 may be, for example, an FPGA (Field Programmable Gate Array), which is of a type such as XC7K160TFFG676ABX and XC7K325TFFG900, and is mainly used for performing processing such as decoding, video source detection, spatial conversion, de-interlacing, and picture quality adjustment, e.g., brightness adjustment, on an input video source under the control of the microcontroller 230. The microcontroller 230, for example, an MCU, may have a model number of NXP LPC433DFET100, for example, which is used to load the programmable logic device 220, communicate with the outside, and the like. Further, the input card 200 may also include a volatile memory 250, such as DDR3, for example, model IS43T216640B-107, coupled to the programmable logic device 220 for data caching and the like. Of course, the video decoding here can also be done with a professional decoding chip, which can be connected between the video input interface 210 and the programmable logic device 220, for example.

As shown in fig. 1, the image processing card 400 is connected to the image processing card connector 19 of the backplane 100, and is mainly used for processing such as scaling, image quality enhancement, and layer aliasing of video data and image data received from the input card 200. Specifically, as shown in fig. 5, the image processing card 400 is provided with a programmable logic device 420, a microcontroller 430, and a connector 410. The connector 410 is connected to the programmable logic device 420, and the microcontroller 430 is connected to the programmable logic device 420. The connector 410 is, for example, a socket connector such as a high-profile plug-in, a pin header, or the like. The programmable logic device 420 may be, for example, an FPGA, which may have a model number of XC7K160TFFG676ABX and XC7K325TFFG900, and is mainly configured to perform processing such as window scaling, layer overlaying, window image quality enhancement, and the like on video data or image data received through the connector 410 under the control of the microcontroller 430, and output the processed image data through the connector 410. A microcontroller 430, such as an MCU, may be of a type such as NXP LPC433DFET100, for loading the programmable logic device 420, and communicating externally, etc. Further, the image processing card 400 may also include a volatile memory 440, such as DDR3, for example, model IS43T216640B-107, coupled to the programmable logic device 420 for data caching and the like.

As shown in fig. 1, the output card 300 is connected to the output card connector 15 of the backplane 100, and is mainly used for processing image data to be output, such as output reflection, interface feathering, interface adaptation, and encoding, and finally outputting to a back-end device, such as an LED display. Specifically, as shown in fig. 5, the output card 300 includes, for example, a connector 310, a programmable logic 320, a microcontroller 330, a video artificial intelligence processing circuit 360, and a video output interface 340. Programmable logic 320 connects connector 310, microcontroller 330, video artificial intelligence processing circuit 360, and video output interface 340. The video output interface 340 is, for example, a standard video interface, such as an HDMI interface, a DVI interface, a DP interface, or an SDI interface. Further, the number of the video output interfaces 340 may be plural, and the plurality of video output interfaces 340 may be selected from a part or all of HDMI interface, DVI interface, DP interface, SDI interface, and in addition, the video output interfaces 340 may also be optical fiber interface or other interfaces for transmitting video or image data, which is not limited by the present invention. Therefore, the diversified video output interface requirements of users can be further met. The connector 310 may be, for example, a socket connector such as a pin header connector, a high-profile card, etc., and the output card 300 is plugged to the output card connector 15 of the backplane board 100 through the connector 310. The programmable logic device 320 may be, for example, an FPGA, which has a model number of XC7K160TFFG676ABX and XC7K325TFFG900, and is mainly used for performing processing such as output review, interface feathering, interface adaptation, encoding, and the like on video data or image data received through the connector 310 under the control of the microcontroller 330, and outputting the processed image data through the video output interface 340. The microcontroller 330, for example, an MCU, may be of a model such as NXP LPC433DFET100, which is used to load the programmable logic device 320, communicate with the outside, and the like. The video artificial intelligence processing circuit 360 is mainly used for performing adaptive intelligent processing on the video data and the image data received from the image processing card 400 based on an artificial intelligence technology, for example, identifying and judging whether the video data has a problem, and repairing and denoising the video data, super-resolution, video debouncing the video data when the video data has the problem, and the like to improve the display effect of the video. Specifically, as shown in fig. 6, the video Artificial Intelligence processing circuit 360 includes an AI (Artificial Intelligence) processing chip 361. The AI processing chip 361 is connected to the programmable logic device 320. The AI processing chip 361 mainly completes the processing of video data identification and judgment, video effect adaptive enhancement, deep learning, and the like. The AI processor chip 361 may be, for example, a haisi Hi3559A/C series processor, etc., but may be other similar AI processors, and is not limited thereto. The AI processing chip 361 performs display effect adaptive enhancement processing on the video data transmitted by the programmable logic device 320, such as video data sampling, problem identification and judgment, performs repair denoising, super-resolution, video debouncing, contrast adjustment and the like when a problem is found, and returns the processed video data to the programmable logic device 320 for further processing by the programmable logic device 320 and outputting the processed video data through the video output interface 340; when no problem is found, no processing is performed. It should be noted here that the AI processing chip 361 performs adaptive processing of the display effect on the received video data, and the processing method and technique thereof may also adopt a mature artificial intelligence video processing technique in the prior art, which is not described herein again. As shown in fig. 6, the video artificial intelligence processing circuitry 360 may also include a database memory 363. The database memory 363 is connected to the AI processing chip 361. The database memory 363 is, for example, a nonvolatile memory, such as an EMMC (Embedded multimedia Card), which can be used for storing a database, such as video noise sample data, luminance sample data, deep learning data, and the like, required by the AI processing chip 361 to perform adaptive processing on the pre-processed video, and is used for comparing and determining sampling data of the video data. Further, as shown in fig. 5, the video artificial intelligence processing circuit 360 may further include a sensing circuit 365. The sensing circuit 365 includes, for example, a brightness sensor, a photosensitive sensor and other sensing elements, and is configured to sense brightness, contrast and other conditions of an external environment, and transmit a sensing result signal to the AI processing chip 361, so that the AI processing chip 361 adaptively adjusts the received video data according to the brightness sample data stored in the database memory 363, so that the adjusted video data is adapted to the external environment where the video processor 800 is located after being played on the display screen, so as to improve a display effect and user experience. For example, in a cinema, the sensing circuit 365 senses that the internal brightness is low and transmits a sensing signal to the AI processing chip 361, and the AI processing chip 361 adjusts the brightness parameter of the video data according to the brightness sample data and the sensing signal stored in the database memory 363, so that the brightness of the video data display matches the brightness in the cinema, and the viewer can watch the movie comfortably. Further, the output card 300 may also include a volatile memory 350, such as DDR3, for example, model IS43T216640B-107, coupled to the programmable logic device 320 for data caching, and the like.

As shown in fig. 1, the master control card 500 is connected to the master control card connector 17 of the backplane 100, and is mainly used for providing control signals to the input card 200, the output card 300, the image processing card 400, and the like, and for realizing communication and human-computer interaction with the outside. Master control card 500 may, for example, include a connector 510 and an embedded processor 520. The connector 510 is connected to the embedded processor 520. The embedded processor 520 may be, for example, an embedded processor based on an ARM core, and is mainly used for controlling the implementation of human-computer interaction functions, such as switching control of layers, input source monitoring, and the like. Further, the master control card 500 also includes, for example, a communication interface 530. The communication interface 530 may be, for example, a USB interface, an RS232 interface, an ethernet interface such as RJ45, etc. for implementing human-computer interaction functions, such as receiving input information of a user, etc., and transmitting the input information to the embedded processor 520 for the embedded processor 520 to convert into corresponding control signals for controlling the cards.

In addition, as shown in fig. 8, video processor 800 may also include a cascading card 700. The backplane 100 is further provided with a cascade card connector 16, and the cascade card connector 16 connects the matrix switch circuit 11 and the main control card connector 17. The cascading card 700 is coupled to the cascading card connector 16. The cascade card 700 can connect the video processor 800 to another video processor, such as another video processor, can receive video data from another video processor, and can also output video data on its own video processor to another video processor, which can share video sources of the two video processors, improving the expansion capability of the video processors. Specifically, as shown in fig. 9, the cascading card may include, for example, a data interface 710, a data interface 720, a programmable logic device 730, a microcontroller 740, and a connector 750. Programmable logic device 730 is connected to data interface 710, data interface 720, microcontroller 740, and connector 750. Data interfaces 710, 720 may be, for example, cxp (coaxpress) interfaces. The CXP interface is an asymmetric high-speed point-to-point serial communication digital interface standard and has the characteristics of high data transmission quality, long transmission distance and the like. Of course, the data interfaces 710 and 720 may also be other types of data transmission interfaces, and the present invention is not limited thereto. One of the data interfaces 710 and 720 can obtain the video data of the video processor from the other video processors connected with it, and transmit the video data to the programmable logic device 730 and the matrix switch chip of the matrix switch circuit 11 through the connector 750; the other of the data interface 710 and the data interface 720 may output the video data transmitted by the matrix switch circuit 11, the connector 750, and the programmable logic device 730 to the other video processor connected thereto for use by the other video processor. The programmable logic device 730, which may be an FPGA, may be, for example, of a type XC7K160TFFG676ABX, XC7K325TFFG900, and is mainly used to process received video data or image data under the control of the microcontroller 740, and output the processed image data through the connector 750 or the data interface 710, 720. A microcontroller 740, for example an MCU, the model of which may be, for example, NXP LPC433DFET100, is used to load the programmable logic device 730, and to communicate with the outside, etc.

In addition, in other embodiments of the present invention, the video processor 800 further includes a power supply unit (not shown), and the back plate 100 of the video processor 800 is provided with power supply connectors (not shown) connected to the matrix switch circuit 11, the input card connector 13, the output card connector 15, the image processing card connector 19, the video artificial intelligence processing circuit connector 18, and the main control card connector 17. The power supply unit is connected with the power supply connector to supply power to the matrix switching circuit 11, the input card 200, the output card 300, the image processing card 400, the video artificial intelligence processing circuit 600 and the master control card 500. The power supply unit here can adopt a power supply module mature in the prior art, and is not described here again.

To sum up, the embodiment of the utility model provides a through set up video artificial intelligence processing circuit on the output card, treat the video data of output and carry out artificial intelligence self-adaptation processing, promoted video display effect, promoted user experience degree and product competitiveness. In addition, input card, output card, image processing card, master control card, video artificial intelligence processing circuit all adopt the connector to connect for the user can connect with the dismouting convenient and fast ground, has promoted work efficiency. Furthermore, configuring the matrix switch circuit to interface with high speed serial interfaces such as serial interfaces, e.g., serializer/deserializer interfaces, between the output card and the input card may reduce the requirements of the output channel and thereby increase the data transmission rate. In addition, the expansion capacity of the video processor can be improved by adding the cascade cards.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (10)

1. A video processor, comprising:

a back plate;

an input card connected to the backplane;

an output card connected to the backplane;

an image processing card connected to the backplane;

a master control card connected to the backplane, the input card, the output card, and the image processing card;

wherein the output card includes:

a video output interface;

the first programmable logic device is connected with the video output interface;

the first microcontroller is connected with the first programmable logic device;

the video artificial intelligence processing circuit is connected with the first programmable logic device; and

and the first connector is connected with the first programmable logic device, and the output card is connected with the backboard through the first connector.

2. The video processor of claim 1, wherein the backplane comprises:

a matrix switching circuit;

an input card connector connected to the matrix switching circuit;

the output card connector is connected with the matrix switching circuit;

a graphic processing card connector connected to the matrix switching circuit; and

a main control card connector for connecting the matrix switching circuit, the input card connector, the output card connector and the image processing card connector;

wherein the output card connector is connected to the first connector of the output card.

3. The video processor of claim 2, wherein the matrix switch circuit comprises a matrix switch chip, the matrix switch chip connecting the input card connector, the output card connector, the image processing card connector, and the master control card connector.

4. The video processor of claim 2, wherein the input card connector, the output card connector, the image processing card connector, and the main control card connector are jack connectors, respectively.

5. The video processor of claim 2, wherein the input card is inserted into the input card connector of the backplane, the main control card is inserted into the main control card connector of the backplane, and the image processing card is inserted into the image processing card connector of the backplane.

6. The video processor of claim 1, wherein the video artificial intelligence processing circuit comprises an AI processing chip, the AI processing chip being coupled to the first programmable logic device; the video artificial intelligence processing circuit further comprises a database memory, and the database memory is connected with the AI processing chip; the video artificial intelligence processing circuit further comprises a sensing circuit, and the sensing circuit is connected with the AI chip.

7. The video processor of claim 1, wherein the input card comprises a video input interface, a second programmable logic device and a second microcontroller, and a second connector, the second programmable logic device connects the video output interface and the second microcontroller, the second connector connects the second programmable logic device, and the input card connects to the backplane through the second connector.

8. The video processor of claim 1, wherein the image processing card comprises a third programmable logic device and a third microcontroller and a third connector, the third programmable logic device connecting the third microcontroller and the third connector, the image processing card being connected to the backplane through the third connector.

9. The video processor of claim 1, wherein the master control card comprises an embedded processor and a fourth connector, the embedded processor is connected to the fourth connector, and the master control card is connected to the backplane through the fourth connector.

10. The video processor of claim 1, further comprising a cascade card, the cascade card comprising a fourth programmable logic device, a fourth microcontroller, a fifth connector, a first data interface, and a second data interface, the fourth microcontroller, the fifth connector, the first data interface, and the second data interface respectively connected to the fourth programmable logic device, the cascade card connected to the backplane through the fifth connector.

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