CN211830923U

CN211830923U - Device capable of connecting two cameras

Info

Publication number: CN211830923U
Application number: CN202020647467.6U
Authority: CN
Inventors: 赵佳康
Original assignee: Beijing Ingenic Semiconductor Co Ltd
Current assignee: Beijing Ingenic Semiconductor Co Ltd
Priority date: 2020-04-26
Filing date: 2020-04-26
Publication date: 2020-10-30
Anticipated expiration: 2030-04-26

Abstract

The utility model discloses accessible single channel ISP module connects and acquires two data of taking photograph to reduce the hardware cost, and support two cameras for old equipment upgrading and provide a selection. Specifically, the utility model provides a device of two cameras of joinable, the device includes two cameras, a CPU, the device still additionally includes an FPGA, FPGA with two cameras are connected and are received the buffer memory the image data that two cameras were gathered, through single channel in the FPGA is connected and is transmitted image data to CPU with the inside ISP module of CPU. The two cameras are respectively connected to the two paths of the path 1 and the path 2 of the FPGA. The channel between the FPGA and the ISP is a single channel connected with an ISP module in the CPU through the FPGA.

Description

Device capable of connecting two cameras

Technical Field

The utility model relates to an image pickup field, in particular to device of two cameras of joinable.

Background

With the rapid development of the internet of things and artificial intelligence, various artificial intelligence algorithms and products are emerging, wherein the artificial intelligence algorithms and products include applications to graphic image acquisition and recognition, such as a face recognition payment function applied to a vending machine/an unmanned supermarket and a face recognition security check function applied to an airport/railway station. These applications all rely on artificial intelligence to analyze the acquired image data, increasing from initial single shot to later dual cameras (cameras) in order to improve recognition accuracy/precision.

The cameras need to be connected to the ISP, and usually, a single camera (as shown in fig. 1)/a double camera (as shown in fig. 2) needs to use a single channel/double channel corresponding to the single camera/double camera, so that double-shot data can be collected through two channels.

However, the prior art has the following disadvantages: a dual channel ISP is typically used to connect the bi-camera devices, but the more ISP channels the higher the hardware and chip cost that is required. In addition, as a multi-channel ISP module is integrated in a newly designed high-end chip due to rapid development of technology, a single-channel ISP is often integrated in some older chips, and if the chips integrating the multi-channel ISP are used for redesigning hardware for supporting double-shot, the supporting of the double-shot by old equipment becomes difficult.

Further, technical terms commonly used in the prior art are as follows:

ISP (image Signal processing) image Signal processor. A unit for connecting a front-end image sensor (Camera) and processing an output signal, so as to match image sensors of different manufacturers. The image processing special engine which is pipelined can process image signals at high speed. A special circuit for realizing Auto Exposure/Auto Focus/Auto White Balance evaluation is also carried out. Often, at present, an ISP module is already integrated in most embedded CPUs.

FPGA: a field programmable gate array; FPGA (field Programmable Gate array) is a product of further development on the basis of Programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The FPGA can be flexibly applied to various scenes due to the characteristic that the internal logic of the FPGA is programmable. Due to the programmable characteristic of the FPGA, the hardware interface provided by internal logic/external can be customized.

Channel: and a channel connecting the Camera and the ISP is called a channel for short.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems in the prior art, the utility model aims to provide a: the utility model discloses accessible single channel ISP module connects and acquires two data of taking photograph to reduce the hardware cost, and support two selections of taking photograph for old equipment upgrading and provide a selection.

Specifically, the utility model provides a device of two cameras of joinable, the device includes two cameras, a CPU, the device still additionally includes an FPGA, FPGA with two cameras are connected and are received the buffer memory the image data that two cameras were gathered, through single channel in the FPGA is connected and is transmitted image data to CPU with the inside ISP module of CPU.

The two cameras are respectively connected to the two paths of the path 1 and the path 2 of the FPGA.

The channel between the FPGA and the ISP is a single channel connected with an ISP module in the CPU through the FPGA.

The ISP module inside the CPU is a single-channel ISP module integrated in the CPU, and the interface of the CPU externally connected with the camera is only one hardware interface.

Thus, the present application has the advantages that: the utility model has simple structure, only needs to add a FPGA in the old device, is connected with the camera through the FPGA and receives and caches the data collected by the camera; the aim of connecting the double cameras and acquiring the image data of the double cameras can be achieved by connecting the single channel in the FPGA with the ISP module inside the CPU and transmitting the image data to the CPU, and normal transmission of the data can be guaranteed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a prior art single camera connection.

Fig. 2 is a schematic diagram of a prior art dual camera connection.

Fig. 3 is a schematic diagram of a single-channel connected dual camera according to an embodiment of the present invention.

Detailed Description

In order to clearly understand the technical contents and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

As shown in fig. 3, the CPU of the integrated single-channel ISP has only one hardware interface to the external Camera, so that it is unable to directly connect two cameras, but can pass through the utility model discloses the connection mode realizes the support to two cameras, and concrete implementation mode is as follows:

the utility model provides a device of joinable two cameras, the device includes two cameras, a CPU, the device still additionally includes an FPGA, FPGA with two camera connections and receiving buffer memory the image data that two cameras were gathered, through single channel in the FPGA is connected with the inside ISP module of CPU and is transmitted image data to CPU.

The FPGA further comprises a cache unit for caching the image data and a sorting unit for sorting the image data according to the sequence of the two cameras, the cache unit is connected with the sorting unit, the cache unit is connected with two paths for connecting the two cameras, and the sorting unit is connected with the ISP module. The sequencing in the sequencing unit is that the image data acquired by the two cameras are sequentially transmitted to the ISP module through the channel connected between the FPGA and the ISP module according to the sequence of the camera1 and the camera 2.

Image data to be sent in the FPGA is configured with image data format parameters in advance before data transmission of an ISP single channel so as to calculate data throughput per second, wherein the data throughput per second of final actual transmission is equal to the resolution of each camera multiplied by 2 multiplied by the number of frames multiplied by the number of bytes of a storage space occupied by each pixel of an image format, and the image data collected by the two cameras are spliced together in a front-back sequence for sending.

The utility model can be interpreted as follows:

1. the two cameras are respectively connected to the 1 and 2 channels of the FPGA which are specially used for connecting the two cameras;

2. the FPGA is responsible for receiving and caching image data acquired by Camera1 and Camera 2;

3. image data are sequentially sent to an ISP module of the CPU through 3 channels of the FPGA according to the sequence of Camera1 and Camera 2;

4. therefore, the CPU end can completely receive the double shot image data.

The role of the FPGA in this application is similar to that of a transfer station (receiving dual-camera data, sending the data to the CPU through a corresponding channel after internal sequencing).

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The device capable of being connected with the two cameras comprises two cameras and a CPU and is characterized by further comprising an FPGA, wherein the FPGA is connected with the two cameras and receives and caches image data collected by the two cameras, and the image data are connected with an ISP module inside the CPU through a single channel in the FPGA and transmitted to the CPU.

2. A device for connecting two cameras according to claim 1, wherein the two cameras are connected to two paths of 1 path and 2 path of the FPGA respectively.

3. The device capable of being connected with two cameras according to claim 1, wherein the FPGA further comprises a cache unit for caching image data and a sorting unit for sorting the image data according to the sequence of the two cameras, the cache unit is connected with the sorting unit, the cache unit is connected with two paths connecting the two cameras, and the sorting unit is connected with the ISP module.

4. A device capable of connecting two cameras according to claim 1, wherein the channel between the FPGA and the ISP is a single channel connected to the ISP module inside the CPU through the FPGA.

5. The device of claim 1, wherein the ISP module inside the CPU is a single channel ISP module integrated inside the CPU, and the interface of the CPU externally connected to the camera has only one hardware interface.