CN112287623B - Pretesting platform based on FPGA and V93000 test machine - Google Patents
Pretesting platform based on FPGA and V93000 test machine Download PDFInfo
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- CN112287623B CN112287623B CN202011195229.7A CN202011195229A CN112287623B CN 112287623 B CN112287623 B CN 112287623B CN 202011195229 A CN202011195229 A CN 202011195229A CN 112287623 B CN112287623 B CN 112287623B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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Abstract
The invention discloses a pretesting platform based on an FPGA and a V93000 tester, belonging to the field of chip testing, comprising the FPGA and the V93000 tester, wherein the V93000 tester is connected with a power supply module of the FPGA through an MS DPS board card and supplies power to the FPGA and a peripheral circuit, and the V93000 tester is directly connected with an IO module of the FPGA through a Pogo block module; the pre-test platform also comprises a BPI FLASH module, a NorFLASH module, a clock module and an SCI module; the BPI FLASH module is directly connected with the FPGA and is used for storing a netlist file of the SoC chip; the NorFLASH module is connected with the FPGA after voltage conversion and is used for storing an SoC chip program operating file; the FPGA configures the clock module through an SPI port; the SCI module realizes the control of the FPGA on the reading and writing of the serial port and is interconnected with other peripheral equipment for data transmission.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a pretesting platform based on an FPGA and a V93000 testing machine.
Background
With the rapid development of integrated circuits, SoC of integrated systems on chip is more and more widely used. In the whole design process of the SoC circuit, the test link is difficult, long in time consumption and high in cost. The test time is one month less, and the test time is several months more, and the cost can account for more than 50% of the manufacturing cost of the chip. The testing link in the development period of the chip has more and more influence and is a key factor for restricting the practical application of the SoC.
In a common chip test process, ATE test program development and chip verification are performed on a chip at the final stage of chip development, which takes a long time. Especially, the development of the ATE test program of some high-speed ports often takes several months, and the overall development period of the chip is increased.
Disclosure of Invention
The invention aims to provide a pre-test platform based on an FPGA and a V93000 tester, so as to realize the development of a test program and the verification of a chip in the design stage of an SoC chip.
In order to solve the technical problems, the invention provides a pretesting platform based on an FPGA and a V93000 tester, which comprises the FPGA and the V93000 tester, wherein the V93000 tester is connected with a power supply module of the FPGA through an MS DPS board card and supplies power to the FPGA and a peripheral circuit, and the V93000 tester is directly connected with an IO module of the FPGA through a Pogo block module;
the pre-test platform also comprises a BPI FLASH module, a NorFLASH module, a clock module and an SCI module; wherein the content of the first and second substances,
the BPI FLASH module is directly connected with the FPGA and is used for storing a netlist file of the SoC chip; the NorFLASH module is connected with the FPGA after voltage conversion and is used for storing SoC chip program running files; the FPGA configures the clock module through an SPI port; the SCI module realizes the control of the FPGA on the reading and writing of the serial port and is interconnected with other peripheral equipment for data transmission.
Optionally, the chip used by the BPI FLASH module is MT28GU01GAAA1 EGC.
Optionally, the NorFLASH module adopts a1 Gb-capacity S29GL01GP chip, performs voltage conversion through two level conversion chips GTL2000DL, and connects the S29GL01GP chip with the FPGA.
Optionally, the clock management chip used by the clock module is AD9518-4ABCPZ, and a reference clock thereof is provided by a crystal oscillator or an external SMA interface.
Optionally, a channel of the FPGA is connected to an SPI port of the chip AD9518-4ABCPZ through the voltage conversion chip TXS0108E, the FPGA completes configuration of the chip AD9518-4ABCPZ through an SPI interface, and a clock output by the chip AD9518-4ABCPZ is used by the FPGA.
Optionally, the chip used by the SCI module is MAX 3232E.
Optionally, the IO interface of the FPGA is connected to the UART port of the chip MAX32 3232E through the voltage conversion chip TXS0108E, so that the FPGA controls the reading and writing of the serial port and is interconnected with other peripherals to perform data transmission.
Optionally, the power supplies VCCINT _ FPGA, MGTAVCC _ FPGA, VCC1V8_ FPGA, MGTAUX _ FPGA, MGTAVTT _ FPGA, and VCC3V3 in the power supply module are powered by 15 lines of power supplies DPS11, DPS12, DPS13, DPS21, DPS22, DPS25, DPS26, DPS31, DPS32, DPS35, DPS36, DPS81, DPS82, DPS85, DPS86 of the MS DPS board card, and meet the required voltage and current.
Optionally, the IO module of the FPGA is connected to the V93000 tester through digital channels 101-124 and 225-232 of the Pogo block module.
Optionally, the BPI FLASH module, the NorFLASH module, the clock module, the SCI module, the power module, and the IO module are all integrated on the same circuit board.
Optionally, the model of the FPGA is XCVU440-FLGA 2892-1-C.
The pretesting platform based on the FPGA and the V93000 tester has high compatibility, and different chips can be pretested by the platform without repeatedly developing and designing boards. An ASIC code of an SoC chip is converted into an RTL code in a chip design stage, the RTL code runs in an FPGA prototype verification system, and then the FPGA prototype verification system is applied to a V93000 testing machine, so that test program development and debugging can be carried out; the test program is developed and debugged through an FPGA prototype verification system in the chip design stage instead of the conventional test in the last stage of chip development, so that the reliability and the correctness of chip design are ensured, the whole development period of the chip is greatly shortened, the design cost is saved, and the platform has higher utilization rate in the SoC chip design stage.
Drawings
FIG. 1 is a frame diagram of a pretest platform based on FPGA and V93000 tester provided by the present invention;
FIG. 2 is a schematic diagram of a BPI FLASH module;
FIG. 3 is a schematic diagram of a NorFLASH module;
FIG. 4 is a schematic diagram of a clock module;
FIG. 5 is a schematic diagram of an SCI module;
FIG. 6 is a schematic diagram of a power module;
fig. 7 is a schematic diagram of an IO module.
Detailed Description
The pretest platform based on the FPGA and the V93000 tester provided by the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a pretesting platform based on an FPGA and a V93000 tester, the architecture of which is shown in figure 1, and the pretesting platform comprises the FPGA and the V93000 tester, wherein the V93000 tester is connected with a power module of the FPGA through an MS DPS board card to supply power for the FPGA and a peripheral circuit, and the V93000 tester is directly connected with an IO module of the FPGA through a Pogo block module. The pre-test platform also comprises a BPI FLASH module, a NorFLASH module, a clock module and an SCI module.
As shown in fig. 2, the chip used by the BPI FLASH module is MT28GU01GAAA1EGC, and a 1.8V level signal thereof is directly connected to the FPGA for storing a netlist file of the SoC circuit.
FIG. 3 is a schematic diagram of the NorFLASH module, which employs a 1Gb S29GL01GP chip. And a 1.8V level signal of the FPGA is converted into 3.3V through two level conversion chips GTL2000DL and then is connected with the S29GL01GP chip for storing SoC chip program running files.
Fig. 4 is a schematic diagram of a clock module, and the clock management chip used is AD9518-4ABCPZ, and its reference clock is provided by a crystal oscillator or an external SMA interface. A1.8V level signal of the FPGA is converted into 3.3V through a level conversion chip TXS0108E and then is connected with a clock management chip AD9518-4ABCPz, the FPGA completes configuration of the clock management chip AD9518-4ABCPz through an SPI interface, and a clock output by the clock management chip AD9518-4ABCPz is used by the FPGA.
FIG. 5 is a schematic diagram of an SCI module, using a chip MAX 3232E. The 1.8V level signal of the FPGA is converted into 3.3V through a level conversion chip TXS0108E and then is connected with a UART port of a chip MAX3232E, so that the read-write control of the serial port by the FPGA is realized, and the data transmission is carried out by interconnecting with other peripherals.
FIG. 6 is a schematic diagram of a power module, in which power supplies VCCINT _ FPGA, MGTAVCC _ FPGA, VCC1V8_ FPGA, MGTAUX _ FPGA, MGTAVTT _ FPGA, and VCC3V3 required by a pre-test platform are supplied with power by 15 power supplies DPS11, DPS12, DPS13, DPS21, DPS22, DPS25, DPS26, DPS31, DPS32, DPS35, DPS36, DPS81, DPS82, DPS85, and DPS86 of an MS DPS board card, and the required voltages and currents are satisfied.
FIG. 7 is a schematic diagram of an IO interface module, which connects the V93000 tester and the FPGA through digital channels of pogo blocks such as 101-124, 225-232 on the V93000 tester to perform data transmission.
The BPI FLASH module, the NorFLASH module, the clock module, the SCI module, the power supply module and the IO module are all integrated on the same circuit board. The FPGA is XCVU440-FLGA2892-1-C in model. The invention simulates the SoC chip to run on the FPGA prototype verification system, and the test program development and debugging are carried out on the FPGA prototype verification system through the tester in the chip design stage, so as to ensure the reliability and the correctness of the chip design, greatly shorten the whole development period of the chip and save the design cost.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A pre-test platform based on an FPGA and a V93000 tester is characterized by comprising the FPGA and the V93000 tester, wherein the V93000 tester is connected with a power module of the FPGA through an MSDPS board card and supplies power to the FPGA and a peripheral circuit, and the V93000 tester is directly connected with an IO module of the FPGA through a Pogo block module;
the pre-test platform also comprises a BPI FLASH module, a NorFLASH module, a clock module and an SCI module; wherein the content of the first and second substances,
the BPI FLASH module is directly connected with the FPGA and is used for storing a netlist file of the SoC chip; the NorFLASH module is connected with the FPGA after voltage conversion and is used for storing an SoC chip program operating file; the FPGA configures the clock module through an SPI port; the SCI module realizes the control of the FPGA on the reading and writing of the serial port and is interconnected with other peripheral equipment for data transmission;
the NorFLASH module adopts a 1Gb S29GL01GP chip, voltage conversion is carried out through two level conversion chips GTL2000DL, and the S29GL01GP chip is connected with the FPGA;
the clock management chip used by the clock module is AD9518-4ABCPZ, and the reference clock is provided by a crystal oscillator or an external SMA interface;
the channel of the FPGA is connected with an SPI port of a chip AD9518-4ABCPz through a voltage conversion chip TXS0108E, the FPGA completes the configuration of the chip AD9518-4ABCPz through an SPI interface, and a clock output by the chip AD9518-4ABCPz is used by the FPGA;
the chip used by the SCI module is MAX 3232E;
the IO interface of the FPGA is connected with the UART port of the chip MAX32 3232E through the voltage conversion chip TXS0108E, so that the FPGA controls the reading and writing of the serial port and is interconnected with other peripheral devices for data transmission.
2. The pre-test platform based on the FPGA and the V93000 tester as claimed in claim 1, wherein the chip used by the BPI FLASH module is MT28GU01GAAA1 EGC.
3. The pre-test platform based on FPGA and V93000 tester as claimed in claim 1, wherein each power supply VCCINT _ FPGA, MGTAVCC _ FPGA, VCC1V8_ FPGA, MGTAUX _ FPGA, MGTAVTT _ FPGA, VCC3V3 in the power supply module is powered by 15 power supplies DPS11, DPS12, DPS13, DPS21, DPS22, DPS25, DPS26, DPS31, DPS32, DPS35, DPS36, DPS81, DPS82, DPS85, DPS86 of MSDPS board card to meet the required voltage and current.
4. The pre-test platform based on the FPGA and the V93000 tester as claimed in claim 1, wherein the IO module of the FPGA is connected to the V93000 tester through digital channels 101-124 and 225-232 of a Pogo block module.
5. The FPGA and V93000 tester based pretest platform of any one of claims 1-4, wherein the BPI FLASH module, the NorFLASH module, the clock module, the SCI module, the power module, and the IO module are all centralized on a same circuit board.
6. The pre-test platform based on the FPGA and the V93000 tester as set forth in any one of claims 1 to 4, wherein the model number of the FPGA is XCVU440-FLGA 2892-1-C.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202189124U (en) * | 2011-07-22 | 2012-04-11 | 航天科工防御技术研究试验中心 | FPGA multiple real-time reconfiguration adapter based on test system |
| CN104199756A (en) * | 2014-09-03 | 2014-12-10 | 航天科工防御技术研究试验中心 | FPGA multiple automatic configuration device and method |
| CN209590083U (en) * | 2018-12-25 | 2019-11-05 | 航天科工防御技术研究试验中心 | A kind of chip testing adapter |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202189124U (en) * | 2011-07-22 | 2012-04-11 | 航天科工防御技术研究试验中心 | FPGA multiple real-time reconfiguration adapter based on test system |
| CN104199756A (en) * | 2014-09-03 | 2014-12-10 | 航天科工防御技术研究试验中心 | FPGA multiple automatic configuration device and method |
| CN209590083U (en) * | 2018-12-25 | 2019-11-05 | 航天科工防御技术研究试验中心 | A kind of chip testing adapter |
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