CN108107351A - Adjustment method, debugger and the system of JTAG debuggers - Google Patents
Adjustment method, debugger and the system of JTAG debuggers Download PDFInfo
- Publication number
- CN108107351A CN108107351A CN201711276058.9A CN201711276058A CN108107351A CN 108107351 A CN108107351 A CN 108107351A CN 201711276058 A CN201711276058 A CN 201711276058A CN 108107351 A CN108107351 A CN 108107351A
- Authority
- CN
- China
- Prior art keywords
- signal
- jtag
- debuggers
- data
- debugging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present invention relates to JTAG device arts, and in particular to a kind of adjustment method, debugger and the system of JTAG debuggers include the following steps：(a) the SVF files of host computer transmission are received；(b) the SVF files are parsed and generate debugging signal；(c) the debugging signal is exported.The embodiment of the present invention employs and SVF files is directly parsed in JTAG debuggers and generate corresponding debugging signal without controlling jtag port level by USB port, substantially increases the debugging efficiency of JTAG debuggers.
Description
Technical field
The invention belongs to JTAG device arts, and in particular to a kind of JTAG adjustment methods, debugger and system.
Background technology
JTAG (Joint Test Action Group, JTAG) is a kind of international standard test protocol
(IEEE 1149.1 is compatible with) is mainly used for chip internal test.Most high-grade devices all supports JTAG protocol now, such as
DSP, FPGA, ARM, part microcontroller device etc..The jtag interface of standard is 4 lines：TMS, TCK, TDI, TDO are respectively mould
Formula selection, clock, data input and DOL Data Output Line.The definition of related JTAG pins is：TCK inputs for test clock；TDI is
Test data inputs, and data input jtag interface by TDI pins；TDO be test data output, data by TDO pins from
Jtag interface exports；TMS selects for test pattern, and TMS is used for that jtag interface is set to be in certain specific test pattern；TRST
For test reset, input pin, low level is effective.
Fig. 1 and Fig. 2 are referred to, Fig. 1 is the schematic diagram of JTAG adjustment methods of the prior art, and Fig. 2 is in the prior art
The corresponding signal waveform schematic diagram of SVF file data lines；Wherein, existing JTAG debugging techniques are by being parsed on PC
SVF (Serial Vector Format, referred to as serial vector format) corresponding port operation data of file generated, and pass through
USB channel transfer port operations data control the port level of JTAG, wherein, the data lines of SVF files corresponds to a series of
Jtag port operates, but USB passages once can be only done the transmission of a port operation data, a line SVF as shown in Figure 2
Corresponding signal waveforms need 26 USB communications that can just send data to test chip, therefore, cause USB passages and lead to
News data volume is excessive, limits the speed of JTAG debugging.
Therefore, the JTAG adjustment methods for how providing a kind of high speed have become the hot issue of research.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of JTAG adjustment methods, debuggers
And system.
The technical problem to be solved in the present invention is achieved through the following technical solutions：
One embodiment of the present of invention provides a kind of JTAG adjustment methods, including：
(a) the SVF files of host computer transmission are received；
(b) the SVF files are parsed and generate debugging signal；
(c) the debugging signal is exported.
In one embodiment of the invention, the debugging signal includes：Tck signal, tms signal, TDI signal.
In one embodiment of the invention, step (b) includes：
(b1) the SVF files are parsed and generate time sequence parameter, JTAG state machine datas, TCK data, TDI data；
(b2) time sequence parameter, JTAG state machine datas, the TCK data, the TDI data conversions are formed into sequential
Control signal, the tms signal, the tck signal, the TDI signal.
In one embodiment of the invention, further included after step (c)：
(x1) read TDO signal and generate TDO data；
(x2) desired value of the TDO data and SVF files is subjected to comparison and generates comparing result；
(x3) comparing result and the TDO data are exported.
An alternative embodiment of the invention provides a kind of JTAG debuggers, including：
Chip is received, for receiving the SVF files transmitted from host computer；
Chip is parsed, is connected with the reception chip, for parsing the SVF files and exporting debugging signal.
In one embodiment of the invention, the debugging signal includes：Tck signal, tms signal, TDI signal.
In one embodiment of the invention, the parsing chip includes：
SVF parsing modules, for parsing the SVF files and generating tune-up data；
JTAG state machine modules, for generating the tms signal；
TCK generation modules, for generating the tck signal；
TDI data outputting modules, for generating the TDI signal；
TDO data read modules, for reading TDO signal；
Time sequence parameter module, for generating timing control signal.
In one embodiment of the invention, the JTAG debuggers by USB port or network interface or serial ports or wifi or
Bluetooth or the ZigBee connections host computer.
In one embodiment of the invention, the JTAG debuggers test one or more test chips simultaneously.
An alternative embodiment of the invention provides a kind of JTAG debugging systems, including：In host computer and above-described embodiment
Any one of them JTAG debuggers.
Compared with prior art, beneficial effects of the present invention：
The embodiment of the present invention employs straight in JTAG debuggers without controlling jtag port level by USB port
It connects parsing SVF files and generates corresponding debugging signal, substantially increase the debugging efficiency of JTAG debuggers.
Description of the drawings
Fig. 1 is the schematic diagram of JTAG adjustment methods of the prior art；
Fig. 2 is the corresponding signal waveform schematic diagram of SVF files data line in the prior art；
Fig. 3 is a kind of structure diagram of JTAG debuggers provided in an embodiment of the present invention；
Fig. 4 is a kind of adjustment method flow diagram of JTAG debuggers provided in an embodiment of the present invention；
Fig. 5 is a kind of debugging principle schematic diagram of JTAG debuggers provided in an embodiment of the present invention；
Fig. 6 (a) is the tck clock of the adjustment method of the JTAG debuggers provided in an embodiment of the present invention using the prior art
Frequency waveform diagram；
Fig. 6 (b) is the TCK of the adjustment method of the JTAG debuggers provided in an embodiment of the present invention using the embodiment of the present invention
Clock frequency waveform diagram；
Fig. 7 is the debugging principle schematic diagram of another kind JTAG debuggers provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment 1：
Fig. 3 and Fig. 4, Fig. 3 are referred to as a kind of structure diagram of JTAG debuggers provided in an embodiment of the present invention, Fig. 4
For a kind of adjustment method flow diagram of JTAG debuggers provided in an embodiment of the present invention.The JTAG debuggers 10 can include
Chip 200 and parsing chip 100 are received, wherein receiving chip 200 is used to receive SVF files that host computer (PC machine) is sent simultaneously
Parsing chip 100 is transferred to, parsing chip 100 is used to parse the formation of SVF files for testing the test signal of chip to be measured.
Correspondingly, adjustment method of the invention can include：
(a) the SVF files of host computer transmission are received；
(b) the SVF files are parsed and generate debugging signal；
(c) the debugging signal is exported.
The embodiment of the present invention by increasing parsing chip in JTAG debuggers, will be parsed by host computer in the prior art
The work of SVF files is transferred to parsing chip completion, that is, parses chip and directly parse SVF files and generate corresponding debugging letter
Number, the problem of host computer parsing SVF files cause transmission time longer is reduced, substantially increases the debugging effect of JTAG debuggers
Rate.
Embodiment 2：
Fig. 5 is referred to, Fig. 5 is a kind of debugging principle schematic diagram of JTAG debuggers provided in an embodiment of the present invention.This reality
Example is applied, on the basis of above-described embodiment, the operation principle of the present invention is described in detail as follows：
Wherein, above-mentioned reception chip 200 is, for example, PHY chip, DVI interface, HDMI interface, USB interface, network interface etc.；Solution
It is, for example, MCU chip etc. to analyse chip 100.For the present embodiment to receive chip 200 as PHY chip, parsing chip 100 is MCU chip
Exemplified by.
The debugging signal that the JTAG debuggers 10 can generate includes：Tms signal, tck signal, TDI signal.
Specific debugging process is as follows：
First, user assigns test instruction by PC machine 20, forms SVF files 201 by PC machine 20, is led to afterwards by PC machine 20
It crosses port and SVF files 201 is sent to JTAG debuggers 10, the PHY chip 200 of JTAG debuggers 10 receives the SVF files 201
And the MCU chip 100 in JTAG debuggers 10 is sent to, the SVF parsing modules 101 of MCU chip 100 carry out SVF files 201
Parsing generation time sequence parameter, JTAG state machine datas, TCK data and TDI data and be transferred to respectively time sequence parameter module 106,
JTAG state machine modules 102, TCK generation modules 103, TDI data outputting modules 104.Wherein, time sequence parameter is used to generate sequential
Control signal controls the frequency of downstream clock, delay etc. between instruction.106 output timing control signal of time sequence parameter module is given
SVF parsing modules 101, SVF parsing modules 101 under the control of timing control signal under send instructions control JTAG state machine modules
102nd, TCK generation modules 103, TDI data outputting modules 104 sequentially generate TCK, TMS, TDI signal respectively, and by TDO data
Read module 105 read in TDO signal, by TDO signal be converted to TDO data be transferred to SVF parsing modules 100 and with SVF files
201 desired value comparison generation comparing result, SVF parsing modules 101 are again by PHY chip 200 and then will be right by USB port
PC is returned to than result.
Wherein, the desired value of SVF files has stored in the module for SVF document analysis module when parsing SVF files
Among.
Fig. 6 (a) and Fig. 6 (b) are refer to, Fig. 6 (a) is that the JTAG provided in an embodiment of the present invention using the prior art is debugged
The tck clock frequency waveform diagram of the adjustment method of device；Fig. 6 (b) is implemented to be provided in an embodiment of the present invention using the present invention
The tck clock frequency waveform diagram of the adjustment method of the JTAG debuggers of example；Using the JTAG debuggers of the embodiment of the present invention
Adjustment method after, tck clock frequency from 1MHz by being increased to 8.3MHz namely debugging speed improves 8 times.
Embodiment 3：
Fig. 7 is referred to, Fig. 7 is the debugging principle schematic diagram of another kind JTAG debuggers provided in an embodiment of the present invention,
On the basis of the above, the adjustment method of another JTAG debuggers 10 is described in detail below, which can
To connect multiple test chips progress while debug；
Wherein, the test chip such as the first test chip, the second test chip, the 3rd test including being sequentially connected in series
Chip, wherein, generate tck signal, tms signal and TDI signal after JTAG modulators parsing SVF files, tck signal and
Tms signal is transmitted separately to the first test chip, the second test chip, the 3rd test chip, and TDI signal is transmitted to the first test
Chip TDI interfaces and the TDO interfaces output for passing through the first test chip, similarly successively by the second test chip and the 3rd test
Chip finally exports TDO signal to JTAG debuggers from the TDO interfaces of the 3rd test chip.
The embodiment of the present invention directly parses the corresponding tune-up data of SVF file generateds and then generation pair in JTAG debuggers
The debugging signal answered, while the TDO signal of reception and SVF files are compared, feed back comparing result, the multiple surveys of synchronism detection
Chip is tried, substantially increases the debugging efficiency of JTAG debuggers.
Embodiment 4：
Referring again to Fig. 5, the embodiment of the present invention describes a kind of JTAG debugging systems, the JTAG debugging systems in detail
It can include：Host computer 20 and JTAG debuggers 10, JTAG tune of the JTAG debuggers involved by any of the above-described embodiment
Try device.
Certainly, the USB port of the present embodiment can be replaced into other wireline interfaces, such as other are general for network interface, serial ports etc.
Interface；Wireless interface, such as wifi, bluetooth or ZigBee etc. can also be replaced into.
The JTAG debugging systems of the embodiment of the present invention, the SVF files of PC are once transferred to JTAG debugging by USB port
Device performs SVF document analysis by the MCU chip in JTAG debuggers and generates debugging signal, improves entire debugging system
Efficiency.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
On the premise of not departing from present inventive concept, several simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of adjustment method of JTAG debuggers, it is characterised in that：Including：
(a) the SVF files of host computer transmission are received；
(b) the SVF files are parsed and generate debugging signal；
(c) the debugging signal is exported.
2. adjustment method according to claim 1, which is characterized in that the debugging signal includes：Tck signal, TMS letters
Number, TDI signal.
3. adjustment method according to claim 2, it is characterised in that：Step (b) includes：
(b1) the SVF files are parsed and generate time sequence parameter, JTAG state machine datas, TCK data, TDI data；
(b2) time sequence parameter, JTAG state machine datas, the TCK data, the TDI data conversions are formed into timing control
Signal, the tms signal, the tck signal, the TDI signal.
4. adjustment method according to claim 1, it is characterised in that：It is further included after step (c)：
(x1) read TDO signal and generate TDO data；
(x2) desired value of the TDO data and SVF files is subjected to comparison and generates comparing result；
(x3) comparing result and the TDO data are exported.
5. a kind of JTAG debuggers, it is characterised in that：Including：
Chip is received, for receiving the SVF files transmitted from host computer；
Chip is parsed, is connected with the reception chip, for parsing the SVF files and exporting debugging signal.
6. JTAG debuggers according to claim 5, it is characterised in that：The debugging signal includes：Tck signal, TMS letters
Number, TDI signal.
7. JTAG debuggers according to claim 6, it is characterised in that：The parsing chip includes：
SVF parsing modules, for parsing the SVF files and generating tune-up data；
JTAG state machine modules, for generating the tms signal；
TCK generation modules, for generating the tck signal；
TDI data outputting modules, for generating the TDI signal；
TDO data read modules, for reading TDO signal；
Time sequence parameter module, for generating timing control signal.
8. JTAG debuggers according to claim 5, it is characterised in that：The JTAG debuggers pass through USB port or net
Mouth or serial ports or wifi or bluetooth or the ZigBee connections host computer.
9. JTAG debuggers according to claim 5, it is characterised in that：The JTAG debuggers test one or more simultaneously
A test chip.
10. a kind of JTAG debugging systems, it is characterised in that：Including：Any one of host computer and claim 5~9
JTAG debuggers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711276058.9A CN108107351A (en) | 2017-12-06 | 2017-12-06 | Adjustment method, debugger and the system of JTAG debuggers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711276058.9A CN108107351A (en) | 2017-12-06 | 2017-12-06 | Adjustment method, debugger and the system of JTAG debuggers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108107351A true CN108107351A (en) | 2018-06-01 |
Family
ID=62208176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711276058.9A Pending CN108107351A (en) | 2017-12-06 | 2017-12-06 | Adjustment method, debugger and the system of JTAG debuggers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108107351A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| WO2022052161A1 (en) * | 2020-09-09 | 2022-03-17 | 国微集团(深圳)有限公司 | Chip debugging system and debugger |
| CN117728899A (en) * | 2024-02-06 | 2024-03-19 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
| CN117728899B (en) * | 2024-02-06 | 2024-06-04 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770417A (en) * | 2010-01-15 | 2010-07-07 | 哈尔滨工业大学 | Hardware fault injection system and fault injection method based on JTAG |
| CN102130951A (en) * | 2011-03-14 | 2011-07-20 | 浪潮(北京)电子信息产业有限公司 | Server and method for remotely upgrading programmable logic device thereof |
| CN102778645A (en) * | 2011-05-09 | 2012-11-14 | 京微雅格（北京）科技有限公司 | JTAG (joint test action group) main controller and realization method of JTAG main controller |
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN203250308U (en) * | 2013-04-28 | 2013-10-23 | 杭州士兰微电子股份有限公司 | USB JTAG conversion debugging device internally embedded in chip |
| CN103376340A (en) * | 2013-07-04 | 2013-10-30 | 曙光信息产业(北京)有限公司 | Adapter plate, a multi-platform serial test system and method |
| CN107066276A (en) * | 2017-04-17 | 2017-08-18 | 中国电子科技集团公司第三十四研究所 | The method that a kind of FPGA device Remote configuration in communication equipment updates |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
-
2017
- 2017-12-06 CN CN201711276058.9A patent/CN108107351A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770417A (en) * | 2010-01-15 | 2010-07-07 | 哈尔滨工业大学 | Hardware fault injection system and fault injection method based on JTAG |
| CN102130951A (en) * | 2011-03-14 | 2011-07-20 | 浪潮(北京)电子信息产业有限公司 | Server and method for remotely upgrading programmable logic device thereof |
| CN102778645A (en) * | 2011-05-09 | 2012-11-14 | 京微雅格（北京）科技有限公司 | JTAG (joint test action group) main controller and realization method of JTAG main controller |
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN203250308U (en) * | 2013-04-28 | 2013-10-23 | 杭州士兰微电子股份有限公司 | USB JTAG conversion debugging device internally embedded in chip |
| CN103376340A (en) * | 2013-07-04 | 2013-10-30 | 曙光信息产业(北京)有限公司 | Adapter plate, a multi-platform serial test system and method |
| CN107066276A (en) * | 2017-04-17 | 2017-08-18 | 中国电子科技集团公司第三十四研究所 | The method that a kind of FPGA device Remote configuration in communication equipment updates |
| CN107122304A (en) * | 2017-05-03 | 2017-09-01 | 成都定为电子技术有限公司 | A kind of JTAG remote debugging methods |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| CN109444723B (en) * | 2018-12-24 | 2020-07-24 | 成都华微电子科技有限公司 | Chip testing method based on J750 |
| WO2022052161A1 (en) * | 2020-09-09 | 2022-03-17 | 国微集团(深圳)有限公司 | Chip debugging system and debugger |
| CN117728899A (en) * | 2024-02-06 | 2024-03-19 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
| CN117728899B (en) * | 2024-02-06 | 2024-06-04 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8281280B2 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| CN102541707B (en) | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method | |
| CN105550119B (en) | A kind of simulator based on JTAG protocol | |
| EP1832887A1 (en) | A test access port controller and a method of effecting communication using the same | |
| US7444571B1 (en) | Apparatus and method for testing and debugging an integrated circuit | |
| CN105807202B (en) | Integrated circuit testing board | |
| CN104820637B (en) | A kind of hand-held USB3.0 protocol analyzers | |
| CN105357070A (en) | FPGA-based ARINC818 bus analysis and test apparatus | |
| CN102880536A (en) | JTAG (joint test action group) debug method of multi-core processor | |
| CN102662835A (en) | Program debugging method of embedded system and embedded system | |
| CN104536867B (en) | System and method for debugging multiple field-programmable gate arrays | |
| CN109815099A (en) | The FPGA verification method of JESD204B controller | |
| CN101770417A (en) | Hardware fault injection system and fault injection method based on JTAG | |
| CN105653409B (en) | A kind of hardware emulator verify data extraction system based on data type conversion | |
| CN106294144B (en) | Generation method, system and the server of the test vector of serial communication protocol | |
| CN206348634U (en) | A kind of Multipath digital quantity acquisition process board based on FPGA | |
| CN104992650B (en) | MIPI signals automatic test approach and device | |
| CN106341181A (en) | Fiber link test system | |
| CN103049361A (en) | FPGA (Field Programmable Gata Array) with embedded logical analysis function and logical analysis system | |
| CN108107351A (en) | Adjustment method, debugger and the system of JTAG debuggers | |
| CN113533936A (en) | Chip scan chain test method and system | |
| CN103257606B (en) | A kind of USB interface high-speed real-time sampling logic analyser | |
| CN103592599A (en) | USB-based logic analyzer triggering device | |
| CN106294228A (en) | Input and output extended chip and its verification method | |
| CN108563545B (en) | SOPC function verification method and system with coverage rate driving software and hardware in cooperation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180601 |