CN103257606B - A kind of USB interface high-speed real-time sampling logic analyser - Google Patents
A kind of USB interface high-speed real-time sampling logic analyser Download PDFInfo
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- CN103257606B CN103257606B CN201310142187.4A CN201310142187A CN103257606B CN 103257606 B CN103257606 B CN 103257606B CN 201310142187 A CN201310142187 A CN 201310142187A CN 103257606 B CN103257606 B CN 103257606B
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Abstract
A kind of USB interface high-speed real-time sampling logic analyser, comprise Single Chip Microcomputer (SCM) system and FPGA system, wherein, Single Chip Microcomputer (SCM) system comprises usb interface module, GPIF module, spi bus module, FPGA boot configuration module and program ram execution module; FPGA system comprises FPGA program execution module, fifo controller module, indicating lamp module and channel sample rate selecting/sampling module.The present invention adopts Single Chip Microcomputer (SCM) system+FPGA system framework, has the advantage of high-speed real-time sampling.The synchronous clock that Single Chip Microcomputer (SCM) system realizes GPIF state machine adopts 100MHz work, achieves usb bus real-time Transmission 600Mbps sample source data.
Description
Technical field
The present invention relates to a kind of USB interface high-speed real-time sampling logic analyser, belong to digital processing field.
Background technology
USB(Universal Serial BUS) USB (universal serial bus): be an external bus standard, for connection and the communication of specification computer and external unit.It is the interfacing being applied in PC field.The plug and play of USB interface support equipment and warm connection function.After having delivered USBV0.7 version from November 11st, 1994, USB version experienced by development for many years, has developed into 3.0 versions till now, becomes the standard extension interface in current computer.Can be well compatible between each USB version, the maximum transmission rate of USB1.1 is 12Mbps, USB2.0 maximum transmission rate be 480Mbps, USB3.0 maximum transmission rate is 5Gbps.
FPGA(Field-Programmable Gate Array), i.e. field programmable gate array, it is the product further developed on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.
Logic analyser: utilize clock gather from testing apparatus and show the instrument of digital signal, main effect is that sequential judges.Because logic analyser has a lot of electric pressure unlike oscillograph, usually only two voltages (logical one and 0) are shown, therefore after setting reference voltage, measured signal is judged by comparer by logic analyser, be High higher than reference voltage person, be Low lower than reference voltage person, between High and Low, form digital waveform.
Logic analyser generally acknowledges one of outstanding instrument in Digital Design verification and debugging process.Whether it can normally work by check digit circuit, and helps user to search and fix a breakdown.In object code test event, sum up logic analyser field and there is following defect:
(1), to there is sampling depth in traditional logic analyser limited, is generally 32KB ~ 512KB, is difficult to capture the whole Wave datas broken down.
(2), traditional logic analyser adopts non real-time transmission, and the transmission of interruption can not ensure the integrality of catching waveform.
Summary of the invention
Technology of the present invention deal with problems for: overcome the deficiencies in the prior art, provide a kind of USB interface high-speed real-time sampling logic analyser.
Technical solution of the present invention is:
A kind of USB interface high-speed real-time sampling logic analyser, comprise Single Chip Microcomputer (SCM) system and FPGA system, wherein, Single Chip Microcomputer (SCM) system comprises usb interface module, GPIF module, spi bus module, FPGA boot configuration module and program ram execution module; FPGA system comprises FPGA program execution module, fifo controller module, indicating lamp module and channel sample rate selecting/sampling module;
Single Chip Microcomputer (SCM) system carries out communication by its usb interface module and outer PC, and the configurator of Single Chip Microcomputer (SCM) system is sent in program ram execution module by usb interface module and carried out storing and performing by PC; PC is also transparently forwarded to FPGA program execution module by the FPGA configuration file that usb interface module inputs by the FPGA boot configuration module in Single Chip Microcomputer (SCM) system, thus is configured FPGA system and makes FPGA start working; Telecommand is sent to spi bus module by usb interface module by PC, spi bus module receives described telecommand and sends to the channel sample rate selecting/sampling module in FPGA system to arrange passage and sample frequency by spi bus after parsing sampling parameter, and sampling parameter state is returned to PC by spi bus module and usb interface module by described channel sample rate selecting/sampling module successively after setting completed; Channel sample rate selecting/sampling module is sampled to external data according to the sampling parameter set, by sampling, the data obtained are stored in fifo controller module, fifo controller module sends request to GPIF module, GPIF module returns to fifo controller module answer signal after receiving request, GPIF module also obtains sampled data from fifo controller module simultaneously, and the data received are sent in PC by usb interface module by GPIF module; Indicating lamp module works to during outside data sampling in channel sample rate selecting/sampling module, controls pilot lamp flickering display.
Described transparent forwarding refers to that the FPGA configuration file before and after forwarding is identical, and described FPGA boot configuration module does not change FPGA configuration file.
Described fifo controller module sends a described request signal every (2n-1) × 10ns time to GPIF module, wherein, when the sampling channel parameter arranged is 1, and n=3; When the sampling channel parameter arranged is 2, n=4; When the sampling channel parameter arranged is more than or equal to 3, n equals sampling channel parameter.
Described GPIF module is after the request signal receiving the transmission of fifo controller module, and delayed 17.5ns returns answer signal.
The working clock frequency of described fifo controller module is 100MHz.
The working clock frequency of described GPIF module is 100MHz.
The beneficial effect of patent of the present invention is:
(1), the present invention adopts Single Chip Microcomputer (SCM) system+FPGA system framework, has the advantage of high-speed real-time sampling.The synchronous clock that Single Chip Microcomputer (SCM) system realizes GPIF state machine adopts 100MHz work, achieves usb bus real-time Transmission 600Mbps sample source data.
(2), real-time sampling frequency can be configured to 600MHz, 300MHz, 200MHz, 100MHz etc.
(3), USB interface high speed data transfer, usb bus is powered, support hot plug, plug and play.
(4) independent Power supply, is not needed, easy to carry, be both applicable to laboratory and used, and be also applicable to go on business or field use.
Accompanying drawing explanation
Fig. 1 structural principle block diagram of the present invention.
Fig. 2 Single Chip Microcomputer (SCM) system of the present invention realizes GPIF state machine timing diagram.
Embodiment
Be illustrated in figure 1 structural principle block diagram of the present invention.Comprise Single Chip Microcomputer (SCM) system and FPGA system, wherein, Single Chip Microcomputer (SCM) system comprises usb interface module, GPIF module, spi bus module, FPGA boot configuration module and program ram execution module; FPGA system comprises FPGA program execution module, fifo controller module, indicating lamp module and channel sample rate selecting/sampling module;
Single Chip Microcomputer (SCM) system carries out communication by its usb interface module and outer PC, and the configurator of Single Chip Microcomputer (SCM) system is sent in program ram execution module by usb interface module and carried out storing and performing by PC; PC is also transparently forwarded to FPGA program execution module by the FPGA configuration file that usb interface module inputs by the FPGA boot configuration module in Single Chip Microcomputer (SCM) system, thus is configured FPGA system and makes FPGA start working; Telecommand is sent to spi bus module by usb interface module by PC, spi bus module receives described telecommand and sends to the channel sample rate selecting/sampling module in FPGA system to arrange passage and sample frequency by spi bus after parsing sampling parameter, and sampling parameter state is returned to PC by spi bus module and usb interface module by described channel sample rate selecting/sampling module successively after setting completed; Channel sample rate selecting/sampling module is sampled to external data according to the sampling parameter set, by sampling, the data obtained are stored in fifo controller module, fifo controller module sends request to GPIF module, GPIF module returns to fifo controller module answer signal after receiving request, GPIF module also obtains sampled data from fifo controller module simultaneously, and the data received are sent in PC by usb interface module by GPIF module; Indicating lamp module works to during outside data sampling in channel sample rate selecting/sampling module, controls pilot lamp flickering display.
Described transparent forwarding refers to that the FPGA configuration file before and after forwarding is identical, and described FPGA boot configuration module does not change FPGA configuration file.
As shown in Figure 2, fifo controller module sends a described request signal MCU_READY every (2n-1) × 10ns time to GPIF module, wherein, when the sampling channel parameter arranged is 1, and n=3; When the sampling channel parameter arranged is 2, n=4; When the sampling channel parameter arranged is more than or equal to 3, n equals sampling channel parameter.Described GPIF module is after the request signal MCU_READY receiving the transmission of fifo controller module, and delayed 17.5ns returns answer signal MCU_RD, and the working clock frequency IF_CLK of fifo controller module and GPIF module is 100MHz.
For n=3, illustrate and how to realize the real-time 600Mbps high-speed sampling of usb bus.The sampling module of FPGA system gathers 3 each 1bit data of passage every 5ns simultaneously and is stored into fifo controller module, when each passage is filled with 16bit data (FPGA system sampling needs the time to be 80ns), GPIF module simultaneously to Single Chip Microcomputer (SCM) system sends request signal MCU_READY, the delayed 17.5ns of GPIF module of Single Chip Microcomputer (SCM) system sends answer signal MCU_RD, and obtain 3 channel datas (namely the time of Single Chip Microcomputer (SCM) system acquisition sampled data is 17.5ns+ (2 × 3-1) × 10ns=67.5ns) from FD [15:0], thus realize 3 passage 200Mbps high-speed real-time sampling data, namely the real-time 600Mbps high-speed sampling of usb bus is realized.
The working clock frequency IF_CLK of current GPIF module is up to 100MHz.Along with updating of chip technology, if the GPIF module work clock frequency IF_CLK of Single Chip Microcomputer (SCM) system can improve later, the high-speed real-time sampling rate that so Single Chip Microcomputer (SCM) system and FPGA system realize can also improve.
Provide the embodiment of the present invention below:
Online updating single-chip microcomputer firmware and series arrangement FPGA program.First connect USB interface to PC, Single Chip Microcomputer (SCM) system and FPGA system power on and start working.PC application program is by after usb interface module down loading updating single-chip microcomputer firmware, and single-chip microcomputer firmware stores at program ram execution module and performs.Then, after PC application program sends series arrangement FPGA binary data by the FPGA boot configuration module of Single Chip Microcomputer (SCM) system, FPGA program is run in FPGA program execution module.
High speed real-time logic analysis instrument arranges sampling parameter process.Instruction that Single Chip Microcomputer (SCM) system and FPGA system circular wait " arrange sampling parameter ", PC application program is selected to arrange sampling parameter instruction, " sampling parameter is set " instruction is sent by usb interface module, Single Chip Microcomputer (SCM) system receives " sampling parameters ", the channel sample rate selecting/sampling module of FPGA system is sent to after being resolved by spi bus module, and sampling parameter is set, sampling parameter comprises: 1 passage 600MHz samples, 2 passage 300MHz sample, 3 passage 200MHz sample, 6 path 10 0MHz sample.After arranging sampling parameter, send " sampling parameter state " to Single Chip Microcomputer (SCM) system, Single Chip Microcomputer (SCM) system sends to PC application program " sampling parameter state ".
High speed real-time logic analysis instrument sampled data process.Instruction that Single Chip Microcomputer (SCM) system and FPGA system circular wait " start sampling ", PC application program sends " starting sampling " instruction by usb interface module, after Single Chip Microcomputer (SCM) system receives " start sampling " instructions parse, Single Chip Microcomputer (SCM) system GPIF state machine is started working, and Single Chip Microcomputer (SCM) system realizes GPIF state machine timing diagram in detail as shown in Figure 2.Single Chip Microcomputer (SCM) system sends " start sampling " to the channel sample rate selecting/sampling module of FPGA system by spi bus module, according to the setting of passage and sampling rate, is stored in fifo controller module after gathering raw data.
The synchronous clock of Single Chip Microcomputer (SCM) system GPIF state machine is IF_CLK=100MHz, and default data bus FD [15:0] is high-impedance state, MCU_READY is high level, MCU_RD is high level.When FPGA system meets according to synchronous clock IF_CLK detection sampling rate, at IF_CLK synchronous clock rising edge, exporting MCU_READY to Single Chip Microcomputer (SCM) system is low level, at the next rising edge of IF_CLK synchronous clock, sampled data in FIFO is outputted to data bus FD [15:0], it is after low level that Single Chip Microcomputer (SCM) system GPIF state machine detects MCU_READY, at the next rising edge of IF_CLK synchronous clock, start image data bus FD [15:0] data, and be low level to FPGA system output MCU_RD, it is high level that an all after date of IF_CLK synchronous clock arranges MCU_RD.Single Chip Microcomputer (SCM) system reads the sampled data in FPGA system fifo controller module according to the circulation of GPIF state machine sequential.When full 512 byte of Single Chip Microcomputer (SCM) system acquisition sampled data, transmit sampled data by USB interface to PC application program, now Single Chip Microcomputer (SCM) system GPIF state machine is in S0 waiting status.In the process of real-time sampling, pilot lamp carries out flickering display.
High speed real-time logic analysis instrument terminates sampling.Instruction that Single Chip Microcomputer (SCM) system and FPGA system circular wait " terminate sampling ", PC application program sends " terminating sampling " instruction by usb interface module, after Single Chip Microcomputer (SCM) system receives " terminate sampling " instructions parse, Single Chip Microcomputer (SCM) system GPIF state machine quits work.Single Chip Microcomputer (SCM) system sends " terminating sampling " to the channel sample rate selecting/sampling module of FPGA system by spi bus module, stops sample source data, reset fifo controller module.
The content be not described in detail in patent specification of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (1)
1. a USB interface high-speed real-time sampling logic analyser, it is characterized in that comprising Single Chip Microcomputer (SCM) system and FPGA system, wherein, Single Chip Microcomputer (SCM) system comprises usb interface module, GPIF module, spi bus module, FPGA boot configuration module and program ram execution module; FPGA system comprises FPGA program execution module, fifo controller module, indicating lamp module and channel sample rate selecting/sampling module;
Single Chip Microcomputer (SCM) system carries out communication by its usb interface module and outer PC, and the configurator of Single Chip Microcomputer (SCM) system is sent in program ram execution module by usb interface module and carried out storing and performing by PC; PC is also transparently forwarded to FPGA program execution module by the FPGA configuration file that usb interface module inputs by the FPGA boot configuration module in Single Chip Microcomputer (SCM) system, thus is configured FPGA system and makes FPGA start working; Telecommand is sent to spi bus module by usb interface module by PC, spi bus module receives described telecommand and sends to the channel sample rate selecting/sampling module in FPGA system to arrange passage and sample frequency by spi bus after parsing sampling parameter, and sampling parameter state is returned to PC by spi bus module and usb interface module by described channel sample rate selecting/sampling module successively after setting completed; Channel sample rate selecting/sampling module is sampled to external data according to the sampling parameter set, by sampling, the data obtained are stored in fifo controller module, fifo controller module sends request to GPIF module, GPIF module returns to fifo controller module answer signal after receiving request, GPIF module also obtains sampled data from fifo controller module simultaneously, and the data received are sent in PC by usb interface module by GPIF module; Indicating lamp module works to during outside data sampling in channel sample rate selecting/sampling module, controls pilot lamp flickering display;
Described transparent forwarding refers to that the FPGA configuration file before and after forwarding is identical, and described FPGA boot configuration module does not change FPGA configuration file;
Described fifo controller module sends a described request signal every (2n-1) × 10ns time to GPIF module, wherein, when the sampling channel parameter arranged is 1, and n=3; When the sampling channel parameter arranged is 2, n=4; When the sampling channel parameter arranged is more than or equal to 3, n equals sampling channel parameter;
Described GPIF module is after the request signal receiving the transmission of fifo controller module, and delayed 17.5ns returns answer signal;
The working clock frequency of described fifo controller module is 100MHz;
The working clock frequency of described GPIF module is 100MHz.
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| CN105372467B (en) * | 2015-12-23 | 2019-04-16 | 广东威创视讯科技股份有限公司 | Signal monitoring method and system |
| CN106483400B (en) * | 2016-09-23 | 2019-09-17 | 深圳市华壹科技有限责任公司 | Mobile terminal logic analyser |
| CN106528468A (en) * | 2016-10-11 | 2017-03-22 | 深圳市紫光同创电子有限公司 | USB data monitoring apparatus, method and system |
| CN106557440B (en) * | 2016-11-29 | 2019-08-16 | 青岛金思特电子有限公司 | A kind of system and method for realizing logic analyser super large storage depth |
| CN108155911B (en) * | 2017-12-04 | 2021-06-25 | 西安电子科技大学 | Non-uniform ultra-wideband sparse signal sampling method based on FPGA |
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