CN201072435Y

CN201072435Y - Logic analyzer

Info

Publication number: CN201072435Y
Application number: CNU2007200072927U
Authority: CN
Inventors: 王贤福; 蔡小丹; 蔡强; 胡伦育
Original assignee: Fujian Newland Computer Co Ltd
Current assignee: Fujian Newland Computer Co Ltd
Priority date: 2007-06-07
Filing date: 2007-06-07
Publication date: 2008-06-11
Anticipated expiration: 2017-06-07

Abstract

The utility model relates to a field of electric signal testing and electric signal simulation, in particular to a logic analyzer which is applied to logic functional testing of integrated circuits. The technical proposal of the utility model is that: the utility model comprises a special integrated circuit module FPGA with a function of hardware compression, which is respectively connected with a SDRAM buffer zone, a clock signal generator, a digital signal acquisition interface, an AD conversion module, a parallel communication interface, a cascade expansion interface and a power supply module, wherein, the AD conversion module is connected with a impedance transformation module through an analog signal channel; the impedance transformation module is connected with an analog signal acquisition interface. The digital signal acquisition interface and the analog signal acquisition interface are connected with a target board in a cascade mode through acquisition modules and signal acquisition lines. The advantage of the utility model is that: since the utility model is a virtual logic analyzer based on PC, a display and a host can be used separately, the utility model has simple structure and low price.

Description

Logic analyser

Technical field

The utility model relates to electronic signal test and field, electronic signal simulation aspect, especially belongs to the logic analyser that integrated circuit is carried out the logic function test.

Technical background

The logic analyser that uses in the background technology generally is that all testing softwares, computing managent component are incorporated among the instrument, and its complex structure costs an arm and a leg, and does not wait from several ten thousand yuan to hundreds of thousands unit, has therefore limited the popularization and application of logic analyser.

Summary of the invention

The purpose of this utility model is to provide a kind of FVLA based on PC, and it is simple in structure, and is cheap, can finish operating functions such as data acquisition, timing analysis and data readback.

Technical solution adopted in the utility model is: it comprises the special IC module FPGA with hardware compression functionality and is connected with supply module with SDRAM data buffer, clock-signal generator, digital signal acquiring interface, AD modular converter, parallel communication interface, cascade expansion interface respectively;

Wherein, the AD modular converter is connected with the impedance conversion module by analog signal channel, and the impedance conversion module is connected with the collection of simulant signal interface;

The digital signal acquiring interface adopts cascade system to be connected by acquisition module, signals collecting line with Target Board with the collection of simulant signal interface.

Usefulness of the present utility model is: 1, because the utility model is based on the FVLA of PC, display screen can separate with main frame and uses, so simple in structure, cheap; 2, because the hardware-compressed mode is adopted in the utility model collection storage, and setting timing waveform data can be played back to dedicated tunnel; Signals collecting can be provided with multiple mode and trigger, and has the live signal time sequence status is analyzed automatically; Waveform shows the employing hybrid mode and has distinctive signal decoding and displaying function (RS232, USB, HDLC, I ²C, the special decoding of data such as magnetic card, PS2), therefore easy to use, simple to operate; 3, the utility model equipment is light, and is easy to carry, is fit to field work.

Description of drawings

Fig. 1 the utility model structural principle block diagram

Fig. 2 the utility model acquisition module Target Board cascade system theory diagram

Embodiment

Be illustrated in figure 1 as the utility model structural principle block diagram, Fig. 2 is an acquisition module Target Board cascade system theory diagram.The utility model comprises the special IC module FPGA with hardware compression functionality and is connected with supply module with SDRAM data buffer, clock-signal generator, digital signal acquiring interface, AD modular converter, parallel communication interface, cascade expansion interface respectively as shown in the figure;

Having the PC end software that the special IC module FPGA of hardware compression functionality cooperated in the utility model can be written into logic analyser with the timing waveform data software of setting, and it is played back to dedicated tunnel simultaneously in sampling process.

Have the PC end software that the special IC module FPGA of hardware compression functionality cooperated in the utility model and can realize USB, RS232, HDLC, I by the waveform display window ²The special decoding of the Wave data of C, magnetic card, PS2.

Specifically set forth its programme of work below in conjunction with accompanying drawing:

The special IC module FPGA that has hardware compression functionality as shown in Figure 1 in the utility model partly is a core component of the present utility model, it is controlled the collection of each analog quantity and semaphore and the data of gathering is temporarily stored among the SDRAM, and control data effectively is transferred to the PC storage and makes related software and handle simultaneously.

The collection of simulant signal interface comprises 16 tunnel simulating signal input channels in the utility model as shown in Figure 1, it finish with Target Board in being connected of simulating signal; And the impedance conversion module section can guarantee that simulating signal is sampled without distortion; Analog signal channel selects to finish AD translated channel selection function; 10 AD modular converters are finished the conversion of analog quantity to digital quantity.

The digital signal acquiring interface comprises 32 way word signals collecting input channels, it finish with Target Board in being connected of digital signal.

The reference clock of clock-signal generator when guaranteeing the FPGA acquired signal.

SDRAM can expand to the 64MByte space, and the data that collect by FPGA are stored in SDRAM inside temporarily, is transferred in PC or other terminal device by the parallel communication interface timesharing again, handles for virtual instrument software.

Supply module offers each die worker and makes power supply, ensures each module operate as normal.

The cascade expansion interface is finished linkage function between acquisition module, guarantees the synchronous operate as normal of each module.

Be illustrated in figure 2 as the utility model acquisition module Target Board cascade system theory diagram.Wherein acquisition module comprises acquisition module 1, acquisition module 2, acquisition module 3, acquisition module 4, be to be in the same place between them by corresponding data line and address signal and clock-signal generator cascade, carry out synchronous acquisition, make the corresponding multiplication of digital signal acquiring interface with the collection of simulant signal interface.After the various test point signals of reserving on signals collecting line and the Target Board are connected, but the various signal ruuning situations of monitoring objective plate make Target Board work transparence.Simultaneously also can be sent to Target Board to pumping signal by acquisition module by PC software operation interface, the running status of analyzing and processing Target Board and correlation parameter, thus realize the autorun of logic analyser to Target Board.

Claims

1. logic analyser is characterized in that:

It comprises the special IC module FPGA with hardware compression functionality and is connected with supply module with SDRAM data buffer, clock-signal generator, digital signal acquiring interface, AD modular converter, parallel communication interface, cascade expansion interface respectively;