CN103592599A - USB-based logic analyzer triggering device - Google Patents
USB-based logic analyzer triggering device Download PDFInfo
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- CN103592599A CN103592599A CN201310537697.1A CN201310537697A CN103592599A CN 103592599 A CN103592599 A CN 103592599A CN 201310537697 A CN201310537697 A CN 201310537697A CN 103592599 A CN103592599 A CN 103592599A
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Abstract
The invention relates to the triggering circuit design technology, and discloses a logic analyzer triggering device based on a USB. The logic analyzer triggering device based on the USB comprises a data channel, a delay module, a series-parallel conversion module, a burr detection module, a state sampling module, a timing sampling module, a fractional frequency module, a clock channel, a clock selection module, a triggering identification module, a storage control module, a data storage module, a USB interface circuit, a PC host and a coding / configuration register reader-writer device. The data channel is respectively connected with the delay module and the series-parallel conversion module, the delay module is respectively connected with the burr detection module and the state sampling module, the series-parallel conversion module is respectively connected with the timing sampling module and the fractional frequency module, and the burr detection module, the state sampling module and the timing sampling module are respectively connected with the data storage module. The fractional frequency module and the clock channel are respectively connected with the clock selection module. The logic analyzer triggering device based on the USB improves portability of an analyzer, so that the logic analyzer based on a USB interface has great economic benefits and practical significance.
Description
Technical field
The present invention relates to trigger circuit design field, relate in particular to a kind of device based on USB Flip-flop Circuit within Digital Logic Analyzer.
Background technology
Along with the development of electronic technology, the future development that the design of digital display circuit is just high towards complexity, operating rate is fast, has higher requirement to testing tool.The traditional method of testing and the testing tool that by the time and frequency domain analysis of simulation system, are grown up are often difficult to prove effective, and must develop the data-domain test instrument that is exclusively used in digital display circuit.Logic analyser is as the universal tester being most widely used in data-domain test instrument, for the exploitation of digital display circuit, the strong instrument that provides is provided.Logic analyser is a kind of instrument of analyzing digitizer hardware and software, has the function of data capture, storage, processing, is one of most important data-domain test instrument.Briefly, logic analyser is exactly catch digital signal and it is shown for the instrument of observing with waveform or data mode.Based on USB(Universal Serial Bus) logic analyser as a kind of virtual instrument, make full use of the power of computing machine, realized the characteristic of plug and play, break through the restriction of traditional instrument at aspects such as data transmission, processing, demonstration and storages, when performance greatly improves, reduced instrument cost.USB interface-based virtual test instrument is a direction of portable testing set development, and therefore developing USB interface-based logic analyser has very large economic benefit and realistic meaning.
Summary of the invention
Technique effect of the present invention can overcome above-mentioned defect, provides a kind of based on USB logic analyser flip flop equipment, and it has improved the portability of analyser.
For achieving the above object, the present invention adopts following technical scheme: it comprises that data channel, time delay module, string modular converter, burr detection module, state sampling module, timing sampling module, frequency division module, clock passage, clock selection module, triggering identification module, storage control module, data memory module, usb circuit, PC main frame and decoding/configuration deposit read write line; Wherein data channel is connected with time delay module, string modular converter respectively, time delay module is connected with burr detection module, state sampling module respectively, string and modular converter be connected with timing sampling module, frequency division module respectively, burr detection module, state sampling module, timing sampling module respectively with data memory module; Frequency division module, clock passage are connected with clock selection module respectively, clock selection module is communicated by letter with timing sampling module, burr detection module, state sampling module, triggering identification module respectively, triggering identification module is connected with state sampling module, timing sampling module, storage control module respectively, storage is controlled mould and is communicated by letter with timing sampling module, data memory module respectively, data memory module is connected with PC main frame by usb circuit, and usb circuit connects decoding/configuration and deposits read write line.
The implication of triggering in logic analyser represents to be controlled and obtained data by the sequence of certain predefined data word, word or event, selects the window of observing system working condition.By have detection and the memory of certain reference point of certain relation to specific data observation starting point, terminal and analyzed data are set, system produces a trigger event, and by corresponding data storage.Relevant to Trigger Function is to follow the tracks of (Trace), is a watch window of opening up in data stream, is used for collecting showing analyzing significant data block, and its position is by triggering decision.Trigger Function is a good and bad important indicator of logic analyser performance judgement.
Accompanying drawing explanation
Fig. 1 is module diagram of the present invention;
Fig. 2 is that start trigger triggers schematic diagram with termination;
Fig. 3 is delayed trigger schematic diagram;
Fig. 4 is that passage triggers schematic diagram;
Fig. 5 is that single channel triggers identification analogous diagram;
Fig. 6 is that single channel triggers identification process figure;
Fig. 7 is external trigger circuit theory diagrams;
Fig. 8 is combination triggering block diagram;
Fig. 9 is that sequence triggers process flow diagram.
Embodiment
As shown in Figure 1, of the present invention based on USB logic analyser flip flop equipment, comprise that data channel, time delay module, string modular converter, burr detection module, state sampling module, timing sampling module, frequency division module, clock passage, clock selection module, triggering identification module, storage control module, data memory module, usb circuit, PC main frame and decoding/configuration deposit read write line; Wherein data channel is connected with time delay module, string modular converter respectively, time delay module is connected with burr detection module, state sampling module respectively, string and modular converter be connected with timing sampling module, frequency division module respectively, burr detection module, state sampling module, timing sampling module respectively with data memory module; Frequency division module, clock passage are connected with clock selection module respectively, clock selection module is communicated by letter with timing sampling module, burr detection module, state sampling module, triggering identification module respectively, triggering identification module is connected with state sampling module, timing sampling module, storage control module respectively, storage is controlled mould and is communicated by letter with timing sampling module, data memory module respectively, data memory module is connected with PC main frame by usb circuit, and usb circuit connects decoding/configuration and deposits read write line.
The Trigger Function that the design's logic analyser module has mainly comprises that the agreements such as edging trigger, pattern triggering, sequence triggering, glitch trigger and I2C trigger.The corresponding identification circuit that triggers detects to judge that to data stream whether trigger condition meets, and provide triggering marking signal.This part circuit designs realization in FPGA.Sample circuit, by the trigger condition comparison of input data and user's setting, is inputted data write store under the control of storage control circuit simultaneously.When triggering identification circuit, recognize while there is set trigger word in input traffic, just output triggers mark pulse.Storage control circuit, after triggering mark pulse is sent, continues to write a certain amount of data, then stops the storage of data.Valid data in storer, after usb circuit is sent into computing machine processing, are observed for user with the form demonstration of waveform or list.
Logic analyser has multiple triggering mode conventionally to meet the application demand of different occasions.The basic Trigger Function that wherein must have is mainly following three kinds of triggerings: start trigger, termination trigger and delayed trigger.
Once referring to recognize to meet to trigger to arrange, start trigger mode just starts immediately the storage of valid data, until be filled with, as shown in the left-half of Fig. 2.
Stopping triggering mode is the storage of advanced row data, just starts to retrieve trigger word after being filled with.After the trigger word that setting detected, stop the storage of data.This triggering mode meets trigger condition data block before for being concerned about, as shown in Fig. 2 right half part
[8].
Delayed trigger refers in input traffic and meets after trigger condition, continues to postpone just carry out the beginning of valid data or stop after some.Delayed trigger is for changing the occasion of relation between tracking and trigger word.The left-half of Fig. 3 is depicted as start trigger and adds delayed mode, and right half part is depicted as to stop triggering and adds delayed mode.
Different according to postponing object in addition, delayed trigger can be divided into following two kinds of modes:
Word postpones to refer to and postpones to as if peek clock is counted, and conventionally comes by aspects such as procedures of observation operation piecemeal and process of measurement working times.
Event delay refer to postpone to as if trigger word, be generally used for analysis cycle, loop nesting program.
The effect that triggers identification circuit is that identification triggers and produce triggering sign.This logic analyser will be realized four kinds of triggering modes such as random triggering, passage triggering, word triggering and external trigger.Various triggering modes are worked independently simultaneously, and triggering selection circuit selects a kind of triggering mode as trigger source, and the triggering of alternate manner output will be left in the basket.We need to record at the position in storer trigger word, so that read valid data (being watch window) from storer.This partial circuit design is pressed difference in functionality sub-module and is realized in FPGA.
In data sampling due to timing analysis, adopt string switch technology, for parallel output clock, be equivalent to a clock sampling to a plurality of data.According to discussion above, during 500MHz sampling, a clock has 8 data, when 200MHz and 100MHz sampling, there are 4 data, other sampling rates are all to only have data, in the situation that 100MHz is above, each system clock effective when arriving, we will judge in several data, whether there are the data that meet trigger condition.For above various situations, we select different modules to go identification to trigger, and have just selected trigger module during the selected sampling rate of user.It is to adopt graphical programming or VHDL hardware description language to programme to realize that each function triggers identification module, the principle of modules is the same, consider article length, I select the situation of 4 representative data, and trigger circuit when namely 200MHz or 100MHz sample illustrate the realization that triggers identification circuit.Below respectively the identification circuit module of each Trigger Function is introduced.
1) trigger at random
Its trigger word is data arbitrarily, and in data stream, any one data is all considered to trigger word, therefore under random triggering mode, trigger marking signal and start with regard to continuously effective from adopting number.
2) passage triggers
When the rising edge that sets or negative edge appear in the signal of chosen passage, produce and trigger, can only select a passage to do trigger source at every turn and trigger, other channel mask.Its theory diagram as shown in Figure 4.
The triggering output of each passage respectively with its mask bit (0: select this passage as trigger port 1: to shield this passage) mutually or after, more all result phases are triggered to sign with drawing total passage.The trigger module of single passage is write as with VHDL.With regard to passage rising edge, trigger to describe the principle of work that passage triggers below, first 4 parallel output data are formed to 4 bits by the time relationship sampling, after triggering enables, after each system rising edge, clock is along judging whether this 4 figure place is 1 entirely, if whole 1, illustrate and certainly do not have rising edge to arrive.If be not 1 entirely, to be divided into two kinds of situations: 1. between this 4 figure place, do not have 0-1 to change, there is no rising edge, as " 1000 ", for this situation, from next system clock, after each rising edge clock, judge successively whether 4 bit data have 1, have 1 to be rising edge.2. between this 4 figure place, there is 0-1 to change, have rising edge, as " 1001 ", by the way of inquiry, find out the position of this rising edge.Single channel triggering analogous diagram and process flow diagram are as shown in Figure 5 and Figure 6.
Passage triggers analogous diagram as shown in Figure 5, TRDATA3[0]-TRDATA0[0] be 4 parallel datas of 0 passage, TRDATA3[0] be the data of first adopting, TRDATA0[0] be the data of finally adopting.CLK is parallel output clock, and PULS_SEL is for triggering the selection (1: rise 0: decline) on edge, and CLRN is reset signal.TRIGLOCA0[1..0] be in 0 passage, to trigger the position of edge in 4 data.Analogous diagram is presented at trigger data and triggers when " 0100 ", and tr puts 1, and trigger position be " 2 ", shows to trigger identification correctly.
3) external trigger
When the rising edge that sets or negative edge appear in the signal on external trigger passage, produce and trigger, realize circuit as shown in Figure 7.PULS_SEL is that 1 selection external trigger is inputted the in-phase end of EXT_TRIG as the clock of d type flip flop, is that the end of oppisite phase of 0 selection EXT_TRIG is as the clock of d type flip flop.When the rising edge of d type flip flop clock arrives, 1, be latched into TRIG, show triggering for generating.
4) word triggers
Word triggers and is divided into again combination triggering and sequence triggering, and when word triggers, user can set triggering mask word, masks unconcerned passage, and word triggers can establish multistage trigger word, in the design, can establish at most 7 grades.The bit comparison corresponding with trigger word respectively of the data of each passage, output ' 1 ' when identical, different output ' 0 ', the relatively output of all passages and mask bit phase separately or after again with, be exactly the marking signal of primary word triggering.
Combined characters triggers the multistage trigger word referring to arranging and searches for, as long as wherein any one trigger word occurs, just produces and triggers, with the sequence independence that arranges of trigger word.Its implementation is input data and a trigger word comparison at different levels, and then by a plurality of comparative result phases or obtain triggering sign.
It is multistage triggering that sequence word triggers, and the data stream being observed only has by the sequencing of trigger word setting and occurs respective data word, could produce triggering marking signal.
Word triggers and writes with VHDL.For combination, trigger, with 4 data respectively with selecteed trigger word comparisons at different levels, as long as there is identical just a generation of comparative result, trigger sign, in this process, also need to consider the passage of conductively-closed, so data and trigger word be all with mask word phase or after just compare, trigger block diagram as shown in Figure 8.For sequence, trigger, first use data 3(and mask word phase or after, below the same) and first order trigger word (with mask word phase or after, below the same) compare, if result is that 1(is identical), use data 2 and second level trigger word comparison; 0(is different if), use data 2 and the comparison of first order trigger word, the like, until data are identical with n level trigger word.Process flow diagram is as Fig. 9.
Claims (1)
1. one kind based on USB logic analyser flip flop equipment, it is characterized in that, comprise that data channel, time delay module, string modular converter, burr detection module, state sampling module, timing sampling module, frequency division module, clock passage, clock selection module, triggering identification module, storage control module, data memory module, usb circuit, PC main frame and decoding/configuration deposit read write line; Wherein data channel is connected with time delay module, string modular converter respectively, time delay module is connected with burr detection module, state sampling module respectively, string and modular converter be connected with timing sampling module, frequency division module respectively, burr detection module, state sampling module, timing sampling module respectively with data memory module; Frequency division module, clock passage are connected with clock selection module respectively, clock selection module is communicated by letter with timing sampling module, burr detection module, state sampling module, triggering identification module respectively, triggering identification module is connected with state sampling module, timing sampling module, storage control module respectively, storage is controlled mould and is communicated by letter with timing sampling module, data memory module respectively, data memory module is connected with PC main frame by usb circuit, and usb circuit connects decoding/configuration and deposits read write line.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059568A (en) * | 2016-06-21 | 2016-10-26 | 电子科技大学 | Multi-channel logic analyzer synchronization trigger circuit based on calibration |
| CN106991025A (en) * | 2017-04-19 | 2017-07-28 | 成都市宏山科技有限公司 | FVLA based on hardware softening |
| CN107689800A (en) * | 2016-08-03 | 2018-02-13 | 瑞昱半导体股份有限公司 | C-type universal serial bus switching circuit |
| CN111221760A (en) * | 2018-11-23 | 2020-06-02 | 珠海格力电器股份有限公司 | Communication control method and device of I2C bus and storage medium |
| CN112634801A (en) * | 2021-01-08 | 2021-04-09 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059568A (en) * | 2016-06-21 | 2016-10-26 | 电子科技大学 | Multi-channel logic analyzer synchronization trigger circuit based on calibration |
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| CN107689800A (en) * | 2016-08-03 | 2018-02-13 | 瑞昱半导体股份有限公司 | C-type universal serial bus switching circuit |
| CN107689800B (en) * | 2016-08-03 | 2020-12-18 | 瑞昱半导体股份有限公司 | C-type universal serial bus switching circuit |
| CN106991025A (en) * | 2017-04-19 | 2017-07-28 | 成都市宏山科技有限公司 | FVLA based on hardware softening |
| CN111221760A (en) * | 2018-11-23 | 2020-06-02 | 珠海格力电器股份有限公司 | Communication control method and device of I2C bus and storage medium |
| CN112634801A (en) * | 2021-01-08 | 2021-04-09 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
| CN112634801B (en) * | 2021-01-08 | 2022-06-10 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
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Application publication date: 20140219 |