CN111221760A - Communication control method and device of I2C bus and storage medium - Google Patents
Communication control method and device of I2C bus and storage medium Download PDFInfo
- Publication number
- CN111221760A CN111221760A CN201811407093.4A CN201811407093A CN111221760A CN 111221760 A CN111221760 A CN 111221760A CN 201811407093 A CN201811407093 A CN 201811407093A CN 111221760 A CN111221760 A CN 111221760A
- Authority
- CN
- China
- Prior art keywords
- host
- bus
- read
- data bus
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention provides a communication control method, a device and a storage medium of an I2C bus, wherein the method comprises the following steps: when the host and the slave on the I2C bus perform data transmission, detecting the read-write mode of the host; and setting the data bus holding time of the host according to the detected read-write mode of the host. The scheme provided by the invention can delay the time for the master to release the control right of the data bus, so that the slave has more preparation time for taking over the data bus.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a communication control method and apparatus for an I2C bus, and a storage medium.
Background
The I2C (inter-integrated circuit) bus has become an international communications standard that can be implemented on over 100 different ICs and has been licensed by over 60 companies. Through the I2C bus communication, the interface problem encountered in designing digital control circuits such as a microcontroller, an EEPROM, a RAM, an LCD driver and an AD/DA data exchanger is solved. I2C includes two bus lines: a serial data bus (SDA) and a serial clock bus (SCL), both lines being connected to a positive current source through a current source or pull-up resistor, and exhibiting a high state when the bus is idle. I2C is a multi-master multi-slave bus that allows only one of the control buses to be arbitrated and the messages not corrupted when multiple masters attempt to control the buses simultaneously. The master of I2C is used to initialize data and generate a transmission clock, each device on the bus has a unique address, and the master configures and controls the slave through the device address. The I2C bus can operate in 3 modes with serial 8-bit bidirectional data transmission bit rates of up to 100kbit/s in standard mode, 400kbit/s in fast mode, and 3.4Mbit/s in high speed mode.
After each host sends 7-bit address or 8-bit data, the host releases the control right of the data bus, and before the slave takes over the data bus completely, the data bus is pulled high by a pull-up resistor and then pulled low by a receiving device in the period after the 8 th clock falling edge and before the 9 th clock rising edge, namely, a sharp burr is generated on the data bus. If not eliminated, the stability of industrial control products is greatly influenced. To ensure data integrity, a filter on the chip is often used to filter out glitches on the data bus. Even if the number of ICs on the same bus is guaranteed to be controlled to within 400pF by the maximum capacitance of the bus, the communication bit rate gradually decreases as the load capacitance of the bus lines increases.
Disclosure of Invention
The main objective of the present invention is to overcome the above-mentioned drawbacks of the prior art, and to provide a communication control method, device and storage medium for I2C bus, so as to solve the problem of glitch generation on I2C data bus in the prior art.
The invention provides a communication control method of an I2C bus, which comprises the following steps: when the host and the slave on the I2C bus perform data transmission, detecting the read-write mode of the host; and setting the data bus holding time of the host according to the detected read-write mode of the host.
Optionally, setting a data bus retention time of the host according to the detected read-write mode of the host, including: and when the data read-write mode of the host is a write mode, setting the data bus holding time of the host as preset time.
Optionally, the preset time is set according to a preparation time for taking over the data bus from the slave; the preset time is greater than the preparation time.
Optionally, setting the data bus holding time of the host to a preset time includes:
and setting the data bus holding time of the host to be the preset time in a control register of the host.
Optionally, detecting the read-write state of the host includes: sampling a clock bus and a data bus of the I2C bus with a processor system clock of the host to determine a start bit of data transfer; and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
In another aspect, the present invention provides a communication control apparatus for an I2C bus, including: the detection unit is used for detecting the read-write mode of the host when the host and the slave on the I2C bus perform data transmission; and the setting unit is used for setting the data bus holding time of the host according to the read-write mode of the host detected by the detection unit.
Optionally, the setting unit, according to the detected read-write mode of the host, sets a data bus retention time of the host, including: and when the data read-write mode of the host is a write mode, setting the data bus holding time of the host as preset time.
Optionally, the preset time is set according to a preparation time for taking over the data bus from the slave; the preset time is greater than the preparation time.
Optionally, the setting unit sets the data bus holding time of the host to a preset time, including: and setting the data bus holding time of the host to be the preset time in a control register of the host.
Optionally, the detecting unit detects a read-write state of the host, including: sampling a clock bus and a data bus of the I2C bus with a processor system clock of the host to determine a start bit of data transfer; and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
A further aspect of the invention provides a storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of any of the methods described above.
According to the technical scheme of the invention, when the host and the slave on the I2C bus perform data transmission, the read-write mode of the host is detected; according to the detected read-write mode of the host, setting the data bus holding time of the host, delaying the time for releasing the control right of the data bus by the sender (host), and enabling the receiver (slave) to have more preparation time for taking over the data bus; starting from the source of burr generated by interaction of the host and the slave, the data corresponding to a specific clock period is processed in a targeted manner, so that the burr is fundamentally solved, the burr of the bus can be eliminated from the source on the basis of not reducing the bit transmission rate of the bus, the burr during the interaction of the host and the slave is eliminated, the filter capacitor on a chip is not relied on, the negative effect of the burr on the bus can be effectively reduced, and the bit transmission rate is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic method diagram of an embodiment of a communication control method of an I2C bus provided by the present invention;
FIG. 2 is a schematic diagram of a master in I2C bus communicating with multiple slaves;
FIG. 3 is a timing diagram of the I2C protocol;
FIG. 4 is a schematic diagram of a glitch generated by the master to slave communication in the I2C bus;
FIG. 5 is a timing diagram of the 8 th clock hold time;
FIG. 6 is a method diagram illustrating an embodiment of a communication control method for an I2C bus according to the present invention;
fig. 7 is a schematic structural diagram of an embodiment of a communication control apparatus of an I2C bus provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 2 is a schematic diagram of communication between a Master (Master) and multiple slaves (Slave) in an I2C bus. Fig. 3 is a timing diagram of the I2C protocol. As shown in fig. 3, when the SCL clock bus is high, the SDA data bus switches from high to low, indicating a Start signal (Start); when the SCL clock bus is high, the SDA data bus changes from low to high, indicating a Stop signal (Stop). Each byte sent on the SDA data bus must be 8 bits, followed by a response bit.
Fig. 4 is a schematic diagram of a glitch generated by the master and slave communications in the I2C bus. As shown in fig. 4, mst _ clk represents the transmission clock, the transmission clock of the I2C bus is generated by the host, slv _ SDA _ oe represents the slave data control line, when slv _ SDA _ oe is high, it represents that the slave controls the bus and pulls the value of the SDA data bus low, when slv _ SDA _ oe is low, it represents that the slave releases the bus, and the value of the SDA data bus is pulled high by the pull-up resistor. The mst _ SDA _ oe represents a host data control line, when the host is used as a transmitter to transmit data, the value of an SDA data bus sampled by an 8 th clock rising edge is low, when the 8 th clock falling edge, the transmitter (host) releases the control right of the data bus, meanwhile, the slave is used as a receiver, when the falling edge of the clock bus is detected, the judgment flow of a response bit is entered, the data control bus of the receiver is changed from low to high, and the control right of the data bus is obtained. If the receiver responds to the transmitter, there is a time difference between the 8 th clock falling edge and the 9 th clock rising edge during half a clock cycle to exchange the control power of the data bus, and the glitch occurs as a result of the data bus being pulled high by the pull-up resistor and then pulled low by the receiver.
The invention provides a communication control method of an I2C bus. The method is used for eliminating the glitch of the I2C bus when the host and the slave interact. The present invention may be used in an appliance, which may include at least one of an air conditioner, a refrigerator, and a washing machine.
The host may specifically be a processor of an electrical appliance, for example, including at least one of a CPU and an MCU. The slave machine can comprise an EEPROM, a DAC and an ADC. An EEPROM (Electrically Erasable Programmable read only memory), a charged Erasable Programmable read only memory, and a memory chip with no data loss after power failure. DAC (digital Analog Converter), digital to Analog Converter, mainly functions to convert data into Analog signals. ADC (Analog to Digital Converter), Analog to Digital Converter, mainly functions to convert Analog signals into Digital signals.
Fig. 1 is a schematic method diagram of an embodiment of a communication control method of an I2C bus provided by the present invention. As shown in fig. 1, according to an embodiment of the present invention, the communication control method of the I2C bus includes at least step S110 and step S120.
Step S110, when the host and the slave on the I2C bus perform data transmission, detecting a read-write mode of the host.
In one embodiment, a clock bus and a data bus of the I2C bus are sampled with a system clock of a processor of the host to determine a start bit of a data transfer; and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
Specifically, when the data bus changes from high to low, if the clock bus is high, the start bit of I2C data transmission can be determined. The communication clock is sampled by the FCLK system clock, and when it is detected that the data bus SDA changes from high to low, if the bus communication clock is high, the start bit of I2C can be determined. Alternatively, the clock bus and data bus of the I2C bus may be sampled with either a rising or falling edge of the system clock.
According to the characteristics of the I2C bus bit-by-bit transmission, in each data transmission, the data read-write mode is detected at the rising edge of the 8 th clock of every 9 clocks. That is, after the start bit of the I2C data transfer, the data bus level of the 8 th clock of the I2C bus clock corresponds to a read/write mode, where a high level is a read mode and a low level is a write mode. After the start bit of the I2C bus data transmission is determined, the read-write bit can be determined according to the start bit, and then the read-write mode of the host is determined according to the level of the data bus of the read-write bit. After the I2C data bus enters the starting state (start bit), counting the number of rising edges of the clock bus through the first counter, and when the number of rising edges of the clock bus counted by the first counter is 8, sampling the level high-low state of the data bus on the 8 th clock, thereby determining the read-write mode of the host.
Step S120, setting the data bus holding time of the host according to the detected read-write mode of the host.
Specifically, when the data read-write mode of the host is the write mode, the data bus holding time of the host is set to be the preset time. More specifically, after the level high-low state of the data bus at the 8 th clock is sampled to determine that the read-write mode of the host is the write mode, the holding time of the data bus is set to be the preset time at the falling edge of the 8 th clock. The preset time is specifically set according to the preparation time for taking over the data bus by the slave; the preset time is greater than the preparation time. The preparation time for taking over the data by the slave can be counted, the preset time is set to be longer than the preparation time, and the host automatically keeps the control right of the data bus for a correspondingly long time on the falling edge of the 8 th clock, so that the purpose of eliminating the burrs is achieved.
Fig. 5 is a timing diagram of the 8 th clock holding time. As shown in fig. 5, tSYNCFor the synchronous time of asynchronous signal synchronization, SCDEL is the data bus hold time after the falling edge of SCL, tHD,DATFor the real hold time acting on the SDA bus, wherein the SCL falling edge detection is the falling edge time of the SCL bus clock (the time is very short and can be ignored when calculating the hold time), the SCL stretched low by the I2C is the hold time set in the present invention, and the SDA output delay is tHD,DATThe true hold time of the data bus after the SCL falling edge.
According to the electrical characteristics of the I2C bus, in the standard mode, the falling time of the clock bus falling edge cannot exceed 300ns, tHD,DATThe hold time of the clock bus is at least 3.45 us. The exchange of control right of the sender and the receiver for controlling the data bus is performed on the falling edge of the clock bus, generally, after the 8 th clock falling edge, the receiver (slave) takes over the data bus immediately, but due to the limitation of the electrical characteristics of the receiver (slave), the receiver cannot take over the data bus with zero delay actually, that is, after the 8 th clock falling edge is generated, the release data bus and the take-over data bus of the two devices are not performed with zero time difference. Delaying transmitter (host) releaseThe time for putting the control right of the data bus can enable the receiver (slave) to have more preparation time for taking over the data bus.
In a specific embodiment, the data bus holding time of the host may be set in a control register of the host, that is, set as the preset time, and according to a clock period value of the system clock and the set holding time, a count size corresponding to the set holding time (preset time) is calculated as a preset number of the second counter, after a falling edge of the 8 th clock, the host continues to hold the control right of the data bus as the transmitter, and the second counter starts counting, counts the number of rising edges of the system clock, and when the number of rising edges of the system clock reaches the preset number, the host releases the data bus.
For clearly illustrating the technical solution of the present invention, the following describes an execution flow of the communication control method of the I2C bus according to a specific embodiment of the present invention.
Fig. 6 is a schematic method diagram of a communication control method of the I2C bus according to an embodiment of the present invention. As shown in fig. 6, after the I2C data bus enters the start state (start bit), the first counter (in the figure, counter 1) counts the number of rising edges of the clock bus, when the first counter counts that the number of rising edges of the clock bus is 8, the high-low level state of the data bus on the 8 th clock is sampled, the data read-write mode of the host is determined, and if the data read-write mode is low level (write mode), the holding time of the data bus is set as the preset time at the falling edge of the 8 th clock; a first counter for counting the number of rising edges of the clock bus is cleared after being added to 9; if the data bus is at high level on the 8 th clock, i.e. the host has read mode, the first counter is directly incremented to 9 and finally cleared.
The invention also provides a communication control device of the I2C bus. The device is used for eliminating the glitch of the I2C bus when the host computer and the slave computer interact. The device can be used in electric appliances, and the electric appliances can comprise at least one of an air conditioner, a refrigerator and a washing machine. The host may specifically be a processor of an electrical appliance, for example, including at least one of a CPU and an MCU. The slave machine can comprise an EEPROM, a DAC and an ADC.
Fig. 7 is a schematic structural diagram of an embodiment of a communication control apparatus of an I2C bus provided in the present invention. As shown in fig. 7, the communication control apparatus 100 of the I2C bus includes: a detection unit 110 and a setting unit 120.
The detecting unit 110 is configured to detect a read-write mode of the host when the host and the slave on the I2C bus perform data transmission; the setting unit 120 is configured to set a data bus retention time of the host according to the read-write mode of the host detected by the detecting unit.
The detection unit 110 detects a read/write mode of the host when the host and the slave on the I2C bus perform data transmission. In one embodiment, a clock bus and a data bus of the I2C bus are sampled with a system clock of a processor of the host to determine a start bit of a data transfer; and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
Specifically, when the data bus changes from high to low, if the clock bus is high, the start bit of I2C data transmission can be determined. The communication clock is sampled by the FCLK system clock, and when it is detected that the data bus SDA changes from high to low, if the bus communication clock is high, the start bit of I2C can be determined. Alternatively, the clock bus and data bus of the I2C bus may be sampled with either a rising or falling edge of the system clock.
According to the characteristics of the I2C bus bit-by-bit transmission, in each data transmission, the data read-write mode is detected at the rising edge of the 8 th clock of every 9 clocks. That is, after the start bit of the I2C data transfer, the data bus level of the 8 th clock of the I2C bus clock corresponds to a read/write mode, where a high level is a read mode and a low level is a write mode. After the start bit of the I2C bus data transmission is determined, the read-write bit can be determined according to the start bit, and then the read-write mode of the host is determined according to the level of the data bus of the read-write bit. After the I2C data bus enters the starting state (start bit), counting the number of rising edges of the clock bus through the first counter, and when the number of rising edges of the clock bus counted by the first counter is 8, sampling the level high-low state of the data bus on the 8 th clock, thereby determining the read-write mode of the host.
The setting unit 120 sets the data bus holding time of the host according to the read-write mode of the host detected by the detection unit
Specifically, when the data read-write mode of the host is the write mode, the data bus holding time of the host is set to be the preset time. More specifically, after the level high-low state of the data bus at the 8 th clock is sampled to determine that the read-write mode of the host is the write mode, the holding time of the data bus is set to be the preset time at the falling edge of the 8 th clock. The preset time is specifically set according to the preparation time for taking over the data bus by the slave; the preset time is greater than the preparation time. The preparation time for taking over the data by the slave can be counted, the preset time is set to be longer than the preparation time, and the host automatically keeps the control right of the data bus for a correspondingly long time on the falling edge of the 8 th clock, so that the purpose of eliminating the burrs is achieved.
Fig. 5 is a timing diagram of the 8 th clock holding time. As shown in fig. 5, tSYNCFor the synchronous time of asynchronous signal synchronization, SCDEL is the data bus hold time after the falling edge of SCL, tHD,DATFor the real hold time acting on the SDA bus, wherein the SCL falling edge detection is the falling edge time of the SCL bus clock (the time is very short and can be ignored when calculating the hold time), the SCL stretched low by the I2C is the hold time set in the present invention, and the SDA output delay is tHD,DATThe true hold time of the data bus after the SCL falling edge.
According to the electrical characteristics of the I2C bus, in the standard mode, the falling time of the clock bus falling edge cannot exceed 300ns, tHD,DATThe hold time of the clock bus is at least 3.45 us. The control right of the data bus is exchanged by the control of the transmitter and the receiver, and the data bus is descended in the clock busThe edge is performed, generally, after the 8 th clock falling edge, the receiver (slave) takes over the data bus immediately, but due to the limitation of the electrical characteristics of the receiver (slave), the receiver cannot actually take over the data bus with zero delay, that is, after the 8 th clock falling edge is generated, the release data bus and the take-over data bus of two devices are not performed with zero time difference. Delaying the time for the sender (master) to release the control of the data bus allows the receiver (slave) more time to prepare for taking over the data bus.
In a specific embodiment, the data bus holding time of the host may be set in a control register of the host, that is, set as the preset time, and according to a clock period value of the system clock and the set holding time, a count size corresponding to the set holding time (preset time) is calculated as a preset number of the second counter, after a falling edge of the 8 th clock, the host continues to hold the control right of the data bus as the transmitter, and the second counter starts counting, counts the number of rising edges of the system clock, and when the number of rising edges of the system clock reaches the preset number, the host releases the data bus.
The invention also provides a storage medium corresponding to the communication control method of the I2C bus, on which a computer program is stored, which program, when being executed by a processor, carries out the steps of any of the methods described above.
Therefore, according to the scheme provided by the invention, when the host and the slave on the I2C bus perform data transmission, the read-write mode of the host is detected; according to the detected read-write mode of the host, setting the data bus holding time of the host, delaying the time for releasing the control right of the data bus by the sender (host), and enabling the receiver (slave) to have more preparation time for taking over the data bus; starting from the source of burr generated by interaction of the host and the slave, the data corresponding to a specific clock period is processed in a targeted manner, so that the burr is fundamentally solved, the burr of the bus can be eliminated from the source on the basis of not reducing the bit transmission rate of the bus, the burr during the interaction of the host and the slave is eliminated, the filter capacitor on a chip is not relied on, the negative effect of the burr on the bus can be effectively reduced, and the bit transmission rate is improved.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or a combination of any of these. In addition, each functional unit may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and the parts serving as the control device may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The above description is only an example of the present invention, and is not intended to limit the present invention, and it is obvious to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (11)
1. A communication control method for an I2C bus, comprising:
when the host and the slave on the I2C bus perform data transmission, detecting the read-write mode of the host;
and setting the data bus holding time of the host according to the detected read-write mode of the host.
2. The method of claim 1, wherein setting a data bus retention time of the host according to the detected read-write mode of the host comprises:
and when the data read-write mode of the host is a write mode, setting the data bus holding time of the host as preset time.
3. The method of claim 2,
the preset time is set according to the preparation time for taking over the data bus from the slave; the preset time is greater than the preparation time.
4. The method of claim 2 or 3, wherein setting the data bus hold time of the host to a preset time comprises:
and setting the data bus holding time of the host to be the preset time in a control register of the host.
5. The method of any of claims 1-4, wherein detecting the read-write status of the host comprises:
sampling a clock bus and a data bus of the I2C bus with a processor system clock of the host to determine a start bit of data transfer;
and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
6. A communication control apparatus of an I2C bus, comprising:
the detection unit is used for detecting the read-write mode of the host when the host and the slave on the I2C bus perform data transmission;
and the setting unit is used for setting the data bus holding time of the host according to the read-write mode of the host detected by the detection unit.
7. The apparatus of claim 6, wherein the setting unit sets the data bus retention time of the host according to the detected read/write mode of the host, and comprises:
and when the data read-write mode of the host is a write mode, setting the data bus holding time of the host as preset time.
8. The apparatus of claim 7,
the preset time is set according to the preparation time for taking over the data bus from the slave; the preset time is greater than the preparation time.
9. The apparatus according to claim 7 or 8, wherein the setting unit sets the data bus holding time of the host to a preset time, and comprises:
and setting the data bus holding time of the host to be the preset time in a control register of the host.
10. The apparatus according to any one of claims 6-9, wherein the detecting unit detects a read/write status of the host, including:
sampling a clock bus and a data bus of the I2C bus with a processor system clock of the host to determine a start bit of data transfer;
and determining a read-write bit of data transmission according to the determined start bit, and determining a read-write mode of the host according to the data bus level of the read-write bit.
11. A storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811407093.4A CN111221760A (en) | 2018-11-23 | 2018-11-23 | Communication control method and device of I2C bus and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811407093.4A CN111221760A (en) | 2018-11-23 | 2018-11-23 | Communication control method and device of I2C bus and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111221760A true CN111221760A (en) | 2020-06-02 |
Family
ID=70830331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811407093.4A Pending CN111221760A (en) | 2018-11-23 | 2018-11-23 | Communication control method and device of I2C bus and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111221760A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117220831A (en) * | 2023-11-02 | 2023-12-12 | 紫光同芯微电子有限公司 | Encoding method for communication bytes, communication method and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078944A (en) * | 2007-05-11 | 2007-11-28 | 东南大学 | Clock switching circuit |
| CN102253910A (en) * | 2010-05-18 | 2011-11-23 | 中兴通讯股份有限公司 | Inter-integrated circuit (I2C) transmission method and device |
| CN102692879A (en) * | 2011-03-25 | 2012-09-26 | 炬力集成电路设计有限公司 | One line control circuit and chip thereof |
| CN103592599A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | USB-based logic analyzer triggering device |
| CN103631314A (en) * | 2012-08-22 | 2014-03-12 | 上海华虹集成电路有限责任公司 | Method for removing noise in level signals |
| CN203522730U (en) * | 2013-10-22 | 2014-04-02 | 赵小丽 | Bus transceiver signal separating circuit |
-
2018
- 2018-11-23 CN CN201811407093.4A patent/CN111221760A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078944A (en) * | 2007-05-11 | 2007-11-28 | 东南大学 | Clock switching circuit |
| CN102253910A (en) * | 2010-05-18 | 2011-11-23 | 中兴通讯股份有限公司 | Inter-integrated circuit (I2C) transmission method and device |
| CN102692879A (en) * | 2011-03-25 | 2012-09-26 | 炬力集成电路设计有限公司 | One line control circuit and chip thereof |
| CN103631314A (en) * | 2012-08-22 | 2014-03-12 | 上海华虹集成电路有限责任公司 | Method for removing noise in level signals |
| CN203522730U (en) * | 2013-10-22 | 2014-04-02 | 赵小丽 | Bus transceiver signal separating circuit |
| CN103592599A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | USB-based logic analyzer triggering device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117220831A (en) * | 2023-11-02 | 2023-12-12 | 紫光同芯微电子有限公司 | Encoding method for communication bytes, communication method and electronic equipment |
| CN117220831B (en) * | 2023-11-02 | 2024-03-01 | 紫光同芯微电子有限公司 | Encoding method for communication bytes, communication method and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1183611B1 (en) | Emulation of a disconnect of a device | |
| US8103896B2 (en) | Method and system for I2C clock generation | |
| EP1950668B1 (en) | Controlling the timing of a state transition of a serial data line in an I2C Controller | |
| WO2011085595A1 (en) | Method and system for controlling inter-integrated circuit bus | |
| CN103095855B (en) | I2C communication interface unit | |
| CN111427831B (en) | Interface implementation method based on power management bus protocol | |
| KR20170110610A (en) | Receive clock calibration for a serial bus | |
| JP2008539499A (en) | Dynamic I2C slave device address decoder | |
| CN110647486B (en) | PCIe link training method, end equipment and communication system | |
| CN111061587A (en) | Communication control method, device, equipment and storage medium of I2C bus | |
| CN107038137B (en) | Hot-plug equipment and method | |
| CN109062850B (en) | Data sending and receiving method of single chip microcomputer | |
| EP2985955B1 (en) | Controller area network (can) device and method for emulating classic can error management | |
| CN103645975A (en) | Abnormality recovery method and serial bus transmission device | |
| Mahat | Design of a 9-bit UART module based on Verilog HDL | |
| US7353300B2 (en) | Apparatus to improve the firmware efficiency for a multiframe serial interface | |
| CN107771331B (en) | Independent UARK BRK detection | |
| CN100480923C (en) | Controller soft realizing method from I2C bus | |
| CN112540943B (en) | Circuit structure and method for preventing I2C interface from waking up SOC system by mistake | |
| CN111881076B (en) | I2C bus hang-up repairing method and device for communication between domestic CPU and BBU | |
| US20150081936A1 (en) | Iic bus start-stop detection circuit | |
| CN111221760A (en) | Communication control method and device of I2C bus and storage medium | |
| TWI741417B (en) | Method and device of real time monitoring the connection status of i2c devices | |
| WO2012171582A1 (en) | Resolving address conflicts in a bus system | |
| CN109739328B (en) | Reset circuit and method of M.3SSD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200602 |