CN106059568A - Multi-channel logic analyzer synchronization trigger circuit based on calibration - Google Patents

Abstract

The invention discloses a multi-channel logic analyzer synchronization trigger circuit based on calibration. The circuit is composed of a plurality of N-channel one-bit multistage sequence trigger circuits, wherein N indicates the number of logic analyzer channels, each N-channel one-bit multistage sequence trigger circuit is configured with a trigger word conversion module, the trigger word conversion module acquires an N-bit trigger word and an N-channel synchronization deviation sequence, and generates a sequenced trigger word for each N-channel one-bit multistage sequence trigger circuit, to control the triggering of the N-channel one-bit multistage sequence trigger circuit. The multi-channel logic analyzer synchronization trigger circuit based on calibration acquires the sequenced trigger word for each channel according to the synchronization deviation, and triggers the channels in sequence, so that influence of the channel synchronization deviation can be amended, the recognition efficiency of the trigger circuit can be improved, and thus the accuracy of data triggering and collection is improved.

Description

Multichannel logic analyser synchronous trigger circuit based on calibration

Technical field

The invention belongs to logic analyser technical field, more specifically, relate to a kind of multichannel based on calibration and patrol Collect analyser synchronous trigger circuit.

Background technology

Logic analyser is used for the observation to data and analysis as data-domain test instrument.Start at logic analyser and adopt After collection process, sampling unit is constantly sent in datastream source source, and then completes to trigger judgement and data storage.Therefore logical analysis The triggering of instrument is not provided only to the capture of the data segment that user is concerned about, trigger signal itself is also that logic analyser will meet simultaneously The data stream of trigger condition carries out the mark stored.If triggering arbitration functions to lose efficacy, then instrument would become hard to accurately from number According to stream captures the waveform needing to analyze, so that instrumental function is had a greatly reduced quality；If simultaneously instrument draws due to self reason Enter deviation, so that do not trigger when data stream meets trigger condition, and produce when data stream is unsatisfactory for trigger condition False triggering, this abnormal analysis result is by the guiding of user error.

The deviation that instrument self reason introduces is in particular in interchannel asynchronous (referred to as synchronism deviation), thus causes Actually originally, the data of alignment, and through instrument channel, sample, trigger and store after the misalignment of data occurs.Existing In technology, obtain the synchronism deviation between each passage generally by calibration electric circuit inspection, then use software according to detection The synchronism deviation obtained is by the data realignment after storage.But this mode is owing to being the place carried out after triggering collection Reason, and triggers judgement and has real-time, triggers the most accurately and judges that guarantee meets the data segment of trigger condition and successfully catches Obtain.For the logic analyser triggering mode of single passage, such as edging trigger, pulsewidth triggering, glitch trigger etc., between multichannel Synchronism deviation has no effect on the judgement of triggering.And during for needing to judge that multiple channel data produces triggering simultaneously, as Pattern triggers and sequence triggers, and interchannel stationary problem just has considerable influence to the judgement triggered.

Pattern triggers and sequence triggers and all has trigger port number and trigger the setting of progression, wherein one-level pattern and one-level sequence It is identical that row trigger determination methods；And the judgement difference that multistage pattern and multistage sequence trigger is, pattern trigger only need multistage In any one-level meet condition and can trigger, sequence triggers then to be needed to judge whether every one-level sets with triggering the most successively Fixed (trigger word and mask word) is consistent, if wherein there being any one-level not correspond, is then unsatisfactory for trigger condition and does not triggers.

Trigger by one-level pattern below and illustrate that the design process of trigger synchronous circuits (will be touched as simplified model as a example by judging Send out port number be set as 8, and sampling followed by carry out under clock trigger judge each passage be 4 bit parallel data).Fig. 1 It is that 11 grade of pattern of 8 passage triggers circuit diagram.As it is shown in figure 1, in 11 grade of pattern of 8 passage triggers circuit (being called for short circuit A), Data chi_data of ch0～ch7 synchronization respectively with trigger word chi_word of path setting with or, identical, export knot Really 1, difference be then 0 (wherein i respective channel number 0～7, lower with).And the effect of mask word chi_sword is whether ignore this Channel data and trigger word with or result, from or the input and output logical relation of door, if mask word chi_sword is 1, then it represents that this passage is shielded, i.e. same or result does not affect triggering and judges.The most also need to judge that the data of 8 passages are the most equal Meet trigger set, will ch0_wtrig～ch7_wtrig signal 8 and output ch_wtrig, if ch_wtrig is 1, Then 1 grade of pattern of 8 passage triggers, and does not triggers.81 grade of sequence of 1, passage trigger circuit and 11 grade of pattern of 8 passages triggers electricity Road is identical, the most distinct in terms of trigger word.

Data after each passage is sampled are actually transferred to multi-bit parallel data by serial data, and data follow synchronization Clock is updated.Fig. 2 is that 4 one-level patterns of 8 passage trigger circuit.As in figure 2 it is shown, 4 one-level patterns of 8 passage trigger circuit (be called for short circuit B), based on circuit A, follows at one and carries out the 8 passage one-level patterns of 4 under synchronised clock simultaneously and trigger. 4 bit data in any T moment are designated as in Fig. 2 T_1, T_2, T_3, T_4 respectively, and wherein the triggering of 4 parts judges the most solely Vertical, the ch_wtrig of any position trigger judge effectively all can to make mutually or after Wtrig_4bit judge effectively.Pass through ch_ simultaneously Wtrig is the concrete place occurred in T_1, T_2, T_3, T_4, thus locks the position that 4 one-level patterns of 8 passage trigger The value of the Wtrig_Local value 0,1,2,3 of Wtrig_Local (T_1, T_2, T_3, the T_4 correspond respectively to).

In like manner 4 multistage patterns of 8 passage trigger circuit then by circuit B based on, be first split as multiple one-level by multistage, often Individual one-level individually carries out triggering judging, each the most multistage Wtrig_4bit phase or obtain 4 multistage patterns of 8 passage and trigger Triggering decision circuitry.Similarly, based on 84, passage multistage sequences triggering circuit are also by circuit B, first it is split as multistage Multiple one-levels, each one-level individually carries out triggering judging, judges successively then according to trigger progression order, until judging to last One-level.Visible circuit is triggered in N channel K level D position in the prior art, no matter is that pattern triggers or sequence triggers, is all by N 11 grade of pattern of passage triggers what circuit built, say, that it is that N channel K level D position is touched that 11 grade of pattern of N channel triggers circuit The unit triggers circuit of Power Generation Road, N channel K level D position is triggered and is comprised 11 grade of pattern triggering circuit of K × D N channel in circuit.

Due to the existence of inter-channel synchronization deviation, pattern and sequence triggering etc. is caused to need the feelings that multiple passages differentiate simultaneously Under condition, triggering circuit recognition efficiency illustrated above is relatively low.

Summary of the invention

It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of multichannel logic analyser based on calibration Synchronous trigger circuit, touches 1 multistage sequence triggering circuit of multichannel as the unit of multichannel Flip-flop Circuit within Digital Logic Analyzer Power Generation Road, obtains the sequence trigger word of each passage, thus revises the impact of Channel Synchronous deviation according to synchronism deviation, improves and touches The recognition efficiency of Power Generation Road, and then improve the accuracy that data-triggered gathers.

For achieving the above object, present invention multichannel logic analyser synchronous trigger circuit based on calibration, if by 1 multistage sequence of N channel of one trigger word modular converter of dry configuration triggers circuit and builds, and N represents logic analyser passage Number；

Trigger word modular converter obtains the trigger word of multichannel logic analyser and arranges the N position trigger word (W that module sends₀, W₁,…,W_N) and the N channel synchronism deviation sequence (Δ of multichannel logic analyser calibration circuit transmission₀,Δ₁,…,Δ_N), wherein W_nRepresent the trigger word of the n-th passage, Δ in N channel unit triggers circuit_nRepresent the synchronization inclined of the n-th passage and reference channel Difference, n=0,2 ..., N-1；Trigger word modular converter is according to synchronism deviation sequence (Δ₀,Δ₁,…,Δ_N) by N position trigger word (W₀,W₁,…,W_N) it being converted into sequence trigger word, 1 the multistage sequence of N channel being sent to correspondence triggers circuit.

Wherein, in trigger word modular converter, the conversion method of trigger word is:

Search synchronism deviation sequence (Δ₀,Δ₁,…,Δ_NThe inclined difference DELTA of smallest synchronization in)_min, calculate Δ '_n=Δ_n- Δ_min, obtain new synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_N), remember synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_N) Middle maximum is M；M level trigger word in sequence trigger wordIn the trigger word of the n-th passageFor:

$w_n^m=\left\{\begin{array}{cc}{W}_n,& {\mathrm{\Δ}}_n^{\′}=m-1\\ X,& {\mathrm{\Δ}}_n^{\′}\≠m-1\end{array}\right.$

Wherein, X represents that trigger word is shielded, m=1,2 ..., M+1.

Present invention multichannel logic analyser trigger synchronous circuits based on calibration, by 1 multistage sequence of several N channel Triggering circuit builds, and N represents that logic analyser port number, 1 multistage sequence of each N channel trigger circuit one trigger word of configuration Modular converter, trigger word modular converter obtains N position trigger word and N channel synchronism deviation sequence, generates each N channel 1 multistage Sequence triggers the sequence trigger word of circuit, to control the triggering of 1 multistage sequence triggering circuit of N channel.The present invention is according to synchronization Deviation obtains the sequence trigger word of each passage, triggers in order, can revise the impact of Channel Synchronous deviation, improves Trigger the recognition efficiency of circuit, and then improve the accuracy that data-triggered gathers.

Accompanying drawing explanation

Fig. 1 is that 11 grade of pattern of 8 passage triggers circuit；

Fig. 2 is that 41 grade of patterns of 8 passage trigger circuit；

Fig. 3 is the structure of a unit triggers circuit in present invention logic analyser synchronous trigger circuit based on calibration Figure；

Fig. 4 is 5 grades of sequence trigger word exemplary plot in the present embodiment.

Detailed description of the invention

Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described, in order to those skilled in the art is preferably Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps When can desalinate the main contents of the present invention, these are described in and will be left in the basket here.

Embodiment

The multichannel logic analyser synchronous trigger circuit based on calibration of the present invention, original with several N channel 1 On the basis of 1 grade, position pattern triggers the multichannel Flip-flop Circuit within Digital Logic Analyzer that circuit builds, 11 grade of pattern of N channel is triggered electricity Road uses 1 multistage sequence of N channel to trigger circuit and is replaced, and is that 1 multistage sequence of each N channel triggers circuit configuration One trigger word modular converter, each Channel Synchronous biased sequence that trigger word modular converter sends according to calibration circuit, will be original The trigger word triggering circuit for 11 grade of pattern of N channel is converted to sequence trigger word, tactile to control 1 multistage sequence of N channel The triggering of Power Generation Road, it is achieved the accurate triggering of data.Obviously, in circuit is triggered in N channel K level D position, K × D N channel 1 is comprised The multistage sequence in position triggers circuit.

Fig. 3 is the structure of a unit triggers circuit in present invention logic analyser synchronous trigger circuit based on calibration Figure.In the present invention, 1 multistage sequence of the N channel of one trigger word modular converter of configuration that unit triggers circuit refers to triggers Circuit.As it is shown on figure 3,1 multistage sequence of each N channel triggers circuit configures a trigger word modular converter, due to N channel 1 multistage sequence triggers circuit and is triggered circuit structure by 11 grade of pattern of N channel, and its operation principle and process belong to known General knowledge, therefore the key modules of the present invention is trigger word modular converter, is described in detail trigger word modular converter below.

Trigger word modular converter obtains the trigger word of multichannel logic analyser and arranges the N position trigger word (W that module sends₀, W₁,…,W_N) and the N channel synchronism deviation sequence (Δ of multichannel logic analyser calibration circuit transmission₀,Δ₁,…,Δ_N), wherein W_nRepresent the trigger word of the n-th passage, Δ in N channel unit triggers circuit_nRepresent the synchronization inclined of the n-th passage and reference channel Difference, n=0,2 ..., N-1.Trigger word modular converter is according to synchronism deviation sequence (Δ₀,Δ₁,…,Δ_N) by N position trigger word (W₀,W₁,…,W_N) it being converted into sequence trigger word, 1 the multistage sequence of N channel being sent to correspondence triggers circuit.

The conversion method of trigger word by: due to calibration circuit used with reference to passage different, then the synchronization obtained Biased sequence (Δ₀,Δ₁,…,Δ_NIn), each synchronism deviation value is probably on the occasion of, it is also possible to negative value, therefore to more convenient Ground builds sequence trigger word, needs synchronism deviation sequence (Δ₀,Δ₁,…,Δ_N) it being converted into nonnegative sequence, its method is: search Rope synchronism deviation sequence (Δ₀,Δ₁,…,Δ_NThe inclined difference DELTA of smallest synchronization in)_min, calculate Δ '_n=Δ_n-Δ_min, obtain new Synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_N).The most now this synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_NIn) Little value is 0, has just obtained a nonnegative sequence.

Note synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_NIn), maximum is M, then in the present invention, sequence trigger word is altogether Meter M+1 level, m level trigger wordIn the trigger word of the n-th passageFor:

$w_n^m=\left\{\begin{array}{cc}{W}_n,& {\mathrm{\Δ}}_n^{\′}=m-1\\ X,& {\mathrm{\Δ}}_n^{\′}\≠m-1\end{array}\right.$

Wherein, m=1,2 ..., M+1；X represents that this trigger word is shielded, namely represent m level the n-th passage touch Send out and judge not affect finally to trigger judged result.

Triggering circuit according to 1 grade, 1 shown in Fig. 1 pattern, in this circuit, trigger word and mask word are separate.Cause This needs trigger word in real processBeing divided into two-way, a road is trigger word, and a road is mask word, i.e. WhenIn 11 grade of pattern of the m level N channel of its correspondence, trigger word chn_word of the n-th passage isCorresponding Mask word chn_sword is 0；WhenTrigger word chn_word of its correspondence is any value of 0,1, corresponding shielding Word chn_sword is 1.

According to above procedure, it is to come really according to synchronism deviation sequence that 1 multistage sequence of N channel triggers the progression of circuit Fixed, say, that to determine that 1 multistage sequence of N channel triggers the progression of circuit according to the result of calibration circuit.So exist In actual application, needing to estimate the non-negative synchronism deviation maximum of multichannel logic analyser, note estimates that non-negative synchronizes Deviation maximum isWhen circuit builds, the progression of 1 multistage sequence triggering circuit of each N channel is configured toSo The progression M+1 required for circuit is triggered afterwards according to 1 multistage sequence of current N channel, fromM+1 level is selected to carry out work in Ji Make, then obviously

1 multistage sequence of the N channel being configured with trigger word modular converter proposed in the present invention triggers circuit as unit Triggering circuit, can build and obtain N channel K level D bit code type triggering circuit and N channel K level D bit sequence triggering circuit, it builds Mode is similar with the construction method of 11 grade of pattern triggering circuit of N channel to prior art, will N channel of the prior art 11 grade of pattern triggers circuit and is replaced i.e. with 1 the multistage sequence triggering circuit of N channel being configured with trigger word modular converter Can, therefore its building mode does not repeats them here.Owing to comprising K × D N channel more than 1 in triggering circuit in N channel K level D position Level pattern triggers circuit, say, that comprises K × D × (M+1) individual N in the present invention in circuit is triggered in N channel K level D position and leads to The 1 grade of pattern in 1, road triggers circuit.

Below as a example by a specific embodiment, the work process of trigger word modular converter in the present invention is carried out specifically Explanation.

Assume the former trigger word of 11 grade of pattern trigger of 8 passages for " 01010010 ", channel sequence is: " CH0～ CH7”.Selector channel 1 is reference channel herein, the synchronism deviation sequence of each passage and passage 1 be (-1,0 ,-1,1 ,-1,1 ,-1, 3).Visible, the inclined difference DELTA of smallest synchronization_min=-1.So conversion after non-negative synchronism deviation sequence be (0,1,0,2,0,2,0, 4), maximum is 4.So sequence trigger word in the present embodiment has 5 grades, can obtain triggering at different levels according to trigger word formula Word.Fig. 4 is 5 grades of sequence trigger word exemplary plot in the present embodiment.Fig. 4 hollow squares represents mask word.As shown in Figure 4, obtain respectively The trigger word of level is:

1st grade of trigger word: " 0X0X0X1X ".

2nd grade of trigger word: " X1XXXXXX ".

3rd level trigger word: " XXX1X0XX ".

4th grade of trigger word: " XXXXXXXX ".

5th grade of trigger word: " XXXXXXX0 ".

Understanding sequentially, wherein CH0, CH2, CH4, CH6 are the first order；CH1 is the second level；CH3 and CH5 is the 3rd Level；CH7 is level V.When being satisfied by sequence triggering for these 5 grades, i.e. it is regarded as meeting the one-level of " 01010010 " trigger condition Pattern triggers.

Understand from the description above, in the present invention, use trigger word modular converter according to each in multichannel logic analyser The synchronism deviation of passage, is converted into N channel 1 by the trigger word of 11 grade of pattern triggering circuit of N channel in prior art multistage Sequence triggers the multistage trigger of circuit, triggers in order, thus revises the impact of Channel Synchronous deviation, improves and triggers The recognition efficiency of circuit, and then improve the accuracy that data-triggered gathers.

Although detailed description of the invention illustrative to the present invention is described above, in order to the technology of the art Personnel understand the present invention, the common skill it should be apparent that the invention is not restricted to the scope of detailed description of the invention, to the art From the point of view of art personnel, as long as various change limits and in the spirit and scope of the present invention that determine in appended claim, these Change is apparent from, and all utilize the innovation and creation of present inventive concept all at the row of protection.

Claims (2)

1. a multichannel logic analyser synchronous trigger circuit based on calibration, by several N channel unit triggers circuit structures Building, N represents logic analyser port number, it is characterised in that described N channel unit triggers circuit is one trigger word conversion of configuration 1 multistage sequence of the N channel of module triggers circuit；

Trigger word modular converter obtains the trigger word of multichannel logic analyser and arranges the N position trigger word (W that module sends₀, W₁,…,W_N) and the N channel synchronism deviation sequence (Δ of multichannel logic analyser calibration circuit transmission₀,Δ₁,…,Δ_N), wherein W_nRepresent the trigger word of the n-th passage, Δ in N channel unit triggers circuit_nRepresent the synchronization inclined of the n-th passage and reference channel Difference, n=0,2 ..., N-1；Trigger word modular converter is according to synchronism deviation sequence (Δ₀,Δ₁,…,Δ_N) by N position trigger word (W₀,W₁,…,W_N) it is converted into sequence trigger word, it is sent to 1 multistage sequence multistage triggering circuit of N channel of correspondence.

Multichannel logic analyser synchronous trigger circuit the most according to claim 1, it is characterised in that described trigger word turns In die change block, the conversion method of trigger word is:

Search synchronism deviation sequence (Δ₀,Δ₁,…,Δ_NThe inclined difference DELTA of smallest synchronization in)_min, calculate Δ '_n=Δ_n-Δ_min, Obtain non-negative synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_N), remember non-negative synchronism deviation sequence (Δ '₀,Δ′₁,…,Δ′_NIn) Maximum is M；M level trigger word in sequence trigger wordIn the trigger word of the n-th passageFor:

$w_n^m=\left\{\begin{array}{cc}{W}_n,& {\mathrm{\Δ}}_n^{\′}=m-1\\ X,& {\mathrm{\Δ}}_n^{\′}\≠m-1\end{array}\right.$

Wherein, X represents that trigger word is shielded, m=1,2 ..., M+1.