CN111722027A - Phase noise data stream processing device and method based on FPGA - Google Patents
Phase noise data stream processing device and method based on FPGA Download PDFInfo
- Publication number
- CN111722027A CN111722027A CN202010610485.1A CN202010610485A CN111722027A CN 111722027 A CN111722027 A CN 111722027A CN 202010610485 A CN202010610485 A CN 202010610485A CN 111722027 A CN111722027 A CN 111722027A
- Authority
- CN
- China
- Prior art keywords
- data
- phase noise
- module
- control module
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012545 processing Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000001914 filtration Methods 0.000 claims abstract description 30
- 238000000605 extraction Methods 0.000 claims abstract description 18
- 238000005070 sampling Methods 0.000 claims abstract description 12
- 238000013500 data storage Methods 0.000 claims description 6
- 238000007726 management method Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 230000003139 buffering effect Effects 0.000 claims description 5
- 238000003672 processing method Methods 0.000 claims description 5
- 238000005111 flow chemistry technique Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 11
- 238000013461 design Methods 0.000 abstract description 3
- 238000001228 spectrum Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000004422 calculation algorithm Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 241000238876 Acari Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012850 discrimination method Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a phase noise data stream processing device and method based on FPGA, the device comprises a data processing module, a clock management module, a control module, a data stream control module and an FFT module; the data processing module comprises a multi-stage extraction filtering unit, and is used for extracting and filtering an input phase noise signal to generate multi-stage phase noise data streams with different sampling rates; the clock management module is used for generating clock signals required by each stage of decimation filtering units; the control module is used for generating reset signals for controlling each stage of decimation filtering units; the data flow control module is used for adjusting the data length and the clock frequency of each stage of phase noise data flow input into the FFT module; the FFT module is used for calculating frequency domain information of each phase noise data stream. The invention realizes the design of extraction filtering and data processing in the FPGA, improves the processing speed of phase noise data, reduces the delay in the data transmission process and the possibility of transmission error, and simultaneously reduces the complexity of the system.
Description
Technical Field
The invention belongs to the technical field of phase noise data processing, and particularly relates to a phase noise data stream processing device and method based on an FPGA.
Background
The phase noise is an important index for describing the frequency stability of the clock signal and has important significance for signal analysis and test. With the rapid development of high and new technologies such as electronic circuit technology, the requirement for measurement accuracy of electronic systems is higher and higher, the demand for high-performance signal generating sources is increased, the indexes of phase noise of high-quality signals are smaller and smaller, and the measurement accuracy and the measurement difficulty are increased. The phase noise plays a significant role in an electronic system, and the stability of equipment is often greatly influenced by the poor phase noise, so that the maintenance cost of the equipment is increased. Phase noise research and testing has become a field of land scarcity in modern technology high lands.
The method for extracting phase noise adopted by the current mainstream phase noise test system is a phase discrimination method, namely, a measured signal and a same-frequency reference local vibration source signal pass through a phase discriminator and a phase-locked loop to convert the phase random fluctuation of the measured signal and the same-frequency reference local vibration source signal into linear output voltage change, when the phase difference between the measured signal and the local vibration source is locked to a 90-degree state by the phase-locked loop, the output of the phase discriminator can be approximately regarded as the phase noise carried by the measured signal, and the obtained phase noise is converted into a data domain and the power spectral density distribution is calculated.
The measured signal is divided into two paths of signals through the power divider, and the two paths of signals are subjected to phase discrimination and transmission through the two paths of channels, so that noise interference on the two paths of signals is independent at random. The two signals are phase noise of the detected signal, the part is related noise, the cross-correlation algorithm has a good suppression effect on irrelevant noise signals, and the same part can be reserved. Conjugate multiplication is carried out on FFT conversion results of the two paths of signals, the conjugate multiplication is equivalent to cross-correlation operation in a mathematical sense, and the result is a phase noise power spectrum and can represent phase noise information of the detected signals.
In order to obtain a phase noise power spectrum close to a carrier frequency with higher resolution and avoid aliasing in the extraction process, multi-stage extraction filtering processing needs to be performed on a digital phase noise signal, and the digital phase noise power spectrum is generally realized by using a CIC + FIR filter. Each stage of the decimation filter realizes 10 times of decimation, the signal sampling rate is reduced step by step, and the FFT result of each stage of signals can obtain the power spectral density with proper resolution.
The existing digital domain processing mode of phase noise adopts FPGA and DSP to process together, as shown in FIG. 1. According to the traditional scheme, data are processed through the FPGA, the DRAM and the DSP, the FPGA achieves extraction and filtering of phase noise data, extraction signals of all levels are generated, the data size is large, and the data must be stored in the DRAM for buffering and can be transmitted to the DSP. The DSP carries out FFT processing on each level of data, then conjugate multiplication is carried out on FFT results, namely cross-correlation processing is carried out, middle process data generated in the middle needs SDRAM buffering, and finally the data of the DSP is transmitted to a computer end for display processing. The traditional scheme has complex data transmission process, low operation speed and difficult realization.
Disclosure of Invention
In view of the above-mentioned deficiencies in the prior art, the present invention provides a phase noise data stream processing device and method based on FPGA, which can save the process of data transmission between FPGA and DSP, thereby increasing the data processing speed.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a phase noise data flow processing device based on FPGA comprises a data processing module, a clock management module, a control module, a data flow control module and an FFT module;
the data processing module comprises a plurality of stages of extraction filtering units, wherein each stage of extraction filtering unit is used for respectively extracting and filtering an input phase noise signal to generate a plurality of stages of phase noise data streams with different sampling rates;
the clock management module is used for generating clock signals required by each stage of decimation filtering units;
the control module is used for generating reset signals for controlling each stage of decimation filtering units according to the control signals;
the data flow control module is used for adjusting the data length and the clock frequency of each level of phase noise data flow generated by the data processing module and input into the FFT module;
the FFT module is used for calculating frequency domain information of each level of phase noise data flow after the data flow control module is synchronized, and outputting FIFO buffer frequency domain data.
Further, the data flow control module sets the clock frequency of the highest frequency band as the working frequency for each stage of phase noise data flow input to the FFT module for processing.
Further, the data flow control module controls the highest frequency band data flow and the clock domain crossing data flow respectively.
Further, the controlling the highest frequency band data stream by the data stream control module specifically includes:
and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.
Further, the controlling the clock domain crossing data stream by the data stream control module specifically includes:
the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.
The invention also provides a phase noise data stream processing method based on the FPGA, which comprises the following steps:
s1, inputting the phase noise signal into a data processing module, and generating multi-level phase noise data streams with different sampling rates through a multi-level decimation filtering unit;
s2, performing working frequency synchronization on each phase noise data stream through a data stream control module;
s3, inputting the synchronized phase noise data streams of all levels into an FFT module to calculate frequency domain signals;
s4, buffering the frequency domain data with FIFO, and outputting the processed data.
Further, in the step S3, the data flow control module is used to set the clock frequency of the highest frequency band as the operating frequency for each stage of phase noise data flow to be input into the FFT module for processing.
Further, in step S3, the data flow control module is used to control the highest frequency band data flow and the cross-clock domain data flow respectively.
Further, the controlling the highest frequency band data stream by using the data stream control module specifically includes:
and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.
Further, the controlling the clock domain crossing data stream by the data stream control module specifically includes:
the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.
The invention has the following beneficial effects:
(1) the invention realizes the design of extraction filtering and data processing in the FPGA, and the signal data is directly calculated in the same FPGA chip, thereby improving the processing speed of phase noise data, reducing the delay in the data transmission process and the possibility of transmission error, and simultaneously reducing the complexity of the system;
(2) the invention has the advantages that the internal resources of the FPGA are reasonable, the maximization of the real-time parallel processing efficiency of the phase noise data is realized, and the minimum resolution of the phase noise power spectrum estimation is reduced to about 0.1 Hz;
(3) the invention modularly divides the phase noise digital processing scheme, each module realizes different functions, and the digital processing of the phase noise is realized.
Drawings
FIG. 1 is a diagram illustrating a digital domain processing method of phase noise in the prior art;
FIG. 2 is a schematic diagram of the structure of the FPGA-based phase noise data stream processing apparatus according to the present invention;
FIG. 3 is a timing diagram illustrating the highest band data flow control in the present invention;
FIG. 4 is a diagram illustrating the operation of an asynchronous ping-pong FIFO according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 2, an embodiment of the present invention provides an FPGA-based phase noise data stream processing apparatus, which includes a data processing module, a clock management module, a control module, a data stream control module, and an FFT module;
the data processing module comprises a plurality of stages of extraction filtering units, wherein each stage of extraction filtering unit is used for respectively extracting and filtering an input phase noise signal to generate a plurality of stages of phase noise data streams with different sampling rates;
the clock management module is used for generating clock signals required by each stage of decimation filtering units;
the control module is used for generating reset signals for controlling each stage of decimation filtering units according to the control signals;
the data flow control module is used for adjusting the data length and the clock frequency of each level of phase noise data flow generated by the data processing module and input into the FFT module;
the FFT module is used for calculating frequency domain information of each level of phase noise data flow after the data flow control module is synchronized, and outputting FIFO buffer frequency domain data.
In the invention, each stage of extraction filtering unit performs conversion equivalent to extraction multiplying power on a data clock, indexes such as data point number, actual data sampling rate and the like are also changed, and relevant information of each stage of data flow generated by algorithm grading processing is shown in table 1.
Table 1 hierarchical process data flow information table
| Number of stages in stages | Clock frequency/Hz | Actual sampling rate/Hz | Analysis Bandwidth/Hz | Number of data points | resolution/Hz |
| Stage 0 | 100M | 10M | 0～5M | 110M | 10K |
| Stage 1 | 10M | 1M | 0～500K | | 1K |
| Stage | |||||
| 2 | |
100K | 0～50K | 1.1M | 100 |
| Stage 3 | 100K | 10K | 0～5K | 110K | 10 |
| |
10K | 1K | 0～500 | 11K | 1 |
| Stage 5 | 1K | 100 | 0～50 | 1.1K | 0.1 |
In table 1, the stage 0 data represents the phase noise data collected by the ADC. The invention utilizes the data processing module to carry out 5-stage extraction filtering altogether, generates 6 sections of phase noise data with different sampling rates, each section of phase noise data corresponds to a section of phase noise power spectrum with different resolutions, and finally, the 6 sections of power spectrum results are synthesized, so that phase noise power spectrum density distribution curves with different resolutions can be obtained at different positions away from the carrier frequency.
The phase noise processing process needs to perform segmented calculation on a plurality of frequency bands, and the number of data points and the data clock of each segment are different, so that the invention adopts different methods to perform segmented calculation.
The phase noise signal that ADC gathered is the highest frequency channel data, and the clock is 100MHz, and the data point is 110M, and the clock of the lowest frequency channel is 1KHz, and the data point is only 1.1K to count, and the data clock of inferior low frequency channel is 10KHz, and the data point is 11K to count. The clocks of each segment of data are different, the clock of each frequency band is 100MHz of a high frequency band at the fastest, and in order to ensure that all data have time and space for processing, the invention utilizes the data flow control module to set the clock frequency of the highest frequency band as the working frequency for inputting each phase noise data stream into the FFT module for processing, so that the working clock of each FFT module is kept under the same clock domain, on the one hand, the input data are processed better, and on the other hand, the running speed of the low frequency band FFT module can be accelerated.
Because the clock of the highest frequency band is faster, but the data volume is more, and the data volume of the other frequency bands is less but the data is not in the same clock domain, the data flow control module is utilized to respectively control the data flow of the highest frequency band and the data flow of the cross-clock domain.
In the FPGA, a certain time is needed for 1K-point FFT operation for a period of data, namely a certain clock beat is needed between input data and output data, the number of high-frequency-range data is large, the data is transmitted from the DDR in sequence, one data is sent to a processing module on each clock rising edge, if no processing is carried out, a part of input data is abandoned by an IP core in the operation process, and thus the problem of data loss is caused.
In the data processing of the highest frequency band, the data is directly processed by FFT algorithm, the speed of single FFT operation is not matched with the transmission speed of the previous path of data, and in order to ensure that the clock of each FFT module keeps synchronization, the invention sets a plurality of FFT module units for data alternate processing.
In order to avoid conflict in the data processing process, each level of phase noise data stream is divided into a plurality of data groups consisting of 1024 data, the data of each data group enters an FFT IP core, and the next data group is input after the signal processing of the IP core is finished.
It was found by simulation that designing 4 FFT IP cores can completely process all the input data sets without missing. Fig. 3 shows a timing diagram of the highest band data flow control. Each line in fig. 3 represents a data valid flag, 1024 clock ticks in length. Four groups of data signals are input into 4 respective FFT IP cores, and real-time processing of the data of the highest frequency band can be realized. The data volume of the highest frequency band is the largest, and the clock frequency is the highest, so the processing speed of the frequency band data becomes a short board of the whole algorithm processing module.
For the rest frequency bands, due to the existence of the decimation filter, the number of data points generated by the frequency bands is less than that of the data of the highest frequency band, and the clock frequency is lower. Therefore, under the condition that the clock frequency of the FFT module is kept at 100MHz, the operation time of the FFT module is enough, so that the processing does not need to adopt a processing architecture of the highest frequency band, the invention adopts an asynchronous ping-pong FIFO processing mode, two FIFOs are used as data storage units, one FIFO writes data and the other FIFO reads data, as shown in FIG. 4.
The input data begins to feed the first set of 1K data points into FIFO1 in the first cycle, after which the full flag of FIFO1 becomes 1, the write enable of FIFO1 is closed, the read enable is opened, and at the same time the write enable of FIFO2 is opened. This operation places FIFO1 in a read state and FIFO2 in a write state, allowing for continuous storage of data. After 1K data points are written into the FIFO2, the full flag of the FIFO2 is set to 1, so that similarly to the previous steps, the write enable of the FIFO2 is turned off, the read enable is turned on, and simultaneously the read enable of the FIFO1 is turned off, and the write enable is turned on, which causes the FIFO2 to be set to the read state and the FIFO1 to be set to the write state, so that the cycle is started and repeated until the data transmission is completed.
The invention adopts asynchronous FIFO, the write clock is the clock frequency of down sampling after each stage of extraction and filtering, and is consistent with the write data, and the read clock is the working clock of FFT and is consistent with the read data. The read clock is faster than the write clock, so in the read state of the two FIFOs, the data in the FIFOs are read only for a period of time, and the FIFOs are set to be in an empty state, so that the input data are continuous and sequentially correspond to each other according to the clock beat, but the output data are output in a segmented manner, and each segment of data is the data read by the FIFOs once.
Based on the phase noise data stream processing device, the invention also provides a phase noise data stream processing method based on the FPGA, which comprises the following steps:
s1, inputting the phase noise signal into a data processing module, and generating multi-level phase noise data streams with different sampling rates through a multi-level decimation filtering unit;
s2, performing working frequency synchronization on each phase noise data stream through a data stream control module;
s3, inputting the synchronized phase noise data streams of all levels into an FFT module to calculate frequency domain signals;
s4, buffering the frequency domain data with FIFO, and outputting the processed data.
In step S3, the present invention sets the highest frequency band clock frequency as the operating frequency for each stage of phase noise data stream input to the FFT module by using the data stream control module, and controls the highest frequency band data stream and the cross-clock domain data stream respectively.
The control of the highest frequency band data stream by using the data stream control module specifically comprises the following steps:
and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and sequentially inputting each data group into the FFT modules for processing.
The control of the clock domain crossing data stream by using the data stream control module specifically comprises the following steps:
the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.
The invention realizes the design of extraction filtering and data processing in the FPGA, and the signal data is directly calculated in the same FPGA chip, thereby improving the processing speed of phase noise data, reducing the delay in the data transmission process and the possibility of transmission error, and simultaneously reducing the complexity of the system. In the design process, the FPGA internal resources are reasonable, the maximization of the real-time parallel processing efficiency of the phase noise data is realized, and the minimum resolution of the phase noise power spectrum estimation is reduced to about 0.1 Hz. Different solutions are proposed for different clock domain processing methods in the phase noise processing module, and the two solutions are applicable to different situations. The invention modularly divides the phase noise digital processing scheme, each module realizes different functions, and has certain guiding significance for the digital processing of the phase noise.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (10)
1. A phase noise data flow processing device based on FPGA is characterized by comprising a data processing module, a clock management module, a control module, a data flow control module and an FFT module;
the data processing module comprises a plurality of stages of extraction filtering units, wherein each stage of extraction filtering unit is used for respectively extracting and filtering an input phase noise signal to generate a plurality of stages of phase noise data streams with different sampling rates;
the clock management module is used for generating clock signals required by each stage of decimation filtering units;
the control module is used for generating reset signals for controlling each stage of decimation filtering units according to the control signals;
the data flow control module is used for adjusting the data length and the clock frequency of each level of phase noise data flow generated by the data processing module and input into the FFT module;
the FFT module is used for calculating frequency domain information of each level of phase noise data flow after the data flow control module is synchronized, and outputting FIFO buffer frequency domain data.
2. The apparatus of claim 1, wherein the data flow control module sets a highest frequency band clock frequency as an operating frequency for each stage of the input FFT module to process the phase noise data flow.
3. The apparatus according to claim 2, wherein the data flow control module controls the highest frequency band data flow and the cross-clock domain data flow respectively.
4. The FPGA-based phase noise data stream processing apparatus of claim 3, wherein the data stream control module specifically controls the highest frequency band data stream as follows:
and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.
5. The apparatus according to claim 3, wherein the data flow control module controls the cross-clock-domain data flow specifically as follows:
the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.
6. A phase noise data stream processing method based on FPGA is characterized by comprising the following steps:
s1, inputting the phase noise signal into a data processing module, and generating multi-level phase noise data streams with different sampling rates through a multi-level decimation filtering unit;
s2, performing working frequency synchronization on each phase noise data stream through a data stream control module;
s3, inputting the synchronized phase noise data streams of all levels into an FFT module to calculate frequency domain signals;
s4, buffering the frequency domain data with FIFO, and outputting the processed data.
7. The method of claim 6, wherein in step S3, the data flow control module is used to set the highest frequency band clock frequency as the operating frequency for each stage of phase noise data flow input to the FFT module.
8. The method according to claim 7, wherein in step S3, the data flow control module is utilized to control the data flow of the highest frequency band and the data flow across clock domains respectively.
9. The method for processing the phase noise data stream based on the FPGA of claim 8, wherein the controlling the highest frequency band data stream by the data stream control module specifically comprises:
and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.
10. The method for processing the phase noise data stream based on the FPGA of claim 8, wherein the controlling the data stream across the clock domain by the data stream control module specifically comprises:
the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010610485.1A CN111722027B (en) | 2020-06-30 | 2020-06-30 | Phase noise data stream processing device and method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010610485.1A CN111722027B (en) | 2020-06-30 | 2020-06-30 | Phase noise data stream processing device and method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111722027A true CN111722027A (en) | 2020-09-29 |
| CN111722027B CN111722027B (en) | 2021-10-08 |
Family
ID=72571973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010610485.1A Expired - Fee Related CN111722027B (en) | 2020-06-30 | 2020-06-30 | Phase noise data stream processing device and method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111722027B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112198428A (en) * | 2020-12-02 | 2021-01-08 | 佛山市联动科技股份有限公司 | Method and system for testing response time of radio frequency switch chip |
| CN113419119A (en) * | 2021-06-02 | 2021-09-21 | 中电科思仪科技股份有限公司 | Parallel phase noise measurement method based on multi-core DSP |
| CN118244019A (en) * | 2024-03-05 | 2024-06-25 | 西安科技大学 | Phase noise analyzer and phase noise analysis method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090244399A1 (en) * | 2008-03-26 | 2009-10-01 | Zoran Corporation | Unified single and multiple carrier receiver architecture |
| CN102768302A (en) * | 2012-07-18 | 2012-11-07 | 北京无线电计量测试研究所 | Double-channel digital phase noise detection device and phase noise detection method |
| CN103733516A (en) * | 2011-06-10 | 2014-04-16 | 技术研究及发展基金公司 | Receiver, transmitter and a method for digital multiple sub-band processing |
| CN105306053A (en) * | 2015-11-05 | 2016-02-03 | 中国电子科技集团公司第四十一研究所 | Digital PLL (Phase-Locked Loop) based phase noise measuring device and method |
| CN107966620A (en) * | 2017-11-21 | 2018-04-27 | 中国电子科技集团公司第四十研究所 | A kind of phase noise measurement device and method of digital frequency discrimination |
| CN107976590A (en) * | 2017-11-21 | 2018-05-01 | 中国电子科技集团公司第四十研究所 | The data processing equipment and method of a kind of phase noise measurement |
-
2020
- 2020-06-30 CN CN202010610485.1A patent/CN111722027B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090244399A1 (en) * | 2008-03-26 | 2009-10-01 | Zoran Corporation | Unified single and multiple carrier receiver architecture |
| CN103733516A (en) * | 2011-06-10 | 2014-04-16 | 技术研究及发展基金公司 | Receiver, transmitter and a method for digital multiple sub-band processing |
| CN102768302A (en) * | 2012-07-18 | 2012-11-07 | 北京无线电计量测试研究所 | Double-channel digital phase noise detection device and phase noise detection method |
| CN105306053A (en) * | 2015-11-05 | 2016-02-03 | 中国电子科技集团公司第四十一研究所 | Digital PLL (Phase-Locked Loop) based phase noise measuring device and method |
| CN107966620A (en) * | 2017-11-21 | 2018-04-27 | 中国电子科技集团公司第四十研究所 | A kind of phase noise measurement device and method of digital frequency discrimination |
| CN107976590A (en) * | 2017-11-21 | 2018-05-01 | 中国电子科技集团公司第四十研究所 | The data processing equipment and method of a kind of phase noise measurement |
Non-Patent Citations (1)
| Title |
|---|
| PATRIK FLEISCHMANN等: "Implementation of a Cross-Spectrum FFT Analyzer for a Phase-Noise Test System in a Low-Cost FPGA", 《INTERNATIONAL JOURNAL OF MICROWAVE SCIENCE AND TECHNOLOGY》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112198428A (en) * | 2020-12-02 | 2021-01-08 | 佛山市联动科技股份有限公司 | Method and system for testing response time of radio frequency switch chip |
| CN113419119A (en) * | 2021-06-02 | 2021-09-21 | 中电科思仪科技股份有限公司 | Parallel phase noise measurement method based on multi-core DSP |
| CN118244019A (en) * | 2024-03-05 | 2024-06-25 | 西安科技大学 | Phase noise analyzer and phase noise analysis method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111722027B (en) | 2021-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111722027B (en) | Phase noise data stream processing device and method based on FPGA | |
| CN103973324B (en) | A kind of wideband digital receiver and real time spectrum processing method thereof | |
| CN111683111B (en) | Interferometry multi-phase channelization baseband conversion system based on GPU | |
| CN106844864A (en) | A kind of multipath clock adjusting method based on phase motor synchronizing technology | |
| CN102868406A (en) | Multichannel high-speed parallel alternate ADC (Analog to Digital Converter) sampling circuit | |
| CN100541385C (en) | The generation device of synchronization frequency division clock and method thereof in the digital television modulator chip | |
| CN104393854B (en) | FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof | |
| CN108710027B (en) | High-precision measurement method for phase difference and amplitude difference between channels | |
| CN111210806A (en) | Low-power-consumption MFCC voice feature extraction circuit based on serial FFT | |
| CN111294089A (en) | Broadband power line carrier communication symbol synchronization method based on FPGA | |
| CN103592881A (en) | Multi-path signal synchronous sampling control circuit based on FPGA | |
| CN109655644B (en) | Method and device for reducing random wave signal output jitter | |
| CN111694027A (en) | Method and device for capturing super-large dynamic spread spectrum signal | |
| CN103018514A (en) | Virtual oscilloscope device based on sound card | |
| CN103676742A (en) | Data reconstitution method based on FPGA | |
| CN111049772B (en) | System and method for realizing 5G signal synchronous processing applied to vector signal analyzer platform | |
| CN107359868A (en) | Pulse density modulated change-over circuit and method | |
| CN109861690A (en) | Export feedback clock duty cycle adjustment device, method and system | |
| CN116701296B (en) | Quantum bit control signal parameterization generation method | |
| CN117040486A (en) | Multi-gear digital filter and broadband digital receiver | |
| CN106130581A (en) | A kind of multiphase filtering wideband digital channel receiver improves system | |
| CN107247183B (en) | Phase measurement system and method | |
| CN110022201A (en) | Bypass attack power consumption profile based on FPGA acquires synchronized clock system | |
| CN1964188B (en) | A draw-off filter device of increment modulation type conversion | |
| CN209526729U (en) | Bypass attack power consumption profile based on FPGA acquires synchronized clock system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20211008 |