CN111722027A - FPGA-based Phase Noise Data Stream Processing Device and Method - Google Patents

Abstract

The invention discloses an FPGA-based phase noise data stream processing device and method. The device includes a data processing module, a clock management module, a control module, a data flow control module and an FFT module; the data processing module includes a multi-stage decimation filtering unit, Extracting and filtering the input phase noise signal to generate multi-level phase noise data streams with different sampling rates; the clock management module is used to generate the clock signal required by the extraction and filtering units at all levels; the control module is used to generate the reset signal that controls the extraction and filtering units at all levels ; The data flow control module is used to adjust the data length and clock frequency input to the FFT module of each level of phase noise data flow; the FFT module is used to calculate the frequency domain information of each level of phase noise data flow. The invention realizes the design of decimation filtering and data processing inside the FPGA, improves the processing speed of the phase noise data, reduces the delay in the data transmission process and the possibility of transmission errors, and also reduces the system complexity.

Description

FPGA-based Phase Noise Data Stream Processing Device and Method

technical field

The invention belongs to the technical field of phase noise data processing, and in particular relates to an FPGA-based phase noise data stream processing device and method.

Background technique

Phase noise is an important indicator to describe the frequency stability of a clock signal, and is of great significance to signal analysis and testing. With the rapid development of high and new technologies such as electronic circuit technology, the measurement accuracy of electronic systems has become higher and higher, and the demand for high-performance signal generators has also increased. Accuracy and measurement difficulty are also increasing. Phase noise plays an important role in electronic systems, and excessive phase noise will often greatly affect the stability of equipment, thereby increasing equipment maintenance costs. Phase noise research and testing has become a field of competition on the high ground of modern technology.

The current mainstream phase noise test system adopts the phase noise extraction method, which means that the measured signal and the reference local oscillator signal of the same frequency pass through a phase detector and a phase-locked loop to convert the random phase fluctuations of the two into The output voltage changes linearly. When the phase difference between the measured signal and the local oscillator source is locked to 90° by the phase-locked loop, the output of the phase detector can be approximately considered as the phase noise carried by the measured signal, and the obtained phase noise Transform to the data domain and compute the power spectral density distribution.

Divide the measured signal into two channels of signals through the power divider, and through the phase detection and transmission of the two channels, the noise interference of the two channels is random and independent. The two signals are the phase noise of the measured signal, and this part is correlated noise. The cross-correlation algorithm has a better suppression effect on uncorrelated noise signals, and the same part can be reserved. The conjugate multiplication of the results of the FFT transformation of the two signals is equivalent to the cross-correlation operation in the mathematical sense, and the result is the phase noise power spectrum, which can characterize the phase noise information of the measured signal.

In order to obtain a higher-resolution phase noise power spectrum close to the carrier frequency without aliasing during the extraction process, it is necessary to perform multi-stage decimation filtering on the digital phase noise signal, which is generally implemented by a CIC+FIR filter. Each stage of the decimation filter realizes 10 times decimation, and reduces the signal sampling rate step by step, and the FFT result of each stage signal can obtain the power spectral density with appropriate resolution.

The existing digital domain processing method of phase noise adopts FPGA and DSP to jointly process, as shown in Figure 1. The data processing of the traditional scheme goes through FPGA, DRAM, DSP, and the FPGA realizes the extraction and filtering of the phase noise data, and generates the extracted signals at all levels. The DSP performs FFT processing on the data at all levels, and then performs conjugate multiplication of the FFT results, that is, cross-correlation processing. The intermediate process data generated in the middle needs SDRAM buffering, and finally the DSP data is transmitted to the computer for display processing. The data transmission process of the traditional scheme is complicated, the operation speed is slow, and it is difficult to implement.

SUMMARY OF THE INVENTION

In view of the above deficiencies in the prior art, the present invention provides an FPGA-based phase noise data stream processing device and method, which can save the process of data transmission in the FPGA and DSP, thereby improving the data processing speed.

In order to achieve the above-mentioned purpose of the invention, the technical scheme adopted in the present invention is:

An FPGA-based phase noise data stream processing device, comprising a data processing module, a clock management module, a control module, a data flow control module and an FFT module;

The data processing module includes a multi-level decimation and filtering unit, and the decimation and filtering units at each level are used to decimate and filter the input phase noise signal respectively to generate multi-level phase noise data streams with different sampling rates;

The clock management module is used to generate clock signals required by the decimation filtering units at all levels;

The control module is used to generate a reset signal for controlling the extraction and filtering units at all levels according to the control signal;

The data flow control module is used to adjust the data length and clock frequency of each phase noise data flow generated by the data processing module and input to the FFT module;

The FFT module is used to calculate the frequency domain information of the phase noise data streams at all levels after synchronization by the data flow control module, and output the FIFO buffered frequency domain data.

Further, the data flow control module sets the clock frequency of the highest frequency band as the operating frequency for inputting the phase noise data flow of each stage to the FFT module for processing.

Further, the data flow control module respectively controls the highest frequency band data flow and the cross-clock domain data flow.

Further, the control of the highest frequency band data flow by the data flow control module is specifically:

Set up multiple FFT modules, divide each level of phase noise data stream into multiple data groups consisting of 1024 data, and input each data group into each FFT module for processing.

Further, the control of the data flow across the clock domain by the data flow control module is specifically:

The asynchronous ping-pong FIFO processing method is adopted, and two FIFOs are used as data storage units. One FIFO writes data and the other FIFO reads data.

The present invention also proposes an FPGA-based phase noise data stream processing method, comprising the following steps:

S1, input the phase noise signal into the data processing module, and generate multi-stage phase noise data streams with different sampling rates through the multi-stage extraction filtering unit;

S2. Synchronize the working frequency of the phase noise data streams at all levels through the data stream control module;

S3. Input the synchronized phase noise data streams at all levels into the FFT module to calculate the frequency domain signal;

S4, using the FIFO to buffer the frequency domain data, and output the processed data.

Further, in the step S3, the data flow control module is used to set the clock frequency of the highest frequency band as the working frequency of each stage of the phase noise data flow input to the FFT module for processing.

Further, in the step S3, the data flow control module is used to control the highest frequency band data flow and the cross-clock domain data flow respectively.

Further, the use of the data flow control module to control the highest frequency band data flow is specifically:

Set up multiple FFT modules, divide each level of phase noise data stream into multiple data groups consisting of 1024 data, and input each data group into each FFT module for processing.

Further, the control of the data flow across the clock domain by the data flow control module is specifically:

The asynchronous ping-pong FIFO processing method is adopted, and two FIFOs are used as data storage units. One FIFO writes data and the other FIFO reads data.

The present invention has the following beneficial effects:

(1) The present invention realizes the design of decimation filtering and data processing inside the FPGA, and the signal data is directly calculated in the same FPGA chip, which improves the processing speed of phase noise data and reduces the delay and occurrence of transmission in the process of data transmission. The possibility of errors, while also reducing the system complexity;

(2) The present invention rationalizes the internal resources of the FPGA, realizes the maximization of the real-time parallel processing efficiency of the phase noise data, and reduces the minimum resolution of the phase noise power spectrum estimation to about 0.1 Hz;

(3) The present invention divides the phase noise digital processing scheme into modules, each module realizes different functions, and realizes the digital processing of phase noise.

Description of drawings

1 is a schematic diagram of a digital domain processing method of phase noise in the prior art;

2 is a schematic structural diagram of an FPGA-based phase noise data stream processing device of the present invention;

Fig. 3 is the highest frequency band data flow control sequence diagram in the present invention;

FIG. 4 is a schematic diagram of an asynchronous ping-pong FIFO operation in the present invention.

Detailed ways

The specific embodiments of the present invention are described below to facilitate those skilled in the art to understand the present invention, but it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes Such changes are obvious within the spirit and scope of the present invention as defined and determined by the appended claims, and all inventions and creations utilizing the inventive concept are within the scope of protection.

As shown in FIG. 2, an embodiment of the present invention provides an FPGA-based phase noise data stream processing device, including a data processing module, a clock management module, a control module, a data flow control module, and an FFT module;

The data processing module includes a multi-level decimation and filtering unit, and the decimation and filtering units at each level are used to decimate and filter the input phase noise signal respectively to generate multi-level phase noise data streams with different sampling rates;

The clock management module is used to generate clock signals required by the decimation filtering units at all levels;

The control module is used to generate a reset signal for controlling the extraction and filtering units at all levels according to the control signal;

The data flow control module is used to adjust the data length and clock frequency of each phase noise data flow generated by the data processing module and input to the FFT module;

The FFT module is used to calculate the frequency domain information of the phase noise data streams at all levels after synchronization by the data flow control module, and output the FIFO buffered frequency domain data.

In the present invention, each level of decimation filtering unit transforms the clock of the data equivalent to the extraction rate, and the indicators such as the number of data points and the actual sampling rate of the data also change. Show.

Table 1. Data flow information table of hierarchical processing process

Grading series clock frequency/Hz Actual sample rate/Hz Analysis bandwidth/Hz number of data points Resolution/Hz Level 0 100M 10M 0～5M 110M 10K Level 1 10M 1M 0～500K 11M 1K Level 2 1M 100K 0～50K 1.1M 100 Level 3 100K 10K 0～5K 110K 10 Level 4 10K 1K 0～500 11K 1 Level 5 1K 100 0～50 1.1K 0.1

In Table 1, level 0 data represents the phase noise data acquired by the ADC. The present invention uses the data processing module to carry out a total of 5 stages of decimation and filtering to generate 6 stages of phase noise data with different sampling rates, each stage of phase noise data corresponds to a stage of phase noise power spectrum with different resolutions, and finally the results of the 6 stages of power spectrum are synthesized. Phase noise power spectral density distribution curves with different resolutions can be obtained at different positions from the carrier frequency.

The phase noise processing process needs to perform segmental calculation on multiple frequency bands, and the data points and data clocks of each segment are different, so the present invention adopts different methods to perform segmental calculation.

The phase noise signal collected by ADC is the highest frequency band data, the clock is 100MHz, the number of data points is 110M, while the clock of the lowest frequency band is 1KHz, the number of data points is only 1.1K points, the data clock of the second low frequency band is 10KHz, the number of data points is 11K point. The clock of each piece of data is different. The fastest clock of each frequency band is 100MHz in the high frequency band. In order to ensure that all data have time and space for processing, the present invention uses the data flow control module to set the clock of the highest frequency band. The frequency of 100MHz is used as the working frequency of each stage of phase noise data stream input to the FFT module, so that the working clock of each FFT module is kept in the same clock domain. Speed up the operation of the low-band FFT module.

Since the clock of the highest frequency band is faster, but the amount of data is large, and the amount of data in the other frequency bands is small but the data is not in the same clock domain, the present invention uses the data flow control module to control the data flow of the highest frequency band and the cross-clock respectively. Domain data flow is controlled.

In FPGA, FFT operation of 1K points takes a certain amount of time, that is, a certain clock beat must pass between input data and output data. On the rising edge of the clock, a data is sent to the processing module. If no processing is done, part of the input data will be discarded by the IP core during the operation, which will cause the problem of missing data.

In the data processing of the highest frequency band, the data is directly subjected to the FFT algorithm, and the speed of a single FFT operation cannot match the transmission speed of the previous data. Alternate processing.

In order to avoid conflicts in the data processing process, the present invention divides each level of phase noise data stream into a plurality of data groups composed of 1024 data, and the data of each data group enters an FFT IP core, and the signal processing of this IP core is completed. Then enter the next data set.

It is found by simulation that designing 4 FFT IP cores can completely process all input data groups without omission. As shown in Figure 3, it is a timing diagram of the highest frequency band data flow control. Each line in Figure 3 represents a data valid flag and is 1024 clock ticks in length. Inputting four sets of data signals into four respective FFT IP cores enables real-time processing of the highest frequency band data. The highest frequency band has the largest amount of data and the highest clock frequency, so the processing speed of the data in this frequency band becomes the short board of the entire algorithm processing module. Through the design of the present invention, the operation speed of the overall system can be significantly improved.

For the remaining frequency bands, due to the existence of the decimation filter, the number of data points generated by these frequency bands is not as large as that of the highest frequency band, and the clock frequency is relatively low. Therefore, when the clock frequency of the FFT module remains 100MHz, the operation time of the FFT is sufficient, so it is not necessary to use the processing architecture of the highest frequency band for processing. The present invention adopts the asynchronous ping-pong FIFO processing method and uses two FIFOs as data storage. Unit, one FIFO writes data while the other FIFO reads data, as shown in Figure 4.

The input data starts to send the first group of 1K data points into FIFO1 in the first cycle. After the transmission, the full flag of FIFO1 becomes 1, the write enable of FIFO1 is turned off, the read enable is turned on, and the FIFO2 is turned on at the same time. Write enable. In this step, FIFO1 is set to read state, and FIFO2 is set to write state, which can realize continuous data storage. After 1K data points are written in FIFO2, the FIFO2 full flag is set to 1, so similar to the previous steps, the write enable of FIFO2 is turned off, the read enable is turned on, and the read enable of FIFO1 is turned off and the write enable is turned on. Yes, this step will put FIFO2 in the read state, and FIFO1 in the write state, so the cycle starts to repeat, until the data transmission is completed.

The invention adopts asynchronous FIFO, the writing clock is the clock frequency of down-sampling after decimation and filtering at all levels, which is consistent with the writing data, and the reading clock is the working clock of the FFT, which is consistent with the reading data. The read clock is faster than the write clock, so in the read state of the two FIFOs, the data in the FIFO is read for a period of time, and the FIFO is set to an empty state, so the input data is continuous, corresponding to the clock beat in turn, but The output data is output in segments, and each segment of data is the data read out by the FIFO at one time.

Based on the above-mentioned phase noise data stream processing device, the present invention also provides an FPGA-based phase noise data stream processing method, comprising the following steps:

S1, input the phase noise signal into the data processing module, and generate multi-stage phase noise data streams with different sampling rates through the multi-stage extraction filtering unit;

S2. Synchronize the working frequency of the phase noise data streams at all levels through the data stream control module;

S3. Input the synchronized phase noise data streams at all levels into the FFT module to calculate the frequency domain signal;

S4, using the FIFO to buffer the frequency domain data, and output the processed data.

In step S3, the present invention uses the data flow control module to set the clock frequency of the highest frequency band as the operating frequency of the input FFT module for each stage of phase noise data flow, and controls the highest frequency band data flow and the cross-clock domain data flow respectively. .

Using the data flow control module to control the highest frequency band data flow is as follows:

Set up multiple FFT modules, divide each level of phase noise data stream into multiple data groups consisting of 1024 data, and sequentially input each data group into the FFT module for processing.

Using the data flow control module to control the cross-clock domain data flow is as follows:

The asynchronous ping-pong FIFO processing method is adopted, and two FIFOs are used as data storage units. One FIFO writes data and the other FIFO reads data.

The invention realizes the design of decimation filtering and data processing in the FPGA, and the signal data is directly calculated in the same FPGA chip, which improves the processing speed of the phase noise data and reduces the delay in the data transmission process and the possibility of transmission errors. It also reduces the complexity of the system. In the design process, the present invention rationalizes the internal resources of the FPGA, maximizes the real-time parallel processing efficiency of the phase noise data, and reduces the minimum resolution of the phase noise power spectrum estimation to about 0.1 Hz. Different solutions are proposed for different clock domain processing methods in the phase noise processing module, and the two solutions are suitable for different situations. The invention divides the phase noise digital processing scheme into modules, each module realizes different functions, and has certain guiding significance for the digital processing of the phase noise.

Those of ordinary skill in the art will appreciate that the embodiments described herein are intended to assist readers in understanding the principles of the present invention, and it should be understood that the scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teachings disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (10)

1. A phase noise data flow processing device based on FPGA is characterized by comprising a data processing module, a clock management module, a control module, a data flow control module and an FFT module;

the data processing module comprises a plurality of stages of extraction filtering units, wherein each stage of extraction filtering unit is used for respectively extracting and filtering an input phase noise signal to generate a plurality of stages of phase noise data streams with different sampling rates;

the clock management module is used for generating clock signals required by each stage of decimation filtering units;

the control module is used for generating reset signals for controlling each stage of decimation filtering units according to the control signals;

the data flow control module is used for adjusting the data length and the clock frequency of each level of phase noise data flow generated by the data processing module and input into the FFT module;

the FFT module is used for calculating frequency domain information of each level of phase noise data flow after the data flow control module is synchronized, and outputting FIFO buffer frequency domain data.

2. The apparatus of claim 1, wherein the data flow control module sets a highest frequency band clock frequency as an operating frequency for each stage of the input FFT module to process the phase noise data flow.

3. The apparatus according to claim 2, wherein the data flow control module controls the highest frequency band data flow and the cross-clock domain data flow respectively.

4. The FPGA-based phase noise data stream processing apparatus of claim 3, wherein the data stream control module specifically controls the highest frequency band data stream as follows:

and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.

5. The apparatus according to claim 3, wherein the data flow control module controls the cross-clock-domain data flow specifically as follows:

the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.

6. A phase noise data stream processing method based on FPGA is characterized by comprising the following steps:

s1, inputting the phase noise signal into a data processing module, and generating multi-level phase noise data streams with different sampling rates through a multi-level decimation filtering unit;

s2, performing working frequency synchronization on each phase noise data stream through a data stream control module;

s3, inputting the synchronized phase noise data streams of all levels into an FFT module to calculate frequency domain signals;

s4, buffering the frequency domain data with FIFO, and outputting the processed data.

7. The method of claim 6, wherein in step S3, the data flow control module is used to set the highest frequency band clock frequency as the operating frequency for each stage of phase noise data flow input to the FFT module.

8. The method according to claim 7, wherein in step S3, the data flow control module is utilized to control the data flow of the highest frequency band and the data flow across clock domains respectively.

9. The method for processing the phase noise data stream based on the FPGA of claim 8, wherein the controlling the highest frequency band data stream by the data stream control module specifically comprises:

and arranging a plurality of FFT modules, dividing each level of phase noise data stream into a plurality of data groups consisting of 1024 data, and inputting each data group into each FFT module for processing.

10. The method for processing the phase noise data stream based on the FPGA of claim 8, wherein the controlling the data stream across the clock domain by the data stream control module specifically comprises:

the asynchronous ping-pong FIFO processing mode is adopted, two FIFOs are used as data storage units, and one FIFO writes data while the other FIFO reads data.

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