CN109581016B

CN109581016B - Random time equivalent sampling system

Info

Publication number: CN109581016B
Application number: CN201811321479.3A
Authority: CN
Inventors: 赵贻玖; 肖双满; 袁熹彬; 付在明; 王厚军
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2018-11-07
Filing date: 2018-11-07
Publication date: 2020-10-16
Anticipated expiration: 2038-11-07
Also published as: CN109581016A

Abstract

The invention discloses a random time equivalent sampling system, which is characterized in that sampling data acquired once is subjected to serial-parallel conversion and then is cached, the time interval between a trigger signal and a first followed channel clock is obtained through measurement, an obtained pulse signal is subjected to broadening and then is measured by a pulse measurement module to obtain a measured value, the initial storage unit serial number of the sampling data is obtained through calculation according to the measured value, then a waveform reconstruction RAM reads the cached data, the read data is subjected to parallel-serial conversion firstly, then the storage unit serial numbers corresponding to the sampling points are calculated according to the initial storage unit serial numbers and equivalent sampling multiples, and the sampling data is stored; and when the batch of the sampling data reaches the equivalent sampling times, outputting the data stored in the waveform reconstruction RAM as equivalent sampling data. Compared with a software implementation mode, the method has the advantages of high data rearrangement efficiency and high waveform recovery speed, so that the waveform refresh rate of the oscilloscope in an equivalent sampling mode is improved.

Description

Random time equivalent sampling system

Technical Field

The invention belongs to the technical field of sampling, and particularly relates to a random time equivalent sampling system.

Background

The digital storage oscilloscope is one of main instruments for testing and analyzing signals, and has wide application in information communication, high-energy physics, medical electronics and other industries. The digital storage oscilloscope mainly works on the principle that a signal conditioning circuit regulates an input signal into the optimal input range of an analog-to-digital converter (ADC), the ADC collects and quantizes an analog input signal, and a Field-Programmable Gate Array (FPGA) controls a memory to access data according to a trigger condition. Due to the limitation of the ADC sampling rate and the Nyquist sampling theorem, the bandwidth of a signal which can be observed by the digital storage oscilloscope in a real-time sampling mode is very limited, and a random equivalent sampling technology is generally required to observe a high-frequency periodic signal.

The current random equivalent sampling technology utilizes FPGA to output random pulses, broadens the pulses through an external circuit, simultaneously caches random sampling data, then utilizes upper computer software to rearrange and combine the random sampling data, and finally recovers and displays waveforms. Fig. 1 is a flow chart of a software reconstruction waveform. As shown in fig. 1, when the waveform is reconstructed by using software, the oscilloscope needs to repeatedly perform start-up acquisition, determine whether acquisition is completed, and read data many times every time the oscilloscope refreshes one waveform software. Due to the limitation of the bus rate and the operation rate of the main controller, particularly under the condition of larger equivalent sampling multiplying power, software needs to spend a large amount of time for waveform reconstruction, so that dead time is longer in an equivalent sampling mode of the oscilloscope, the waveform refresh rate is reduced, the oscilloscope is insensitive to signal change, and the practicability is not strong.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a random time equivalent sampling system, which utilizes an FPGA (field programmable gate array) to reconstruct data and has the characteristics of high data rearrangement efficiency, high waveform recovery speed and the like compared with a software implementation mode, thereby improving the waveform refresh rate of an oscilloscope in an equivalent sampling mode.

In order to achieve the purpose, the random time equivalent sampling system comprises an ADC (analog-to-digital converter) module, a trigger signal generation module, a serial-parallel conversion module, a data cache module, a pulse output module, a pulse widening module, a pulse measurement module, an initial storage unit calculation module, a parallel-serial conversion module and a waveform reconstruction RAM (random access memory), wherein the serial-parallel conversion module, the data cache module, the pulse output module, the pulse measurement module, the initial storage unit calculation module, the parallel-serial conversion module and the waveform reconstruction RAM are realized in an FPGA (field programmable gate array);

the ADC module is used for sampling an input signal, sending the acquired sampling data to the data serial-parallel conversion module, and sending a channel associated clock ADCLK of the sampling data to the data cache module and the pulse output module;

the trigger signal generation module is used for receiving an input signal, comparing the input signal with a preset trigger level, generating a trigger signal TRIG and sending the trigger signal TRIG to the pulse output module;

the serial-parallel conversion module deserializes and reduces the speed of the sampled DATA, and sends M paths of converted DATA to the DATA cache module as parallel sampled DATA DATA, wherein M represents the deserializing and speed reducing multiplying power of the sampled DATA, the value of the deserializing and speed reducing multiplying power is set according to an associated clock ADCLK, and the clock of the parallel sampled DATA DATA is required to be consistent with the associated clock ADCLK;

the DATA caching module receives the parallel sampling DATA DATA and the associated clock ADCLK, caches the parallel sampling DATA DATA under the associated clock ADCLK, generates a trigger enable signal TRIG _ EN during caching and sends the trigger enable signal TRIG _ EN to the pulse output module;

the pulse output module comprises 4 flip-flops D1, D2, D3, D4 and an inverter I, and is used for generating a pulse signal T according to the received associated clock ADCLK, the trigger signal TRIG and the trigger enable signal TRIG _ EN and sending the pulse signal T to the pulse stretching module; the method comprises the steps that a reference voltage Vcc is used as a D end and a set pin of a trigger D1 to be input, a trigger signal TRIG is used as a CP end input of a trigger D1 to be input, a trigger enable signal TRIG _ EN is used as a zero clearing input of a trigger D1, a Q end output signal of a trigger D1 is used as a D end input of a trigger D2 and a CP end input of a trigger D4 to be input, a slave clock ADCLK is used as CP end inputs of triggers D2 and D3, a Q end output signal of the trigger D2 is used as a D end input of a trigger D3, a Q end output signal of the trigger D3 is inverted by an inverter I to be used as a zero clearing input of a trigger D4, the reference voltage Vcc is used as a D end and a set pin of the trigger D4 to be input, and an output signal of a trigger D4 is a pulse signal T;

the pulse stretching module is used for stretching the pulse signal T and sending the stretched pulse signal EXPEND _ T to the pulse measuring module;

the pulse measurement module is used for measuring a pulse signal EXPEND _ T and sending an obtained measurement value count to the initial storage unit calculation module;

the initial storage unit calculation module is used for calculating an initial storage unit serial number S of the sampling data according to the received measured value count and sending the initial storage unit serial number S to the waveform reconstruction RAM; the calculation formula of the initial storage unit number S is as follows:

wherein, count _ T and count _2T respectively represent the measured values of the pulse signals which are correspondingly stretched at 1 sampling interval T and 2 sampling intervals 2T and are measured in advance by the pulse measurement module, and X represents the equivalent sampling multiple;

the method comprises the steps of presetting a storage space with the size of X × N × d in a waveform reconstruction RAM, wherein N represents the number of sampling points of an ADC module in single sampling, d represents the data bit width of each sampling point, dividing the storage space into X × N storage units, sending a sampling data reading instruction to a data cache module and a parallel-serial conversion module after the waveform reconstruction RAM receives the serial number S of an initial storage unit of the sampling data, receiving and storing serial sampling data sent by the parallel-serial conversion module, and storing the serial number A of the storage unit corresponding to the nth sampling point_nThe waveform reconstruction RAM generates a reset signal after the sampling data is stored, and sends the reset signal to the data cache module, the pulse output module, the pulse measurement module, the initial storage unit calculation module and the parallel-serial conversion module to start next acquisition;

and the parallel-serial conversion module is used for reading the parallel sampling DATA DATA of this time from the DATA cache module, performing parallel-serial conversion and then sending the serial sampling DATA to the waveform reconstruction RAM.

The invention relates to a random time equivalent sampling system, which is characterized in that sampling data acquired once is subjected to serial-parallel conversion and sent to a data cache module in an FPGA for caching, a pulse output module measures to obtain a time interval between a trigger signal and a first followed channel clock, the output pulse signal is widened by a pulse widening module and then measured by a pulse measuring module to obtain a measured value, an initial storage unit calculating module calculates to obtain an initial storage unit serial number of the sampling data according to the measured value, then a waveform reconstruction RAM reads data from a data cache module, the read data is subjected to parallel-serial conversion firstly, then storage unit serial numbers corresponding to all sampling points are calculated according to the initial storage unit serial number and an equivalent sampling multiple, and the sampling data is stored; and when the batch of the sampling data reaches the equivalent sampling times, outputting the data stored in the waveform reconstruction RAM as equivalent sampling data. Compared with a software implementation mode, the method has the advantages of high data rearrangement efficiency and high waveform recovery speed, so that the waveform refresh rate of the oscilloscope in an equivalent sampling mode is improved.

Drawings

FIG. 1 is a flow chart of a software reconstruction waveform;

FIG. 2 is a block diagram of one embodiment of a random time equivalent sampling system of the present invention;

FIG. 3 is a block diagram of a pulse output module according to the present invention;

fig. 4 is a schematic diagram of a charge-discharge pulse spreading circuit based on a double-slope capacitor in the present embodiment.

Detailed Description

The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.

Fig. 2 is a block diagram of an embodiment of a random time equivalent sampling system according to the present invention. As shown in fig. 2, the random time equivalent sampling system of the present invention includes an ADC module 1, a trigger signal generation module 2, a serial-to-parallel conversion module 3, a data buffer module 4, a pulse output module 5, a pulse stretching module 6, a pulse measurement module 7, an initial storage unit calculation module 8, a parallel-to-serial conversion module 9, and a waveform reconstruction RAM10, where the serial-to-parallel conversion module 3, the data buffer module 4, the pulse output module 5, the pulse measurement module 7, the initial storage unit calculation module 8, the parallel-to-serial conversion module 9, and the waveform reconstruction RAM10 are implemented in an FPGA, and each module is specifically described below.

The ADC module 1 is configured to sample an input signal, send obtained sampling data to the data serial-to-parallel conversion module 3, and send a channel associated clock ADCLK of the sampling data to the data buffer module 4 and the pulse output module 5.

The trigger signal generating module 2 is configured to receive an input signal, compare the input signal with a preset trigger level, generate a trigger signal TRIG, and send the trigger signal TRIG to the pulse output module 5.

The serial-parallel conversion module 3 performs deserializing and speed reduction on the sampled DATA, and sends the converted M paths of DATA as parallel sampled DATA DATA to the DATA cache module 4. The purpose of serial-parallel conversion is to reduce the speed of the sampled DATA to meet the DATA rate requirement of the FPGA, obviously, the speed of the parallel sampled DATA after speed reduction is 1/M of the original sampled DATA, M represents the deserializing speed reduction multiplying factor of the sampled DATA, the value of M is set according to the associated clock ADCLK, and the clock of the parallel sampled DATA DATA needs to be consistent with the associated clock ADCLK. In fact, the slave clock ADCLK is the working clock of the FPGA.

The DATA buffer module 4 receives the parallel sampling DATA and the associated clock ADCLK, buffers the parallel sampling DATA under the associated clock ADCLK, generates a trigger enable signal TRIG _ EN during buffering, and sends the trigger enable signal TRIG _ EN to the pulse output module 5. During random equivalent sampling, single sampling data is distributed at positions which are equidistant before and after a trigger point, and the generation time of a trigger signal is not fixed, so that the data before and after the trigger point needs to be dynamically cached, and in order to simplify the read-write control flow of cached data, the data caching module 4 is realized based on an asynchronous FIFO inside an FPGA. The generation process of the trigger enable signal TRIG _ EN can be briefly described as follows:

in the data buffer module 4, a counter is provided, which has a size of only half the FIFO capacity and is used to count the data before the trigger signal. When the data buffering starts, the FIFO starts to store data, the counter starts to count, when the data in the FIFO does not reach half, the trigger signal TRIG _ EN is invalid, and at this time, even if the trigger signal is generated, the trigger signal is considered invalid. This is because single sample data is incomplete if the data in the FIFO is less than half capacity. When the counter is full, which means that half of the data in the FIFO is reached, the trigger signal TRIG _ EN is asserted, and the latter trigger signal is an asserted trigger signal, which can be used to control the data buffering. If the trigger signal TRIG _ EN is set to be effective, no trigger signal arrives temporarily, the first half data in the FIFO needs to be dynamically updated, and the data is always kept to be half of the capacity, that is, the first half data is the data before triggering. When the trigger signal comes, the data is continuously written into the storage space at the back half part of the FIFO until the FIFO is full.

The pulse output module 5 comprises 4 flip-flops D1, D2, D3, D4 and an inverter I, and is configured to generate a pulse signal T according to the received slave clock ADCLK, the trigger signal TRIG and the trigger enable signal TRIG _ EN, and send the pulse signal T to the pulse stretching module 6. The design idea of the pulse output module 5 in the invention is as follows:

because the ADC module 1 always works at the highest sampling rate in the equivalent sampling mode, the data output mode of the ADC module 1 is double-edge double-data-rate output, and the data speed reduction module performs four-time speed reduction on the assumption that the highest sampling rate is 1.25 GHz. After the speed reduction processing, the frequency of the associated channel clock is 312.5MHz, the corresponding clock period is 3.2ns, and the time interval delta t between the trigger signal and the first associated channel clock immediately after the trigger signal is in the range of 0-3.2 ns. The key problem of realizing random equivalent sampling is how to accurately measure the time interval delta t between the arrival of a trigger pulse and the first sampling pulse, and the time interval directly determines how to store the acquired data after triggering according to the time sequence, thereby ensuring the correct reconstruction of the waveform. Because delta t is usually below ns level, the pulse widening circuit can accurately measure the pulse signal after being widened by an external circuit, and in order to ensure that the pulse widening circuit outside the FPGA works in a linear region, the widened pulse signal cannot be too narrow, a sampling interval (3.2ns) is superposed on the basis of the original time interval delta t, so that the pulse width of the signal finally sent to the pulse widening circuit is within the range of 3.2-6.4 ns.

Fig. 3 is a structural diagram of a pulse output module in the present invention. As shown in fig. 3, a reference voltage Vcc is input as a D terminal and a set pin of the flip-flop D1, a trigger signal TRIG is input as a CP terminal of the flip-flop D1, a trigger enable signal TRIG _ EN is input as a clear input of the flip-flop D1, a Q terminal output signal of the flip-flop D1 is input as a D terminal of the flip-flop D2 and input as a CP terminal of the flip-flop D4, a slave clock ADCLK is input as CP terminals of the flip-flops D2 and D3, a Q terminal output signal of the flip-flop D2 is input as a D terminal of the flip-flop D3, a Q terminal output signal of the flip-flop D3 is inverted by an I and then input as a clear input of the flip-flop D4, a reference voltage Vcc is input as a D terminal and a set pin of the flip-flop D4, and an output signal of the flip-flop D4 is a pulse signal T.

The specific working process of the pulse output module 5 is as follows: after initial acquisition, output signals of Q ends of the flip-flops D1-D4 are all logic level '0', when the system allows triggering, the output of the TRIG _ EN is high level, the flip-flop D1 is triggered by rising edges, the output level of the flip-flop D1 is changed from '0' to '1', meanwhile, the flip-flop D4 is also triggered by the rising edges, and the output signal, namely the level of the pulse signal T is changed from '0' to '1'; after the flip-flop D1 receives the first trigger edge, the flip-flop D2 detects that the first ADCLK clock edge latches the high level output from the flip-flop D1, and the second ADCLK clock edge latches the high level output from the flip-flop D2 at the flip-flop D3, at which time the flip-flop D4 is cleared, and the pulse signal T output from the flip-flop D4 changes from "1" to "0".

According to the above description, the flip-flops D2 and D3 are used to superimpose a sampling interval on the time interval Δ T, so that the pulse time interval Δ T of the final pulse signal T is between 3.2ns and 6.4 ns.

The pulse stretching module 6 is configured to stretch the pulse signal T, and send the stretched pulse signal EXPEND _ T to the pulse measurement module 7. The specific circuit and the stretching multiple of the pulse stretching module 6 can be set as required, and in this embodiment, the pulse stretching module 6 adopts a pulse stretching circuit based on charging and discharging of a double-slope capacitor. Fig. 4 is a schematic diagram of a charge-discharge pulse spreading circuit based on a double-slope capacitor in the present embodiment. As shown in fig. 4, in the present embodiment, based on the dual-ramp capacitor charge-discharge pulse stretching circuit, when the rising edge of the pulse signal T arrives, the capacitor is charged by the low-current constant current source, and when the falling edge of the pulse arrives, the capacitor is immediately stopped being charged, and simultaneously, the capacitor is charged by the low-current constant current sourceThe charging constant current source is in direct proportion to the low current constant current source to discharge the capacitor, and the voltage of the capacitor is delta U when the capacitor is charged and discharged, namely the charging and discharging time of the capacitor is determined by the current output by the constant current source: Δ T/Δ T ═ I_c/I_fK, wherein I_fFor discharge current, I_cFor charging current, K is the pulse stretching multiple. The stretched pulses can form the time gate of the pulse measuring module 7.

The pulse measurement module 7 is configured to measure the pulse signal EXPEND _ T, and send the obtained measurement value count to the initial storage unit calculation module 7.

The initial storage unit calculation module 7 is configured to calculate an initial storage unit serial number S of the current sampling data according to the received measurement value count, and send the initial storage unit serial number S to the waveform reconstruction RAM 10. The calculation formula of the initial storage unit number S is as follows:

wherein, count _ T and count _2T respectively represent the measured values of the pulse signal after stretching corresponding to 1 sampling interval T and 2 sampling intervals measured in advance by the pulse measurement module 7, and X represents the equivalent sampling multiple. count _2T-count _ T is theoretically equal to count _ T, but due to the presence of non-linear factors in the pulse stretching module, the measurement result is affected, the actual value is different from the theoretical value, and in order to reduce the effect on the calculation result, count _2T-count _ T is still used in the denominator.

A storage space with the size of X × N × d is preset in the waveform reconstruction RAM10, where N represents the number of sampling points of a single sampling of the ADC module 1, and d represents the data bit width of each sampling point, and the storage space is divided into X × N storage units, and obviously, the size of each storage unit is d, the waveform reconstruction RAM10 sends a sampling data reading instruction to the data cache module 4 and the parallel-serial conversion module 9 after receiving the initial storage unit serial number S of the current sampling data, then receives and stores serial sampling data sent by the parallel-serial conversion module 9, and the storage unit serial number a corresponding to the nth sampling point is a serial number a of the storage unit corresponding to the nth sampling point_n＝S+n×X，n＝1,2,…,N。

Because the sampling data of the ADC module 1 is only a part of a complete equivalent sampling, that is, the processing of the waveform reconstruction RAM10 is only partial data each time, in order to obtain a complete equivalent sampling waveform, it is necessary to perform multiple times of acquisition, triggering, buffering, and sorting, that is, to splice together the sampling points at different positions of the repetitive cycle signal waveform, and to recover the original signal. Since sampling is performed for multiple times, other related modules except the waveform reconstruction RAM10 need to be reset every time the sampling is completed, and therefore, after the waveform reconstruction RAM10 finishes storing the sampled data, a reset signal is generated and sent to the data cache module 4, the pulse output module 5, the pulse measurement module 7, the initial storage unit calculation module 7 and the parallel-serial conversion module 9 to be reset, so as to start the next sampling. When the storage frequency of the waveform reconstruction RAM10 reaches the equivalent sampling multiple X, that is, a complete equivalent sampling is completed, and the storage space is full, the data stored in the storage space is output as equivalent sampling data.

The parallel-serial conversion module 9 is configured to read the parallel sample DATA of this time from the DATA buffer module 4, perform parallel-serial conversion, and send the serial sample DATA to the waveform reconstruction RAM 10.

Examples

In order to better explain the technical scheme of the invention, a specific process of the random time equivalent sampling system of the invention is explained in detail by using a specific embodiment.

The present embodiment sets the equivalent sampling magnification to 40. The single-channel highest sampling rate of the ADC module 1 is 1.25GHz, that is, the sampling rate of the ADC module 1 is 1.25GHz, the bit width of data of each sampling point is 8 bits, and the rate of the output slave clock ADCLK is 312.5 MHz. Therefore, the number of ways of the parallel data after the serial-parallel conversion by the serial-parallel conversion module 3 is 4, that is, 1/4 speed reduction is performed, the input data rate of the data cache module 4 is 312.5MHz, and the bit width of the input data is 32 bit. And setting the number of single sampling points to be 64, wherein the data amount stored in the FIFO every time is 16 32-bit data, and the number of the data points corresponds to 64 data points with 8 bits. The FIFO output data rate is determined by the data storage rate of the data reconstruction RAM, and the data bit width is also 32 bits and corresponds to 4 sampling points.

The pulse output module 5 generates a pulse signal T, the pulse stretching module 6 stretches the pulse signal T to obtain a pulse signal EXPEND _ T, and the pulse measurement module 7 sends a measured value count obtained by measurement of the pulse signal T to the initial storage unit calculation module 7. Assume that the measurement value count is 1500.

In order to reduce the error generated when the serial number of the memory cell is calculated each time, pulses corresponding to one clock period (3.2ns) and two clock periods (6.4ns) are input to the pulse measurement module 7 in advance, and count values corresponding to pulse widths of 3.2ns and 6.4ns are obtained by using the pulse measurement module 7, and are respectively recorded as count _3.2ns being 2000 and count _6.4ns being 1000. The initial storage unit calculating module 7 calculates the initial storage unit serial number S after receiving the count value:

in the embodiment, the size of a storage space in a data reconstruction RAM is 4 × 40 × d, a waveform reconstruction RAM10 sends a sampling data reading instruction to a data cache module 4 and a parallel-serial conversion module 9 after receiving an initial storage unit serial number S of sampling data of the time, the FIFO outputs one beat of data, the parallel-serial conversion module 9 divides the data into 4 points and stores the points into the data reconstruction RAM, the data reconstruction RAM obtains the storage unit serial number of the sampling data at the current time in the storage space from the initial storage unit serial number and equivalent multiplying power, and the calculation formula is that A_nS + N × X is 80+ N × 40, N is 1,2, …, N, i.e., the memory cell number is 80,120,160,200,240 … in that order.

It should be noted that: if the starting memory cell number S is calculated to be 120, the memory cell numbers are 120,160,200 … in sequence, that is, although the starting memory cell numbers are different, the memory cells storing data of two times of sampling data are the same except for the first point, and overwriting of data occurs. This is because the pulse signal T is generated by the slave clock ADCLK and the trigger signal, and the slave clock is obtained by slowing down the sampling rate (data rate) of the ADC. In this embodiment, the speed is reduced by 4 times, that is, M in the calculation formula of the starting storage unit serial number is 4, so when the calculated starting storage unit serial number S is 4 values, i.e., 40, 80,120, and 160, the storage units following each group of data are the same, that is, the previous data are overwritten. The research shows that the sampling times are more in the equivalent random time sampling, so that the occurrence of the above conditions does not have substantial influence on the finally obtained equivalent sampling data.

Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.

Claims

1. A random time equivalent sampling system is characterized by comprising an ADC (analog-to-digital converter) module, a trigger signal generation module, a serial-parallel conversion module, a data cache module, a pulse output module, a pulse broadening module, a pulse measurement module, an initial storage unit calculation module, a parallel-serial conversion module and a waveform reconstruction RAM (random access memory), wherein the serial-parallel conversion module, the data cache module, the pulse output module, the pulse measurement module, the initial storage unit calculation module, the parallel-serial conversion module and the waveform reconstruction RAM are realized in an FPGA (field programmable gate array);