CN114384288B - Signal generating device - Google Patents
Signal generating device Download PDFInfo
- Publication number
- CN114384288B CN114384288B CN202210279995.4A CN202210279995A CN114384288B CN 114384288 B CN114384288 B CN 114384288B CN 202210279995 A CN202210279995 A CN 202210279995A CN 114384288 B CN114384288 B CN 114384288B
- Authority
- CN
- China
- Prior art keywords
- waveform sequence
- waveform
- control unit
- unit
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
Abstract
The present invention provides a signal generating device, the device comprising: the system comprises a first-level cache and control unit, a second-level cache and control unit and a digital-to-analog conversion unit; the output end of the first-level cache and control unit is connected with the first input end of the second-level cache and control unit; the first-level cache and control unit is used for caching, reading and waveform conversion processing on the waveform sequence; the second input end of the second-level cache and control unit is used for receiving an external trigger signal; the output end of the second-level cache and control unit is connected with the input end of the digital-to-analog conversion unit; the second-level cache and control unit is used for caching the processed waveform sequence and reading the processed waveform sequence according to the external trigger signal; the digital-to-analog conversion unit is used for converting the waveform sequence from a digital signal to an analog signal. The invention sets the external trigger control logic at the rear through the cascade cache control, eliminates the influence of the preceding stage time on the trigger time delay, realizes the low trigger time delay, and can be applied in the test scene of the transient response.
Description
Technical Field
The invention relates to the technical field of test and measurement, in particular to a signal generating device.
Background
A signal generating device, also known as a signal source, is a device that can provide electrical signals of various frequencies, waveforms and output levels. The signal generating device is used as a signal source or an excitation source for testing when measuring the amplitude characteristic, the frequency characteristic, the transmission characteristic and other electrical parameters of various telecommunication systems or telecommunication equipment, and when measuring the characteristics and parameters of components.
At present, for a signal generating device, an analog radio frequency source for generating a radio frequency signal by using a frequency Synthesizer, a baseband signal generating device realized based on a Direct Digital Synthesizer (DDS) principle, and a signal generating device capable of arbitrarily switching various waveform outputs based on a wave table storage form are mainly used, and the signal generating devices all have an external trigger function. The external trigger function means that the signal generating device can control the actions of signal output, signal closing, signal parameter switching and the like according to an external trigger signal.
The external trigger function is usually realized by directly connecting an external trigger signal to a pin of a Field Programmable Gate Array (FPGA) through an external trigger channel, where the external trigger signal directly participates in a primary control unit after being sampled by the FPGA, but there are also multiple stages of processing units behind the external trigger signal, and processing time of the processing units is directly reflected in a trigger delay parameter, and the trigger delay is long, usually more than 500ns, so that the signal generating device cannot meet the use requirement of a user in some test scenes requiring transient response.
Therefore, the long trigger time delay of the signal generating device is an urgent technical problem to be solved.
Disclosure of Invention
The invention provides a signal generating device, which is used for overcoming the defects that the signal generating device in the prior art has longer trigger time delay and cannot be applied to a test scene of instantaneous response, and realizing the signal generating device with low trigger time delay, which can be applied to the test scene of instantaneous response.
The present invention provides a signal generating device, comprising: the system comprises a first-level cache and control unit, a second-level cache and control unit and a digital-to-analog conversion unit;
the output end of the first-level cache and control unit is connected with the first input end of the second-level cache and control unit; the first-level cache and control unit is used for caching, reading and waveform conversion processing on the waveform sequence transmitted through the upper computer interface to obtain the processed waveform sequence;
a second input end of the second-level cache and control unit is used for receiving an external trigger signal; the output end of the second-level cache and control unit is connected with the input end of the digital-to-analog conversion unit; the second-level cache and control unit is used for caching the processed waveform sequence and reading the processed waveform sequence according to the external trigger signal;
the digital-to-analog conversion unit is used for converting the read processed waveform sequence from a digital signal to an analog signal.
Optionally, the first-level cache and control unit includes: the device comprises a waveform sequence primary cache unit, a waveform sequence parameter storage unit, a primary waveform reading control unit and a waveform sequence processing unit;
the output end of the first-level buffer unit of the waveform sequence is connected with the first input end of the first-level waveform reading control unit; the waveform sequence primary cache unit is used for caching a waveform sequence;
the first output end of the waveform sequence parameter storage unit is connected with the second input end of the first-stage waveform reading control unit; the waveform sequence parameter storage unit is used for storing waveform sequence parameters;
the output end of the first-stage waveform reading control unit is connected with the input end of the waveform sequence processing unit; the first-stage waveform reading control unit is used for reading the waveform sequence according to the waveform sequence parameters;
and the waveform sequence processing unit is used for performing waveform transformation processing on the read waveform sequence to obtain a processed waveform sequence.
Optionally, the second-level cache and control unit includes: the waveform sequence secondary buffer unit and the second-level waveform reading control unit;
the output end of the waveform sequence processing unit is connected with the input end of the waveform sequence secondary cache unit; the output end of the waveform sequence secondary cache unit is connected with the first input end of the second-level waveform reading control unit; the waveform sequence secondary cache unit is used for caching the processed waveform sequence;
the second input end of the second-stage waveform reading control unit is used for receiving an external trigger signal; the second output end of the waveform sequence parameter storage unit is connected with the third input end of the second-stage waveform reading control unit; the output end of the second-stage waveform reading control unit is connected with the input end of the digital-to-analog conversion unit; and the second-stage waveform reading control unit is used for reading the processed waveform sequence according to the waveform sequence parameters and the external trigger signal.
Optionally, the method further comprises: a synchronization unit;
the input end of the synchronization unit is used for receiving an external trigger signal; the output end of the synchronization unit is connected with the input end of the second-level cache and control unit; the synchronization unit is used for synchronizing the clock of the external trigger signal with a system clock.
Optionally, the synchronization unit includes: a first D flip-flop and a second D flip-flop;
the input end of the first D trigger is used for receiving an external trigger signal; the first D trigger is used for sampling the external trigger signal;
the first D trigger and the second D trigger are connected in a cascade mode; the output end of the second D trigger is connected with the second input end of the second-level cache and control unit; the second D flip-flop is used for sampling the output signal of the first D flip-flop.
Optionally, the driving clock of the first D flip-flop and the driving clock of the second D flip-flop are both in the same frequency and phase as the system clock.
Optionally, the waveform sequence parameters include:
a storage base address of the waveform sequence;
the stored length of the waveform sequence.
Optionally, the waveform sequence primary buffer unit is a double-rate synchronous dynamic random access memory.
Optionally, the reading order of the waveform sequence parameters is a storage order of the waveform sequence parameters in the waveform sequence parameter storage unit.
Optionally, the waveform sequence second-level buffer unit is a first-in first-out data buffer.
The signal generating device provided by the invention carries out post-setting on the external trigger control logic through cascade cache control, eliminates the influence of data reading time and intermediate-level waveform transformation processing time on the trigger time delay, realizes low trigger time delay, and can be applied in a test scene of instantaneous response.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating an implementation manner of an external trigger function in the prior art provided by the present invention;
FIG. 2 is a diagram illustrating the definition of trigger delay in the prior art according to the present invention;
FIG. 3 is a schematic diagram of a signal generating device according to the present invention;
FIG. 4 is a second schematic structural diagram of a signal generating device according to the present invention;
FIG. 5 is a third schematic structural diagram of a signal generating device according to the present invention;
FIG. 6 is a fourth schematic structural diagram of a signal generating device according to the present invention;
FIG. 7 is a timing diagram of a synchronization unit in the signal generation apparatus provided by the present invention;
FIG. 8 is a fifth schematic view of the signal generator according to the present invention.
Detailed Description
Fig. 1 is a schematic diagram illustrating an implementation manner of an external trigger function in the prior art, as shown in fig. 1, a waveform storage medium stores a waveform sequence, a waveform sequence table stores waveform sequence parameters, and an external trigger control unit receives an external trigger signal. Firstly, after receiving an external trigger signal, an external trigger control unit reads a waveform sequence from a waveform sequence storage medium according to waveform sequence parameters in a waveform sequence table; then, processing such as gain control, offset control, flatness compensation and the like is carried out on the read waveform sequence; finally, the processed waveform sequence is converted from a Digital signal to an analog signal using a Digital to analog converter (DAC).
Fig. 2 is a schematic diagram illustrating the definition of trigger delay in the prior art, where as shown in fig. 2, the trigger delay is defined as the time difference between the trigger time of the external trigger signal and the waveform output time.
In the prior art, an external trigger signal directly participates in the waveform sequence reading control of a front stage, and because the trigger time delay is related to the trigger time and the waveform output time of the external trigger signal, the processing time of the waveform sequence by a rear stage directly influences the trigger time delay, so that the trigger time is longer, and the use requirements of users cannot be met in some test scenes needing instantaneous response.
In order to overcome the defects that the signal generating device in the prior art has long trigger time delay and cannot be applied to a test scene of instantaneous response, the invention provides the signal generating device.
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Fig. 3 is a schematic structural diagram of a signal generating device provided by the present invention, and as shown in fig. 3, the present invention provides a signal generating device, which includes: the system comprises a first-level cache and control unit, a second-level cache and control unit and a digital-to-analog conversion unit;
the output end of the first-level cache and control unit is connected with the first input end of the second-level cache and control unit; the first-level cache and control unit is used for caching, reading and waveform conversion processing on the waveform sequence transmitted through the upper computer interface to obtain the processed waveform sequence;
the second input end of the second-level cache and control unit is used for receiving an external trigger signal; the output end of the second-level cache and control unit is connected with the input end of the digital-to-analog conversion unit; the second-level cache and control unit is used for caching the processed waveform sequence and reading the processed waveform sequence according to the external trigger signal;
the digital-to-analog conversion unit is used for converting the read processed waveform sequence from a digital signal to an analog signal.
Specifically, the user caches the required waveform sequence to the first-level cache and control unit through the upper computer interface.
The waveform sequence can be a section or a plurality of sections, and the waveform sequences are independent and unrelated. The content of the waveform sequence may be a sine wave, a triangular wave, a rectangular wave, or a user-defined complex waveform.
After the first-level cache and control unit caches the waveform sequence, the first-level cache and control unit also reads the waveform sequence and performs waveform conversion processing on the read waveform sequence, wherein the waveform conversion processing specifically comprises gain control, offset control, in-band flatness compensation and the like, so that the processed waveform sequence is obtained.
Optionally, the first-level cache and control unit includes: the device comprises a waveform sequence primary cache unit, a waveform sequence parameter storage unit, a primary waveform reading control unit and a waveform sequence processing unit;
the output end of the first-level buffer unit of the waveform sequence is connected with the first input end of the first-level waveform reading control unit; the waveform sequence primary buffer unit is used for buffering the waveform sequence;
the first output end of the waveform sequence parameter storage unit is connected with the second input end of the first-stage waveform reading control unit; the waveform sequence parameter storage unit is used for storing waveform sequence parameters;
the output end of the first-stage waveform reading control unit is connected with the input end of the waveform sequence processing unit; the first-stage waveform reading control unit is used for reading a waveform sequence according to the waveform sequence parameters;
and the waveform sequence processing unit is used for performing waveform transformation processing on the read waveform sequence to obtain a processed waveform sequence.
Specifically, fig. 4 is a second schematic structural diagram of the signal generating device provided by the present invention, and as shown in fig. 4, the signal generating device includes a first-level buffer and control unit, a second-level buffer and control unit, and a digital-to-analog conversion unit. The first-level cache and control unit comprises a waveform sequence first-level cache unit, a waveform sequence parameter storage unit, a first-level waveform reading control unit and a waveform sequence processing unit.
The waveform sequence primary buffer unit in the primary buffer and control unit buffers the waveform sequence.
Optionally, the first-level buffer unit of the waveform sequence is a double-rate synchronous dynamic random access memory.
Specifically, a Memory with a large Memory space is required to cache a waveform sequence required by a user, and the waveform sequence primary cache unit may be a storage device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) or a Quad Rate Synchronous Dynamic Random Access Memory (QDR SDRAM).
In the embodiment of the invention, the primary buffer unit of the waveform sequence is DDR SDRAM.
By using DDR SDRAM with larger storage space as the primary buffer unit of the waveform sequence, the method is favorable for buffering a large amount of waveform sequences and improving the waveform output quantity of the signal generating device.
And a waveform sequence parameter storage unit in the first-level cache and control unit stores the waveform sequence parameters.
The waveform sequence parameter storage unit is a cascade of a Block Random Access Memory (Block RAM) and a First In First Out (FIFO) data buffer, a read interface of the Block RAM has a read delay of two beats, and a read interface of the FIFO is zero delay.
Optionally, the waveform sequence parameters include:
a storage base address of the waveform sequence;
the stored length of the waveform sequence.
Specifically, the storage base address of the waveform sequence is a start address at which the waveform sequence is stored, and the storage length of the waveform sequence is an address difference between the start address at which the waveform sequence is stored and an end address at which the waveform sequence is stored.
According to the storage base address of the waveform sequence and the storage length of the waveform sequence, the specified waveform sequence can be read quickly and accurately.
Storing the waveform sequence parameters corresponding to the multiple sections of waveform sequences together to form a waveform sequence parameter table.
Specific parameters contained in the waveform sequence parameters are defined, the storage base address of the waveform sequence and the storage length of the waveform sequence are stored, and the method is favorable for rapidly and accurately reading the specified waveform sequence according to the waveform sequence parameters.
Optionally, the reading order of the waveform sequence parameters is the storage order of the waveform sequence parameters in the waveform sequence parameter storage unit.
Specifically, the waveform sequence parameters are sequentially read according to the storage sequence of the waveform sequence parameters in the waveform sequence parameter storage unit, and the waveform sequence parameters stored in the waveform sequence parameter storage unit are read first, that is, the waveform sequence parameters are read in a manner of storing first and reading first.
And when the waveform sequence parameters stored in the waveform sequence parameter storage unit are completely read, the waveform sequence parameters are read again from the first stored waveform sequence parameter.
The reading mode of storing and reading the waveform sequence parameters first can facilitate the waveform sequence parameter storage unit to adopt a Block RAM-FIFO cascaded structure, thereby shortening the reading time of the waveform sequence parameters and further shortening the reading time of the waveform sequence.
The output end of the first-level buffer unit of the waveform sequence is connected with the first input end of the first-level waveform reading control unit; the first output end of the waveform sequence parameter storage unit is connected with the second input end of the first-level waveform reading control unit, so that the first-level waveform reading control unit can read the corresponding waveform sequence from the first-level buffer unit of the waveform sequence according to the waveform sequence parameters stored in the waveform sequence parameter storage unit.
The output end of the first-stage waveform reading control unit is connected with the input end of the waveform sequence processing unit, and the first-stage waveform reading control unit can input the read waveform sequence into the waveform sequence processing unit.
The waveform sequence processing unit performs waveform conversion processing on the read waveform sequence, wherein the waveform conversion processing specifically comprises gain control, offset control, in-band flatness compensation and the like, so as to obtain a processed waveform sequence.
The waveform sequence is cached first, the waveform sequence parameters are stored, the cached waveform sequence is read according to the waveform sequence parameters, and finally the read waveform sequence is processed, so that the processed waveform sequence is obtained, the caching, reading and waveform change processing of the waveform sequence in the front stage are realized, a foundation is laid for the direct reading of the processed waveform sequence in the rear stage, and the realization of shortening the trigger time delay is further facilitated.
The output end of the first-level cache and control unit is connected with the first input end of the second-level cache and control unit, the first-level cache and control unit inputs the processed waveform sequence into the second-level cache and control unit, and the second-level cache and control unit caches and reads the processed waveform sequence.
Optionally, the second-level cache and control unit includes: the waveform sequence secondary buffer unit and the second-level waveform reading control unit;
the output end of the waveform sequence processing unit is connected with the input end of the waveform sequence secondary cache unit; the output end of the waveform sequence second-level cache unit is connected with the first input end of the second-level waveform reading control unit; the waveform sequence secondary cache unit is used for caching the processed waveform sequence;
the second input end of the second-stage waveform reading control unit is used for receiving an external trigger signal; the second output end of the waveform sequence parameter storage unit is connected with the third input end of the second-stage waveform reading control unit; the output end of the second-stage waveform reading control unit is connected with the input end of the digital-to-analog conversion unit; and the second-stage waveform reading control unit is used for reading the processed waveform sequence according to the waveform sequence parameters and the external trigger signal.
Specifically, as shown in fig. 4, the second level buffer and control unit includes a waveform sequence second level buffer unit and a second level waveform read control unit.
The output end of the waveform sequence processing unit is connected with the input end of the waveform sequence secondary cache unit, the waveform sequence processing unit inputs the processed waveform sequence into the waveform sequence secondary cache unit, and the waveform sequence secondary cache unit caches the processed waveform sequence.
Optionally, the waveform sequence second level buffer unit is a first-in first-out data buffer.
Specifically, a buffer with a fast read function is needed to buffer the processed waveform sequence, so that the processed waveform sequence can be fast read from the waveform sequence secondary buffer unit, and the waveform sequence is immediately output.
The waveform sequence second level buffer unit may be a First In First Out (FIFO) data buffer.
The output end of the waveform sequence secondary cache unit is connected with the first input end of the second-level waveform reading control unit, and the second-level waveform reading control unit can obtain the processed waveform sequence cached in the waveform sequence secondary cache unit.
The second output end of the waveform sequence parameter storage unit is connected with the third input end of the second-stage waveform reading control unit, and the second-stage waveform reading control unit can obtain the waveform sequence parameters stored in the waveform sequence parameter storage unit.
The second input end of the second-level waveform reading control unit is used for receiving an external trigger signal, and the external trigger signal instructs the second-level waveform reading control unit to read the processed waveform sequence from the waveform sequence second-level cache unit.
After receiving the external trigger signal, the second-stage waveform reading control unit firstly reads the waveform sequence parameters from the waveform sequence parameter storage unit, and then reads the corresponding processed waveform sequence from the waveform sequence second-stage cache unit according to the read waveform sequence parameters.
The waveform sequence parameters are sequentially read out from the waveform sequence parameter storage unit in the storage order.
And after the processed waveform sequence is read, waiting for the next external trigger signal until the external trigger signal is received again, and reading the processed waveform sequence again by the second-stage waveform reading control unit.
The processed waveform sequence is cached and then read according to the indication of the external trigger signal, so that the influence of data reading time in a front stage and waveform conversion processing time in a middle stage on trigger time delay is eliminated, low trigger time delay is realized, and the method can be applied to a test scene of instantaneous response.
The output end of the second-stage waveform reading control unit is connected with the input end of the digital-to-analog conversion unit, and the second-stage waveform reading control unit inputs the read processed waveform sequence into the digital-to-analog conversion unit.
The digital-to-analog conversion unit converts the read processed waveform sequence from a digital signal to an analog signal.
By means of cascade cache control, the external trigger control logic is arranged in a post mode, the influence of data reading time and intermediate-level waveform transformation processing time on trigger time delay is eliminated, low trigger time delay is achieved, and the method can be applied to a test scene of instantaneous response.
The clock of the external trigger signal is asynchronous with the system working clock, the metastable state problem exists when the external trigger signal is sampled by directly utilizing the internal working clock of the FPGA, the interval time from the output moment of the external trigger signal to the output moment of the effective waveform signal is not fixed due to the metastable state problem, the error of the system working clock, namely the trigger jitter, usually exists, and the use requirement of the strict fixed trigger time delay cannot be met in some severe fields such as the quantum field.
Therefore, the external trigger clock needs to be synchronized with the system operating clock to reach a fixed trigger delay.
Optionally, the method further comprises: a synchronization unit;
the input end of the synchronization unit is used for receiving an external trigger signal; the output end of the synchronization unit is connected with the input end of the second-level cache and control unit; the synchronization unit is used for synchronizing the clock of the external trigger signal with the system clock.
Specifically, fig. 5 is a third schematic structural diagram of the signal generating device provided by the present invention, and as shown in fig. 5, the signal generating device further includes a synchronizing unit in addition to the first-level buffer and control unit, the second-level buffer and control unit, and the digital-to-analog converting unit.
The input end of the synchronization unit receives an external trigger signal, and the synchronization unit synchronizes the clock of the external trigger signal with the system clock.
The output end of the synchronization unit is connected with the input end of the second-level cache and control unit, and the synchronization unit inputs the synchronized external trigger signal into the second-level cache and control unit.
Optionally, the synchronization unit comprises: a first D flip-flop and a second D flip-flop;
the input end of the first D trigger is used for receiving an external trigger signal; the first D trigger is used for sampling the external trigger signal;
the first D trigger and the second D trigger are connected in a cascade mode; the output end of the second D trigger is connected with the second input end of the second-level cache and control unit; the second D flip-flop is used for sampling the output signal of the first D flip-flop.
Specifically, fig. 6 is a fourth schematic structural diagram of the signal generating device provided by the present invention, and as shown in fig. 6, the synchronizing unit includes a first D flip-flop and a second D flip-flop.
The input end of the first D trigger receives an external trigger signal, and the first D trigger samples the input external trigger signal.
The first D trigger and the second D trigger are connected in a cascade mode, the output end of the first D trigger is connected with the input end of the second D trigger, and the driving clock port of the first D trigger is connected with the driving clock port of the second D trigger. The second D flip-flop samples the output signal of the first D flip-flop.
The output end of the second D trigger is connected with the second input end of the second-level cache and control unit, and the second D trigger inputs the synchronized external trigger signal into the second-level cache and control unit.
Optionally, the driving clock of the first D flip-flop and the driving clock of the second D flip-flop are both in the same frequency and phase as the system clock.
Specifically, the driving clock of the first D flip-flop is a system clock, and the driving clock of the second D flip-flop is also a system clock, so that the driving clock of the first D flip-flop and the driving clock of the second D flip-flop are both in the same frequency and phase as the system clock.
The driving clock of the D trigger and the system clock are in the same frequency and phase, so that the synchronization of the external trigger signal and the system clock is further facilitated.
The first D trigger can generate metastable state when sampling the external trigger signal, the output state during the metastable state is indefinite, therefore, the output signal of the first stage D trigger is continuously synchronized by using the second D trigger, and the output of the second stage D trigger is synchronized with the system clock.
Fig. 7 is a timing chart of the synchronizing unit in the signal generating apparatus according to the present invention, as shown in fig. 7, where 1 denotes a high level and 0 denotes a low level. In the second high level and the second low level of the system clock, the external trigger signal generates a transition to change from low level to high level, but because the D flip-flop is triggered by the rising edge of the clock, the system clock is the falling edge in the phase, the first D flip-flop can not be triggered, and in the second low level of the system clock, the first D flip-flop outputs the previous low level.
In the second low level and the third high level of the system clock, a clock rising edge exists, the first D flip-flop is triggered, and in the third high level of the system clock, the first D flip-flop outputs an external trigger signal with high level. Therefore, the output timing diagram of the first D flip-flop is shown in fig. 7.
And in the third high-level stage of the system clock, the second D flip-flop samples the previous signal output by the first D flip-flop, and the sampling output of the second D flip-flop is low level. Therefore, the output timing diagram of the second D flip-flop is shown in fig. 7.
As can be seen from the timing diagram of the synchronization unit in fig. 7, in the fourth high stage of the system clock, the rising edge of the second D flip-flop is synchronized with the rising edge of the system clock, so that a fixed trigger delay is implemented.
Alternatively, the number of cascaded D flip-flops in the synchronization unit may be two or more.
By adopting a double-D trigger cascade mode and sharing one clock with the clock of the D trigger and the system clock, the whole system is ensured to be in a strict synchronous relation, an external trigger signal after the D trigger is synchronized also has a strict synchronous relation with the system, and the establishment and maintenance time of the clock and data is ensured.
Fig. 8 is a fifth schematic structural diagram of the signal generating device according to the present invention, and as shown in fig. 8, a signal source i and a signal source ii are the same two devices, each signal source includes a first-level buffer and control unit, a second-level buffer and control unit, and a digital-to-analog conversion unit, an output end of the first-level buffer and control unit is connected to a first input end of the second-level buffer and control unit, and an output end of the second-level buffer and control unit is connected to an input end of the digital-to-analog conversion unit.
The output end of the synchronization unit is respectively connected with the second input end of the second-level cache and control unit in the first signal generation device and the second input end of the second cache and control unit in the second signal generation device.
The synchronization unit can simultaneously input the synchronized external trigger signal into the two secondary buffer and control units, thereby generating a multi-channel synchronized waveform sequence.
The synchronized external trigger signals are input into the interfaces of the plurality of signal sources for receiving the external trigger signals, so that the plurality of signal sources have fixed time delay output when outputting signals, and the synchronism of all channels is ensured.
The terms "first," "second," and the like in the embodiments of the present application are used for distinguishing between similar elements and not for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in other sequences than those illustrated or otherwise described herein, and that the terms "first" and "second" used herein generally refer to a class and do not limit the number of objects, for example, a first object can be one or more.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A signal generating device, comprising: the system comprises a first-level cache and control unit, a second-level cache and control unit and a digital-to-analog conversion unit;
the output end of the first-level cache and control unit is connected with the first input end of the second-level cache and control unit; the first-level cache and control unit is used for caching, reading and waveform conversion processing on the waveform sequence transmitted through the upper computer interface to obtain the processed waveform sequence;
the second input end of the second-level cache and control unit is used for receiving an external trigger signal; the output end of the second-level cache and control unit is connected with the input end of the digital-to-analog conversion unit; the second-level cache and control unit is used for caching the processed waveform sequence and reading the processed waveform sequence according to the external trigger signal;
the digital-to-analog conversion unit is used for converting the read processed waveform sequence from a digital signal to an analog signal;
the first-level cache and control unit comprises: the device comprises a waveform sequence primary cache unit, a waveform sequence parameter storage unit, a primary waveform reading control unit and a waveform sequence processing unit;
the output end of the first-level buffer unit of the waveform sequence is connected with the first input end of the first-level waveform reading control unit; the waveform sequence primary cache unit is used for caching a waveform sequence;
the first output end of the waveform sequence parameter storage unit is connected with the second input end of the first-stage waveform reading control unit; the waveform sequence parameter storage unit is used for storing waveform sequence parameters;
the output end of the first-stage waveform reading control unit is connected with the input end of the waveform sequence processing unit; the first-stage waveform reading control unit is used for reading the waveform sequence according to the waveform sequence parameters;
and the waveform sequence processing unit is used for performing waveform transformation processing on the read waveform sequence to obtain a processed waveform sequence.
2. The signal generating apparatus of claim 1, wherein the level two cache and control unit comprises: the waveform sequence secondary buffer unit and the second-level waveform reading control unit;
the output end of the waveform sequence processing unit is connected with the input end of the waveform sequence secondary cache unit; the output end of the waveform sequence secondary cache unit is connected with the first input end of the second-level waveform reading control unit; the waveform sequence secondary cache unit is used for caching the processed waveform sequence;
the second input end of the second-stage waveform reading control unit is used for receiving an external trigger signal; the second output end of the waveform sequence parameter storage unit is connected with the third input end of the second-stage waveform reading control unit; the output end of the second-stage waveform reading control unit is connected with the input end of the digital-to-analog conversion unit; and the second-stage waveform reading control unit is used for reading the processed waveform sequence according to the waveform sequence parameters and the external trigger signal.
3. The signal generating apparatus of claim 1, further comprising: a synchronization unit;
the input end of the synchronization unit is used for receiving an external trigger signal; the output end of the synchronization unit is connected with the input end of the second-level cache and control unit; the synchronization unit is used for synchronizing the clock of the external trigger signal with a system clock.
4. The signal generating apparatus of claim 3, wherein the synchronization unit comprises: a first D flip-flop and a second D flip-flop;
the input end of the first D trigger is used for receiving an external trigger signal; the first D trigger is used for sampling the external trigger signal;
the first D trigger and the second D trigger are connected in a cascade mode; the output end of the second D trigger is connected with the second input end of the second-level cache and control unit; the second D flip-flop is used for sampling the output signal of the first D flip-flop.
5. The signal generating apparatus according to claim 4, wherein the driving clock of the first D flip-flop and the driving clock of the second D flip-flop are in same frequency and phase with the system clock.
6. The signal generating apparatus of claim 1, wherein the waveform sequence parameters comprise:
a storage base address of the waveform sequence;
the stored length of the waveform sequence.
7. The signal generating apparatus of claim 1, wherein the waveform sequence level one buffer unit is a double rate synchronous dynamic random access memory.
8. The signal generation apparatus according to claim 1, wherein the reading order of the waveform sequence parameters is a storage order of the waveform sequence parameters in the waveform sequence parameter storage unit.
9. The signal generating apparatus of claim 2, wherein the waveform sequence second level buffer unit is a first-in-first-out data buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210279995.4A CN114384288B (en) | 2022-03-22 | 2022-03-22 | Signal generating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210279995.4A CN114384288B (en) | 2022-03-22 | 2022-03-22 | Signal generating device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114384288A CN114384288A (en) | 2022-04-22 |
| CN114384288B true CN114384288B (en) | 2022-07-01 |
Family
ID=81204997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210279995.4A Active CN114384288B (en) | 2022-03-22 | 2022-03-22 | Signal generating device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114384288B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102520761A (en) * | 2011-12-20 | 2012-06-27 | 北京航天测控技术有限公司 | Arbitrary waveform generating system based on user-defined processor |
| CN103018512A (en) * | 2011-09-23 | 2013-04-03 | 北京普源精电科技有限公司 | Oscilloscope with external triggering function |
| CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
| CN104079268A (en) * | 2014-06-25 | 2014-10-01 | 东莞中子科学中心 | Method and device for achieving arbitrary waveform occurrence and display of pulse power supply |
| CN104702249A (en) * | 2013-12-10 | 2015-06-10 | 苏州普源精电科技有限公司 | Signal generator with burst synchronization function |
| CN111366898A (en) * | 2020-03-09 | 2020-07-03 | 北京环境特性研究所 | Coherent radar wide pulse waveform generation method and device |
| CN112436824A (en) * | 2020-11-12 | 2021-03-02 | 华中科技大学 | High-stability time sequence signal generation method and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7281025B2 (en) * | 2003-12-18 | 2007-10-09 | Tektronix, Inc. | Triggered DDS pulse generator architecture |
-
2022
- 2022-03-22 CN CN202210279995.4A patent/CN114384288B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103018512A (en) * | 2011-09-23 | 2013-04-03 | 北京普源精电科技有限公司 | Oscilloscope with external triggering function |
| CN102520761A (en) * | 2011-12-20 | 2012-06-27 | 北京航天测控技术有限公司 | Arbitrary waveform generating system based on user-defined processor |
| CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
| CN104702249A (en) * | 2013-12-10 | 2015-06-10 | 苏州普源精电科技有限公司 | Signal generator with burst synchronization function |
| CN104079268A (en) * | 2014-06-25 | 2014-10-01 | 东莞中子科学中心 | Method and device for achieving arbitrary waveform occurrence and display of pulse power supply |
| CN111366898A (en) * | 2020-03-09 | 2020-07-03 | 北京环境特性研究所 | Coherent radar wide pulse waveform generation method and device |
| CN112436824A (en) * | 2020-11-12 | 2021-03-02 | 华中科技大学 | High-stability time sequence signal generation method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114384288A (en) | 2022-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4785415A (en) | Digital data buffer and variable shift register | |
| CN109032498B (en) | Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system | |
| CN112600567B (en) | High-speed multichannel parallel-serial conversion circuit | |
| CN203376745U (en) | Multi-channel radio-frequency signal synchronous acquisition system based on PXIe bus | |
| CN109581016B (en) | Random time equivalent sampling system | |
| CN103018512A (en) | Oscilloscope with external triggering function | |
| CN104297543A (en) | Hybrid oscilloscope with channel synchronization function | |
| CN114384288B (en) | Signal generating device | |
| CN116032252B (en) | Digital-analog interface time sequence control circuit | |
| CN215493781U (en) | Digital oscilloscope supporting extended analog front end | |
| JPH07120505A (en) | Waveform storage device | |
| Huang et al. | Design of portable high-speed oscilloscope analyzer for multifunctional integrated signal testing | |
| CN110765047B (en) | Digital signal control system, FPGA module and method based on instruction set | |
| KR102064232B1 (en) | Apparatus and method for coverting data rate | |
| CN114421963A (en) | Synchronous frequency division circuit | |
| US6633613B1 (en) | Digital circuit for formatting and compressing radar video data | |
| US8154431B2 (en) | Data generator providing large amounts of data of arbitrary word length | |
| CN111756357B (en) | Parameter determination method of periodic signal and electronic equipment | |
| CN113504513B (en) | Time domain nonlinear frequency modulation signal generation method | |
| Yang et al. | Test vector generation for high-speed digital integrated circuits | |
| KR100242692B1 (en) | Input apparatus for pulse code modulation data | |
| JP2003008442A (en) | Digital signal transition splitting method and apparatus | |
| JP3439565B2 (en) | Waveform storage device | |
| Wen et al. | DAC-based 6.4 GSPS High Speed and Dual Channel Signal Generation for AXIe Instrument | |
| JP3429993B2 (en) | Waveform storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |