CN114421963A

CN114421963A - Synchronous frequency division circuit

Info

Publication number: CN114421963A
Application number: CN202111606420.0A
Authority: CN
Inventors: 吴俊杰; 徐宏林; 张�浩
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2021-12-26
Filing date: 2021-12-26
Publication date: 2022-04-29
Anticipated expiration: 2041-12-26
Also published as: CN114421963B

Abstract

With the rapid development of microelectronic technology and communication technology, high-integration phased array digital radars have become feasible and more urgent. The receive and transmit channels are important components of a phased array digital radar. For a broadband radar system, a high-speed and high-precision ADC chip with a converter exceeding GHz is a core device in a radar transceiving link. Compared with the traditional ADC chip at MHz level, the method is limited by the process, and a multi-channel interweaving method is mostly adopted in the high-speed ADC with the sampling rate exceeding GHz during the design of an inner core; in the design of data transmission, the conventional low-speed CMOS parallel interface cannot meet the requirements of low power consumption and miniaturization of a chip, and instead, a high-speed serial SEDERS interface of the JESD204B protocol is adopted to realize high-speed data transmission of an ADC. The synchronous clock divider circuit is crucial to the phase relationship of the data paths between the multiple-channel interleaved ADC channels and the data synchronization between different clock domains. The invention provides a synchronous frequency division circuit device applied to a high-speed high-precision ADC system aiming at the design difficulty of a synchronous frequency division circuit of a high-speed high-precision ADC, and solves the problem of the design of the synchronous circuit of the high-speed high-precision ADC circuit of a multi-channel interweaving framework.

Description

Synchronous frequency division circuit

Technical Field

The invention belongs to the field of integrated circuit design and application, and particularly relates to a synchronous frequency division circuit in a high-speed data converter.

Background

With the rapid development of microelectronic technology and communication technology, high-integration phased array digital radars have become feasible and more urgent. The receive and transmit channels are important components of a phased array digital radar. One phased array digital radar usually needs thousands or even over ten thousands of receiving channels, and the performance of the receiving channels directly determines the key factors of the overall performance of the phased array radar. For a broadband radar system, a high-speed and high-precision ADC chip with a converter exceeding GHz is a core device in a radar transceiving link. Compared with the traditional ADC chip at MHz level, the method is limited by the process, and a multi-channel interweaving method is mostly adopted in the high-speed ADC with the sampling rate exceeding GHz during the design of an inner core; in the design of data transmission, the conventional low-speed CMOS parallel interface cannot meet the requirements of low power consumption and miniaturization of a chip, and instead, a high-speed serial SEDERS interface of the JESD204B protocol is adopted to realize high-speed data transmission of an ADC. The synchronous clock divider circuit is crucial to the phase relationship of the data paths between the multiple-channel interleaved ADC channels and the data synchronization between different clock domains. A conventional low rate ADC clock divider circuit is shown in fig. 1. The ADC is realized by adopting a single channel at low speed, a multi-channel interweaving method is not needed, and the realization is simple. FIG. 2 is a clock domain architecture of a high-speed data converter, which is implemented by a multi-channel interleaved architecture for reducing the circuit implementation pressure on the one hand of a high-speed high-precision ADC with a GHz level sampling rate, which requires a multi-phase frequency division clock synchronous with a sampling clock circuit and also ensures the synchronous relationship between an ADC analog circuit and an ADC digital circuit; on the other hand, the high-speed and high-precision ADC mostly adopts the SERDES based on the JESD204B protocol for data transmission, and needs to perform clock domain crossing synchronization signal processing between the protocol layer and the ADC digital circuit and between the protocol layer and the physical layer.

Disclosure of Invention

The invention aims to provide a synchronous frequency division circuit device applied to a high-speed high-precision ADC system aiming at the design difficulty of a synchronous frequency division circuit of a high-speed high-precision ADC, and solves the problem of the design of the synchronous circuit of the high-speed high-precision ADC circuit of a multi-channel interweaving framework. The specific contents are as follows:

the working clocks for generating the high-speed interleaved ADC comprise an ADC analog channel working clock, an ADC digital channel working clock, a JESD204B transport layer working clock, a JESD204B protocol layer working clock and a FIFO buffer circuit working clock.

The synchronous frequency division circuit comprises an 8 frequency divider circuit, an 8x1 clock selector circuit, a synchronous edge taking circuit 1, a 2 frequency divider circuit 1, a beat extension circuit 1, a synchronous edge taking circuit 2, a 2 frequency divider circuit 2, a beat extension circuit 2, a synchronous edge taking circuit 3, a 2 frequency divider circuit 3, a beat extension circuit 3, a 2x1 clock selector circuit 1, a 2x1 clock selector circuit 2, a 2x1 clock selector circuit 3 and a sysref synchronizer.

The 8-divider circuit generates 8-divided clocks sclk _ div8_ p0, sclk _ div8_ p1, sclk _ div8_ p2, sclk _ div8_ p3, sclk _ div8_ p4, sclk _ div8_ p5, sclk _ div8_ p6, sclk _ div8_ p7 with a fixed phase difference according to a sampling clock sclk, the 8-phase divided clock being generated by the sampling clock sclk according to a synchronization control input signal sysref _ in.

The 8x1 clock selector circuit generates a divided-by-8 clock signal sysclk _ div8. For an ADC digital circuit to sample an analog 8-phase input signal, the 8-divided sampling clock takes one of sclk _ div8_ p0, sclk _ div8_ p1, sclk _ div8_ p2, sclk _ div8_ p3, sclk _ div8_ p4, sclk _ div8_ p5, sclk _ div8_ p6, sclk _ div8_ p 7.

The synchronous edge taking circuit 1 performs synchronous processing on an input synchronous control signal sysref _ in a high-speed sampling clock sclk domain, adjusts the pulse width of the input signal to be within one sampling period, and is used for performing synchronous pulse control signal sysref _ pos of a frequency division clock 2.

The 2-frequency divider circuit 1 is configured to generate a two-frequency-divided output synchronous clock sclk _ div2 with a fixed output phase according to the sampling clock sclk and the synchronous control signal sysref _ pos after the synchronous edge fetching circuit 1.

The beat extension circuit 1 is characterized in that the synchronous circuit takes the sysref _ pos synchronous control signal after the edge circuit 1 to perform pulse extension processing, and the pulse width of the synchronous control signal is extended to be the width sysref _ in _ div2 which is twice the original signal period.

The synchronous edge fetching circuit 2 generates a clock domain synchronous pulse signal sclk _ div2_ pos based on sclk _ div2 after the signal of the extension circuit 1 is beaten is synchronized by a two-frequency-division output clock sclk _ div 2.

The 2-frequency divider circuit 2 generates an output four-frequency-divided clock sclk _ div4 by synchronously taking the sclk _ div2_ pos signal generated by the edge circuit 2 from the two-frequency-divided clock sclk _ div2 of the sampling clock. The beat extension circuit 2 performs pulse extension processing on the sysref _ div2_ pos signal after the edge circuit 2 is taken by the synchronous circuit, and extends the pulse width of the synchronous control signal to be four times the width of the original signal cycle sysref _ in _ div 4.

The synchronous edge fetching circuit 3 generates a clock domain synchronous pulse signal sclk _ div4_ pos based on sclk _ div4 after synchronizing the signals of the extension circuit 2 through a four-frequency-division output clock sclk _ div 4.

The 2-frequency divider circuit 3 generates an eight-frequency-divided clock sclk _ div8 with a fixed output phase by synchronously taking out the sclk _ div4_ pos signal generated by the edge 3 circuit from the four-frequency-divided clock sclk _ div4 of the sampling clock.

The beat extension circuit 3 performs pulse extension processing on the sysref _ div4_ pos signal generated by the edge circuit 3 by the synchronous circuit, and expands the pulse width of the synchronous signal into eight times the width of the sysref _ in _ div8 of the original signal period.

The 2x1 clock selector circuit 1 selects the two-divided clock sclk _ div2 of the sampling clocks sclk and sclk using a 1-out-of-2 clock selector according to the user mode of the 204b protocol transport layer.

The 2 × 1 clock selector circuit 2 selects the four-divided clock sclk _ div4 of the sampling clock sclk and the eight-divided clock sclk _ div8 of the sclk using the 1-out-of-2 clock selection circuit according to the user mode of the 204b protocol transport layer.

The 2x1 clock selector circuit 3 selects the clock output signals of the 2x1 clock selector circuit 1 and the 2x1 clock selector circuit 2 using the 2-to-1 clock selection circuit according to the user mode of the 204B protocol transport layer, generating a synchronous clock pclk of the 204B interface protocol layer.

The sysref synchronizer synchronizes the expanded sync pulse signal sysref _ in _ div8 generated by beat expansion 3 to the PCLK clock domain for local multi-frame signal generation at the 204B protocol link layer.

The invention has the beneficial effects that:

the invention solves the synchronization problem of an ADC analog channel, an ADC digital channel, a high-speed 204B interface transmission layer, a high-speed 204B interface protocol layer, an FIFO buffer circuit and a high-speed 204B interface physical layer of an interweaving framework, can apply the synchronous frequency division circuit device to the synchronous design of a high-speed high-precision DAC, and improves the performance of a DAC chip.

Drawings

Fig. 1 is a block diagram of a conventional ADC clock synchronization scheme.

FIG. 2 is a clock domain architecture of a high speed data converter.

Fig. 3 is a synchronous frequency division circuit of a high-speed data converter.

Fig. 4 is a timing diagram of an eight-phase clock divider circuit.

FIG. 5 is a timing diagram of a synchronous clock divider circuit.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description, but the scope of the invention is not limited to the following description.

As shown in fig. 3, a synchronous frequency divider circuit of a high-speed high-precision data converter is used for generating the operating clocks of an ADC with a high-speed interleaved architecture, including an ADC analog channel operating clock, an ADC digital channel operating clock, a JESD204B transport layer operating clock, a JESD204B protocol layer operating clock, a FIFO buffer circuit operating clock, and a JESD204B physical layer operating clock. Fig. 4 and 5 are timing diagrams of the circuit of the present invention.

The synchronous frequency dividing circuit and method will be described in detail below.

The high-speed high-precision interleaved architecture ADC receives a high-precision sampling clock sysclk from a clock generator and a low-speed synchronous control signal sysref _ in signal, and the synchronous frequency divider circuit generates a synchronous pulse signal sysref _ pos1 by passing the input synchronous control signal sysref through a synchronous edge extractor circuit. The synchronous edge fetching circuit 1 is composed of 3 stages of flip-flops, wherein the 1 st and 2 nd stage flip-flops are used for carrying out two-stage signal delay on an input sysref _ in signal to generate sysref _ r1 and sysref _ r2 signals, the 3 rd stage flip-flop generates a sysref _ r3 signal, and the sysref _ r2 and the sysref _ r3 generate a synchronous edge fetching signal sysref _ pos1 with the same pulse width as the cycle of a sampling clock sclk through an exclusive-or gate.

The 8-division circuit is generated by a counter circuit, the certainty of the initial phase of a frequency division clock is guaranteed according to a synchronous edge signal sysref _ pos1, 8-division clocks sysclkdiv _ p0, sysclkdiv _ p1, sysclkdiv _ p2, sysclkdiv _ p3, sysclkdiv _ p4, sysclkdiv _ p5, sysclkdiv _ p6 and sysclkdiv _ p7 which have 45-degree phase difference are generated by delay 0-delay 7 units, and the 8-phase working clock and the ADC digital channel working clock are generated for an ADC analog sub-channel. As shown in the timing diagram of fig. 4, when the system clock samples the pulse signal after the synchronous edge, the frequency division counter starts to clear and starts to count from 0 to 7 cycles, thereby generating 8-phase frequency division clocks accurately.

The frequency division by 2 circuit 1 is configured to generate a frequency division by 2 clock sysclk _ div2 with a fixed initial phase according to the signal sysref _ in _ pos in the pulse of the synchronous edge.

The beat extension circuit 1 is a first-stage flip-flop circuit and an exclusive-or gate circuit, and is configured to generate a synchronization signal sysref _ div2_ pos with an extended pulse width, where the pulse width is a clock period divided by a sampling clock 2.

The synchronous edge taking circuit 2 is a primary trigger circuit and an AND gate circuit and is used for generating a synchronous signal of 2 frequency division clock pulse width.

The frequency division by 2 circuit 2 is configured to accurately generate the divided-by 4 clock sysclk _ div4 of the sampling clock from the divided-by 2 clock according to the synchronization pulse signal sysref _ div2_ pos.

The beat extension circuit 2 is a one-stage flip-flop circuit and an exclusive-or gate circuit, and is configured to generate a synchronization signal sysref _ div4 with an extended pulse width, where the pulse width is a clock width of a sampling clock divided by 4 cycles.

The synchronous edge taking circuit 3 is a two-stage flip-flop delay circuit and an and gate circuit, and is used for generating a synchronous control signal sysref _ div4_ pos with a 4-division clock pulse width.

The divide-by-2 and 3 circuit is used for accurately generating the sampling clock and the divide-by-8 clock sysclk _ div8 from the divide-by-2 clock according to the synchronous pulse signal sysref _ div4_ pos.

The beat extension circuit 3 is a one-stage flip-flop circuit and an exclusive-or gate circuit, and is configured to generate a synchronization signal sysref _ div8 with an extended pulse width, where the pulse width is a clock width of a sampling clock divided by 8 cycles.

The sysref synchronizer is a two-stage flip-flop delay circuit for synchronizing the synchronization signal sysref _ div8 of the sysclk _ div8 clock domain to the PCLK clock domain.

The 2X1 clock selection circuit 1 is used to select a sampling clock sclk and a two-divided-frequency clock sclk _ div2, the 2X1 clock selection circuit 2 is used to select a four-divided-frequency sampling clock sclk _ div4 and an eight-divided-frequency sampling clock sclk _ div8, the 2X1 clock selection circuit 3 is shown to select the clock outputs after the clock selection circuit 1 and the clock selection circuit 2, which are used as PCLK and provided to a high-speed interface circuit transmission layer and a protocol layer.

The present invention is not limited to the above-described specific embodiments, and various modifications and variations are possible. Any modifications, equivalents, improvements and the like made to the above embodiments in accordance with the technical spirit of the present invention should be included in the scope of the present invention.

Claims

1. A synchronous frequency dividing circuit is used for generating working clocks of an ADC (analog to digital converter) with a high-speed interleaved architecture, and comprises an ADC analog channel working clock, an ADC digital channel working clock, a JESD204B transport layer working clock, a JESD204B protocol layer working clock and an FIFO buffer circuit working clock, and is characterized in that: the circuit comprises an 8 frequency divider circuit, an 8x1 clock selector circuit, a synchronous edge taking circuit 1, a 2 frequency divider circuit 1, a beat extension circuit 1, a synchronous edge taking circuit 2, a 2 frequency divider circuit 2, a beat extension circuit 2, a synchronous edge taking circuit 3, a 2 frequency divider circuit 3, a beat extension circuit 3, a 2x1 clock selector circuit 1, a 2x1 clock selector circuit 2, a 2x1 clock selector circuit 3 and a synchronizer;

the 8-frequency divider circuit uses a fixed 8-frequency division clock for a sampling clock of a sub-ADC (analog-to-digital converter) with an 8-channel interweaving architecture according to a phase difference generated by the sampling clock, wherein the 8-frequency division clock is generated by the sampling clock according to a synchronous control input signal;

the 8x1 clock selector circuit generates 8-division clock signals for the ADC digital circuit to sample the analog 8-phase input signal, wherein the 8-division clock is one of the 8-division clock signals;

the synchronous edge taking circuit 1 carries out synchronous processing on an input synchronous control signal in a sampling clock domain, adjusts the pulse width of the input signal to be within a sampling period and is used for generating a synchronous pulse control signal of a frequency division clock of 2;

the 2 frequency divider circuit 1 is used for outputting two frequency-divided output synchronous clocks with fixed phases according to a sampling clock and a synchronous pulse control signal of the synchronous edge taking circuit 1;

the beat expansion circuit 1 is used for carrying out pulse expansion processing on a synchronous pulse control signal generated by the synchronous circuit edge taking circuit 1 and expanding the pulse width to be twice of the original signal period;

the synchronous edge taking circuit 2 generates a clock domain synchronous pulse signal based on the synchronous pulse control signal after synchronizing the output synchronous clock of the two frequency divisions of the signal output by the beat extension circuit 1;

the 2-frequency divider circuit 2 generates and outputs a four-frequency division clock by a two-frequency division clock of the sampling clock through a clock domain synchronous pulse signal generated by the synchronous edge taking circuit 2;

the beat expansion circuit 2 is used for carrying out pulse expansion processing on a clock domain synchronous pulse signal after the circuit of the edge 2 of the synchronous circuit, and expanding the pulse width to be four times of the width of the original signal period;

the synchronous edge taking circuit 3 generates a clock domain synchronous pulse signal based on the expanded clock domain synchronous pulse signal after the signal expanded by the beat expansion circuit 2 is synchronized by a four-frequency-division output clock;

the 2-frequency divider circuit 3 generates an eight-frequency division clock with a fixed output phase by a clock domain synchronous pulse signal generated by the synchronous edge taking circuit 3;

the beat expansion circuit 3 is used for carrying out pulse expansion processing on a clock domain synchronous pulse signal generated by the edge 3 circuit of the synchronous circuit, and expanding the pulse width to be eight times of the original signal period;

the 2x1 clock selector circuit 1 selects a two-frequency-division clock of the sampling clock by adopting a 2-to-1 clock selector according to a user mode of a 204b protocol transport layer;

the 2x1 clock selector circuit 2 selects the four-frequency division clock and the eight-frequency division clock of the sampling clock by adopting a 2-to-1 clock selection circuit according to the user mode of the 204b protocol transport layer;

the 2x1 clock selector circuit 3, according to the user mode of the 204b protocol transport layer, adopts the 2-to-1 clock selector circuit to select the clock output signals of the 2x1 clock selector circuit 1 and the 2x1 clock selector circuit 2, and generates the synchronous clock of the 204b interface protocol layer;

the synchronizer synchronizes the expanded synchronous pulse signal generated by the beat expansion circuit 3 to the clock domain, and is used for generating a local multi-frame signal of a 204B protocol link layer.