CN115714599A

CN115714599A - Synchronous frequency division circuit based on interweaving framework

Info

Publication number: CN115714599A
Application number: CN202211611496.7A
Authority: CN
Inventors: 吴俊杰; 徐宏林; 张�浩
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2022-12-15
Filing date: 2022-12-15
Publication date: 2023-02-24

Abstract

A synchronous frequency division circuit based on an interleaving framework comprises an 8 frequency divider circuit, an 8x1 clock selector circuit, three synchronous edge taking circuits, three 2 frequency divider circuits and three beat expansion circuits, wherein an external sampling clock sclk and a low-speed synchronous control signal sysref _ in are input to generate a synchronous pulse signal sysref _ pos, then 8 frequency division clocks with fixed phase difference are generated to be used for sampling a sampling clock of an analog circuit of an ADC digital circuit of the 8-channel interleaving framework, and the synchronous clock pclk of a 204B protocol is generated to be used for a transmission layer and a protocol layer of a high-speed interface circuit, so that the synchronization problem is solved, and the synchronous frequency division circuit is applied to the synchronous design of a high-speed high-precision ADC and can improve the performance of an ADC chip.

Description

Synchronous frequency division circuit based on interweaving framework

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a clock synchronization frequency division technology.

Background

With the development of microelectronic technology and communication technology, high-integration phased array digital radars become feasible and urgent. The receiving and transmitting channels are important components of the phased array digital radar, one phased array digital radar needs thousands of receiving and transmitting channels, and the performance of the receiving and transmitting channels directly determines the overall performance of the phased array radar.

The traditional low-rate ADC clock frequency division circuit is realized by adopting a single channel as shown in figure 1, and does not need multi-channel interleaving and a high-speed serial interface circuit. According to the application requirements of different sampling rates, an external synchronous control signal SYSREF is adopted to reset the frequency dividers in the ADC chip, so that the initial phases of the different frequency dividers are kept consistent. The internal clock MUX selects the required frequency division clock, distributes the clock to the delay circuit in the chip, outputs CLK _ ANA to the analog circuit and outputs CLK _ DIG to the digital circuit. According to the signal quality of the output signal ADC _ DATAOUT of the ADC, the phase relation of CLK _ ANA and CLK _ DIG in the delay circuit is adjusted. And measuring the phase relation between the ADC _ DATAOUT of different chips, adjusting the phase of SYSREF of different chips and realizing synchronization of multiple chips.

The clock design in the high-speed high-precision ADC relates to an ADC analog circuit, an ADC digital circuit, a protocol layer circuit of a high-speed serial interface and a physical layer of the high-speed serial interface. The synchronous clock frequency division circuit is important for the phase relation of data paths among multiple channels of the interleaved ADC and the data synchronization among different clocks.

Compared with the traditional MHz level, the high-speed and high-precision ADC chip exceeding GHz is a core device of a transmitting-receiving link in a broadband radar system. Limited by the state of the art, in order to reduce the circuit implementation pressure, a multi-channel interleaving method is adopted in the core design, as shown in fig. 3. Multichannel interleaving requires a multiphase frequency division clock which is synchronous with a sampling clock circuit, and also requires that an ADC analog circuit and an ADC digital circuit are synchronous. When data transmission is designed, the traditional low-speed CMOS parallel interface cannot meet the requirements of low power consumption and miniaturization of a chip. The high-speed serial SEDERS interface of the JESD204B protocol is adopted to replace the interface, synchronous signal processing across clock domains is required to be carried out between a protocol layer and an ADC digital circuit and between the protocol layer and a physical layer, and high-speed data transmission of the ADC is realized.

Disclosure of Invention

The invention provides a synchronous frequency division circuit based on an interweaving framework in order to solve the problem of synchronous frequency division design of a high-speed high-precision ADC (analog to digital converter).

The circuit comprises an 8 frequency divider circuit, an 8x1 clock selector circuit, three synchronous edge taking circuits, three 2 frequency divider circuits and three beat expansion circuits.

An external sampling clock sclk and a low-speed synchronous control signal sysref _ in are input into the synchronous edge taking circuit 1 to generate a synchronous pulse signal sysref _ pos.

Further, the synchronous edge fetching circuit 1 comprises 3 stages of flip-flops, the sysref _ in is input into the 1 st, 2 nd and 3 rd flip-flops, three stages of delay signals sysref _ r1, sysref _ r2, sysref _ r3, sysref _ r2 and sysref _ r3 are generated to be input into an exclusive-or gate, and sysref _ pos is generated, and the pulse width is the same as the cycle of sclk.

sclk and sysref _ pos are input to an 8-divider circuit, which generates 8 divided clocks sclk _ div8_ p0, sclk _ div8_ p1, sclk _ div8_ p2, sclk _ div8_ p3, sclk _ div8_ p4, sclk _ div8_ p5, sclk _ div8_ p6, sclk _ div8_ p7, which have fixed phase differences, and an 8 × 1 clock selector circuit, with 8 select 1 generating an 8 divided clock signal sysclk _ div8, which is used for the 8-channel interleaved architecture ADC digital circuit to sample the sampling clock of the analog circuit.

Further, the 8-divider circuit includes a counter circuit and 7 delay units delay0, delay1, delay2, delay3, delay4, delay5, and delay6, and counts cyclically, to generate 8 division clocks having a phase difference of 45 degrees for the operation clocks of the ADC analog channel and the ADC digital channel, and sysref _ pos maintains the certainty of the initial phase.

sclk and sysref _ pos are input to a frequency divider circuit 1 of 2, which generates a synchronous clock sclk _ div2 of 2 frequency division with a fixed phase, and sysref _ pos is input to a beat extension circuit 1, which extends the pulse width by an initial double, generating a signal sysref _ in _ div2.

sclk _ div2 and sysref _ in _ div2 are input to the synchronous edge fetching circuit 2, and a synchronous pulse signal sclk _ div2_ pos based on the synchronous clock sclk _ div2 is generated.

sclk _ div2 and sclk _ div2_ pos are input to a 2-divider circuit 2 to generate a 4-division synchronous clock sclk _ div4 with fixed phase, and sysref _ div2_ pos is input to a beat extension circuit 2 to extend the pulse width by an initial quadruple to generate a signal sysref _ in _ div4.

sclk _ div4 and sysref _ in _ div4 are input to the synchronous edge fetching circuit 3, and a synchronous pulse signal sclk _ div4_ pos based on the synchronous clock sclk _ div4 is generated.

sclk _ div4 and sclk _ div4_ pos are input to a 2-divider circuit 3 to generate a fixed-phase, 8-divided synchronous clock sclk _ div8, and sysref _ div4_ pos is input to a beat-up extension circuit 3 to extend the pulse width by the initial eight times to generate a signal sysref _ in _ div8.

sclk and sclk _ div2 are input to the 2x1 clock selector circuit 1, and are input to the 2x1 clock selector circuit 3 after 1 is selected by 2 according to the user mode of the 204b protocol.

sclk _ div4 and sclk _ div8 are input to the 2x1 clock selector circuit 2, and are input to the 2x1 clock selector circuit 3 after 1 is selected by 2 according to the user mode of the 204b protocol.

The 2x1 clock selector circuit 3 generates a synchronous clock pclk of the 204B protocol for the transport layer and the protocol layer of the high speed interface circuit according to the user mode of the 204B protocol transport layer, select-2-1.

sysref _ in _ div8 and PCLK are input to the sysref synchronizer, which synchronizes sysref _ in _ div8 and PCLK, generating 204B a local multi-frame signal for the protocol link layer.

Further, the

beat extension circuits

1, 2, and 3 include a first-stage trigger delay circuit and an exclusive or gate circuit, the synchronous edge taking circuit 2 includes a first-stage trigger delay circuit and an and gate circuit, the synchronous edge taking circuit 3 includes a two-stage trigger delay circuit and an and gate circuit, and the sysref synchronizer includes a two-stage delay trigger circuit.

The invention has the beneficial effects that: the synchronous edge taking and beat expanding circuit provides a clock PCLK for the synchronization parallel of a JESD204B interface transmission layer and a protocol layer, inputs a sysref _ in synchronous control signal and a multiphase frequency division clock of the sysref _ in to generate a JESD204B local multi-frame clock, solves the synchronization problem of an ADC analog channel, an ADC digital channel, a high-speed 204B interface transmission layer, a high-speed 204B interface protocol layer, an FIFO buffer circuit and a high-speed 204B interface physical layer of an interleaved architecture, is applied to the synchronous design of a high-speed high-precision ADC, and can improve the performance of an ADC chip.

Drawings

Fig. 1 is a conventional clock division circuit configuration, fig. 2 is an 8-channel interleaved clock division circuit configuration, and fig. 3 is a high-speed data conversion clock.

Detailed Description

The technical scheme of the invention is specifically explained in the following by combining the attached drawings.

The structure of the circuit is shown in fig. 2, a sampling clock sclk and low-speed synchronous control signals sysref _ in, sclk and sysref _ in are input into a synchronous edge taking circuit 1 to generate a synchronous pulse signal sysref _ pos.

sclk and sysref _ pos are input to an 8-divider circuit, which generates 8 divided clocks sclk _ div8_ p0, sclk _ div8_ p1, sclk _ div8_ p2, sclk _ div8_ p3, sclk _ div8_ p4, sclk _ div8_ p5, sclk _ div8_ p6, sclk _ div8_ p7, which have fixed phase differences, and input to an 8 × 1 clock selector circuit, and select-8 generates an 8 divided clock signal sysclk _ div8.

The 8-divider circuit includes a counter circuit and 7 delay units delay0, delay1, delay2, delay3, delay4, delay5, delay6, cycle count, generating 8 divided clocks.

The sclk _ div2 and sysref _ in _ div2 are input to the synchronous edge fetching circuit 2, and the synchronous pulse signal sclk _ div2_ pos based on the synchronous clock sclk _ div2 is generated.

sclk _ div2 and sclk _ div2_ pos are input to a 2-divider circuit 2 to generate a 4-divided synchronous clock sclk _ div4 with a fixed phase, and sysref _ div2_ pos is input to a beat extension circuit 2 to extend the pulse width by an initial quadruple to generate a signal sysref _ in _ div4.

sclk _ div4 and sclk _ div8 are input to the 2x1 clock selector circuit 2, and are input to the 2x1 clock selector circuit 3 after 2 selects 1 according to the user mode of the 204b protocol.

The 2x1 clock selector circuit 3 generates a synchronous clock pclk of the 204B protocol for the transport layer and the protocol layer of the high speed interface circuit according to the user mode of the transport layer of the 204B protocol, select-2-1.

sysref _ in _ div8 and PCLK are input to the sysref synchronizer to synchronize sysref _ in _ div8 and PCLK, generating a local multi-frame signal at the 204B protocol link layer.

The above-described embodiments are not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the present invention.

Claims

1. A synchronous frequency division circuit based on an interleaved architecture, comprising: the circuit comprises an 8 frequency divider circuit, an 8x1 clock selector circuit, three synchronous edge taking circuits, three 2 frequency divider circuits and three beat expansion circuits;

an external sampling clock sclk and a low-speed synchronous control signal sysref _ in are input into a synchronous edge taking circuit 1 to generate a synchronous pulse signal sysref _ pos;

sclk and sysref _ pos are input into an 8-frequency divider circuit to generate 8 frequency division clocks sclk _ div8_ p0, sclk _ div8_ p1, sclk _ div8_ p2, sclk _ div8_ p3, sclk _ div8_ p4, sclk _ div8_ p5, sclk _ div8_ p6 and sclk _ div8_ p7 with fixed phase difference, and input into an 8x1 clock selector circuit, wherein 8 to 1 generates an 8 frequency division clock signal sysclk _ div8 which is used for sampling a sampling clock of an 8-channel interleaved architecture ADC digital circuit sampling analog circuit;

sclk and sysref _ pos are input into a 2-frequency divider circuit 1 to generate a 2-frequency division synchronous clock sclk _ div2 with a fixed phase, and sysref _ pos is input into a beat extension circuit 1 to extend the pulse width to be twice of the initial time to generate a signal sysref _ in _ div2;

sclk _ div2 and sysref _ in _ div2 are input into the synchronous edge fetching circuit 2, and a synchronous pulse signal sclk _ div2_ pos based on the synchronous clock sclk _ div2 is generated;

sclk _ div2 and sclk _ div2_ pos are input into a 2-frequency divider circuit 2 to generate a 4-frequency division synchronous clock sclk _ div4 with a fixed phase, and sysref _ div2_ pos is input into a beat extension circuit 2 to extend the pulse width to be four times initially to generate a signal sysref _ in _ div4;

sclk _ div4 and sysref _ in _ div4 are input into the synchronous edge fetching circuit 3, and a synchronous pulse signal sclk _ div4_ pos based on the synchronous clock sclk _ div4 is generated;

sclk _ div4 and sclk _ div4_ pos are input into a 2-frequency divider circuit 3 to generate an 8-frequency division synchronous clock sclk _ div8 with a fixed phase, and sysref _ div4_ pos is input into a beat extension circuit 3 to extend the pulse width to the initial eight times to generate a signal sysref _ in _ div8;

sclk and sclk _ div2 are input into a 2x1 clock selector circuit 1, and are input into a 2x1 clock selector circuit 3 after 1 is selected by 2 according to a user mode of a 204b protocol;

the sclk _ div4 and the sclk _ div8 are input into a 2x1 clock selector circuit 2, and are input into a 2x1 clock selector circuit 3 after 1 is selected from 2 according to a user mode of a 204b protocol;

the 2x1 clock selector circuit 3 generates a synchronous clock pclk of a 204B protocol according to a user mode of a 204B protocol transmission layer by 2-to-1 selection, and the synchronous clock pclk is used for a transmission layer and a protocol layer of a high-speed interface circuit;

2. The synchronous frequency divider circuit of claim 1, wherein the synchronous edge fetching circuit 1 comprises 3 stages of flip-flops, the sysref _ in inputs the 1 st, 2 nd, and 3 rd stage flip-flops to generate three stages of delay signals sysref _ r1, sysref _ r2, sysref _ r3, sysref _ r2, and sysref _ r3 input exclusive-or gates to generate sysref _ pos with the same pulse width as the cycle of sclk.

3. The synchronous frequency division circuit based on the interleaving architecture as claimed in claim 1, wherein the 8 frequency divider circuit comprises a counter circuit and 7 delay units delay0, delay1, delay2, delay3, delay4, delay5, delay6, cycle count, generate 8 division clocks with a phase difference of 45 degrees for the operating clocks of the ADC analog channel and ADC digital channel, sysref _ pos maintains the certainty of the initial phase.

4. The synchronous frequency division circuit based on the interleaving architecture as claimed in claim 1, wherein the beat extension circuits 1, 2, 3 comprise a one-stage flip-flop delay circuit and an exclusive-or gate circuit, the synchronous edge fetching circuit 2 comprises a one-stage flip-flop delay circuit and an and gate circuit, the synchronous edge fetching circuit 3 comprises a two-stage flip-flop delay circuit and an and gate circuit, and the sysref synchronizer comprises a two-stage flip-flop circuit.