CN109687860A - A kind of multi-phase clock serializer and signal translating system - Google Patents
A kind of multi-phase clock serializer and signal translating system Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
Abstract
This application involves a kind of multi-phase clock serializer and signal translating systems, the multi-phase clock serializer, it applies in the signal translating system with single-frequency, including multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；Multidiameter delay data are pre-processed by multidiameter delay data prediction circuit, obtain multiple pretreatment serial datas, while serially providing sufficient settling time to be subsequent；And the wide continuous impulse signal generating circuit can generate multiple Deng wide pulse signals, enable multiplex electronics that multichannel pretreatment serial data is carried out final serial process according to multiple wide clock pulses, to obtain serial data stream.The generation of equal wide pulse signals is without using frequency divider, to simplify the structure of multi-phase clock serializer.
Description
Technical field
The present invention relates to signal switch technology field more particularly to a kind of multi-phase clock serializers and signal translating system.
Background technique
Serializer (serializers) is interface circuit important in high-speed data communication system, is used for multidiameter delay
Data are converted into highspeed serial data stream.There are three types of the serializers of structure at present: shift register structure (shift-register
Type), tree-shaped (tree type) structure and multi-phase clock structure (multi-phase type).
The serializer design of multi-phase clock structure is simple, low in energy consumption, is widely used in middle low speed interface circuit.The structure
Clock dividers (frequency divider) is needed to generate the uniform multiphase clock of phase phase difference, and multiphase clock
Phase difference will control in a data bit width.
With the increase of serial scale, which needs more frequency dividing multi-phase clock signals, and when these leggies
The phase difference of clock will control within the scope of a data bit width, increase desiging frequency divider difficulty and scale, or even need to introduce
The clock control circuit of the complexity such as phaselocked loop.It further needs exist for introducing phase of several delay buffers to guarantee clock and data
Position nargin, the structure that this results in multi-phase clock serializer are complex.
Summary of the invention
In view of this, the present invention provides a kind of multi-phase clock serializer, it is serial to solve multi-phase clock in the prior art
Device is in the increased situation of serial scale, the complex problem of the clock control circuit being related to.
To achieve the above object, the invention provides the following technical scheme:
A kind of multi-phase clock serializer, is applied in the signal translating system with single-frequency, the multi-phase clock string
Row device includes:
Multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；
The multidiameter delay data prediction circuit receives input and the initial clock signal of multidiameter delay data；
The wide continuous impulse signal generating circuit receives the initial clock signal, and to the initial clock signal
Postponed, obtain multiple delay clock signals, the delay time of the two neighboring delay clock signals is identical；To adjacent
It is of same size that two delay clock signals carry out the multiple high level of logical operation generation, and continuous multiple on a timeline
Wide clock pulses；
The multidiameter delay data prediction circuit is according to the initial clock signal and multiple delay clock signals to institute
It states multidiameter delay data and carries out at least one level serial process, obtain multichannel pretreatment serial data；
The multiplex electronics carry out multichannel pretreatment serial data according to the multiple wide clock pulses
Serial process obtains serial data stream.
Preferably, the multidiameter delay data prediction circuit includes:
Sample circuit and multiple 2:1 multiplex electronics；
The sample circuit samples the portion in the multidiameter delay data when the initial clock signal failing edge triggers
Branch data obtain multi-channel sampling output data；
Each 2:1 multiplex electronics receive the circuit-switched data in the multidiameter delay data in remainder；And
Under the action of the delay clock signals, the pretreatment serial data all the way is exported.
Preferably, the sample circuit includes multiple d type flip flops；
One input terminal of each d type flip flop receives the initial clock signal；Described in another input terminal receives
A circuit-switched data in multidiameter delay data in partial data；
The d type flip flop is used for a number received to another input terminal in the initial clock signal failing edge
According to being sampled, sampling output data is obtained.
Preferably, the wide continuous impulse signal generating circuit includes:
Multiple delay cells and multiple XOR gates；
The delay cell receives the initial clock signal and adjusts value signal, changes institute according to the adjusting value signal
The delay time of initial clock signal is stated, and exports multiple delay clock signals；
Each XOR gate is connected with the output end of two adjacent delay cells, for two neighboring prolonging to received
Slow clock signal carries out XOR logic operation, obtains multiple wide clock pulses.
Preferably, the multiplex electronics include multiple multiplexers, and the multiple multiplexer forms (m+
1): 1 multiplex electronics, wherein the value of (m+1) is identical as the quantity of the XOR gate.
Preferably, the quantity of the multidiameter delay data is greater than or equal to 8, and the multiple side for being 2.
It preferably, further include clock-signal generator, for exporting the initial clock signal.
The present invention also provides a kind of signal translating systems to use including multi-phase clock serializer described in any of the above one
In multidiameter delay data are converted to serial data stream.
It can be seen via above technical scheme that multi-phase clock serializer provided by the invention, is applied with single-frequency
Signal translating system in, multi-phase clock serializer include multidiameter delay data prediction circuit, wide continuous impulse signal produce
Raw circuit and multiplex electronics；Multidiameter delay data are pre-processed by multidiameter delay data prediction circuit, are obtained
Multichannel pre-processes serial data, while serially providing sufficient settling time to be subsequent；And the wide continuous impulse signal
Generation circuit can generate multiple Deng wide pulse signals, enable multiplex electronics will be more according to multiple wide clock pulses
Road pretreatment serial data carries out final serial process, to obtain serial data stream.
Since multi-phase clock serializer provided in the present invention is realized only with three above module by multidiameter delay data
It is converted into serial data stream, and wide continuous impulse signal generating circuit can generate multiple delay clock signals and multiple
Wide clock pulses, so as to avoid using the clock control in the prior art with the complicated component such as phaselocked loop, frequency divider
Circuit, and then simplify the structure of multiphase serializer.Simultaneously as multidiameter delay data prediction circuit can be subsequent serial
Settling time is provided, ensure that the phase margin of clock and data.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is serializer structural schematic diagram in the prior art；
Fig. 2 is the timing diagram of serializer shown in Fig. 1；
Fig. 3 is a kind of multi-phase clock serializer structural schematic diagram provided in an embodiment of the present invention；
Fig. 4 is a kind of multidiameter delay data prediction electrical block diagram provided in an embodiment of the present invention；
Fig. 5 is a kind of wide continuous impulse signal generating circuit structural schematic diagram provided in an embodiment of the present invention；
Fig. 6 is a kind of multiplex electronics structural schematic diagram provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of 8:1 serializer；
Fig. 8 is the corresponding timing diagram of Fig. 7 serializer.
Specific embodiment
Just as described in the background section, multi-phase clock serializer in the prior art needs to introduce the complexity such as phaselocked loop
Clock control circuit, some even needs to introduce several delay buffers also to guarantee the phase margin of clock and data,
This has resulted in the complex problem of clock control circuit structure.
Specifically, as depicted in figs. 1 and 2, wherein Fig. 1 is a kind of multi-phase clock serializer knot provided in the prior art
Structure schematic diagram, Fig. 2 are the corresponding timing diagram of multi-phase clock serializer shown in FIG. 1；As shown in Figures 1 and 2, D0-D3 is defeated
Four channel parallel datas entered, CLK is input clock, and frequency requirement is serial data rate f0.Clock signal clk is by frequency dividing
Device L0 separates a half-frequency clock signal C0, half-frequency clock signal C0Frequency be clock signal CLK frequency half namely f0/
2；Clock signal clk separates another half-frequency clock signal C by frequency divider L11, half-frequency clock signal C1Frequency be f0/ 2,
With half-frequency clock signal C0Phase by pi/2.
D0 and two channel parallel data of D2 pass through first choice switch SEL1 in half-frequency clock signal C0Under the action of, output the
Level-one serial data D5；D1 and two channel parallel data of D3 pass through the second selection switch SEL2 in half-frequency clock signal C1Effect
Under, export first order serial data D6；The first order serial data D5 and D6, due to half-frequency clock signal C0And half-frequency clock signal
C1Phase by pi/2 refer to shown in Fig. 2, therefore, phase by pi/2 D5 and D6.It also needs to add several in circuit and prolong
When buffer (delay buffer) clock signal clk is delayed to obtain delay clock signal C2(frequency f0), to guarantee
When in D5 and D6 input third selection switch SEL3, the phase margin of clock and data.
It will be seen from figure 1 that half-frequency clock signal C in order to obtain0And C1, need to realize by frequency divider；And in order to obtain
Delay clock signal C2, need to add setting delay buffer, to guarantee the phase margin of clock and data.And knot shown in Fig. 1
Four channel parallel datas are only converted to serializer structure when serial data by structure.If serial scale increases, also need to obtain
More half-frequency clock signals, and meet tightened up phase margin, so that more frequency dividers and delay buffer be needed to go
It realizes.This results in serializer structure is complicated to change.
Based on this, the present invention provides a kind of multiphase clock serializer, applies in the signal conversion system with single-frequency
In system, the multi-phase clock serializer includes:
Multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；
The multidiameter delay data prediction circuit receives input and the initial clock signal of multidiameter delay data；
The wide continuous impulse signal generating circuit receives the initial clock signal, and to the initial clock signal
Postponed, obtain multiple delay clock signals, the delay time of the two neighboring delay clock signals is identical；To adjacent
It is of same size that two delay clock signals carry out the multiple high level of logical operation generation, and continuous multiple on a timeline
Wide clock pulses；
The multidiameter delay data prediction circuit is according to the initial clock signal and multiple delay clock signals to institute
It states multidiameter delay data and carries out at least one level serial process, obtain multichannel pretreatment serial data；
The multiplex electronics carry out multichannel pretreatment serial data according to the multiple wide clock pulses
Serial process obtains serial data stream.
Multi-phase clock serializer provided by the invention, is applied in the signal translating system with single-frequency, when multiphase
Clock serializer includes multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；It is logical
Excessive channel parallel data pretreatment circuit pre-processes multidiameter delay data, obtains multichannel pretreatment serial data, simultaneously
Sufficient settling time is serially provided to be subsequent；And the wide continuous impulse signal generating circuit can generate it is multiple wide
Pulse signal enables multiplex electronics to be carried out multichannel pretreatment serial data according to multiple wide clock pulses final
Serial process, to obtain serial data stream.
Since multi-phase clock serializer provided in the present invention is realized only with three above module by multidiameter delay data
It is converted into serial data stream, and wide continuous impulse signal generating circuit can generate multiple delay clock signals and multiple
Wide clock pulses, so as to avoid using the clock control in the prior art with the complicated component such as phaselocked loop, frequency divider
Circuit, and then simplify the structure of multiphase serializer.Simultaneously as multidiameter delay data prediction circuit can be subsequent serial
Settling time is provided, ensure that the phase margin of clock and data.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 3 is referred to, Fig. 3 is a kind of multi-phase clock serializer provided in the embodiment of the present invention, comprising: multidiameter delay number
Data preprocess circuit 1, wide continuous impulse signal generating circuit 2 and multiplex electronics 3；
The multidiameter delay data prediction circuit 1 receives input and the initial clock signal of multidiameter delay data D0-Dn
clk；
The wide continuous impulse signal generating circuit 2 receives the initial clock signal clk, and to the initial clock
Signal clk is postponed, and obtaining multiple (m+2) delay clock signals, (1) clk0-clk (m+1), m are greater than or equal to, adjacent
The delay time of two delay clock signals is identical；Logical operation production is carried out to two adjacent delay clock signals
Raw multiple high level are of same size, and continuous multiple (m+1) wide clock pulses (p0-pm) on a timeline；
The multidiameter delay data prediction circuit 1 is according to the initial clock signal clk and multiple (m) delayed clocks
Signal (clk0-clk (m-1)) carries out at least one level serial process to the multidiameter delay data D0-Dn, obtains multichannel pretreatment
Serial data (q0-qm)；
The multiplex electronics 3 locate the multichannel according to the multiple (m+1) wide clock pulses (p0-pm) in advance
It manages serial data (q0-qm) and carries out serial process, obtain serial data stream sout.
It should be noted that wide continuous impulse signal generating circuit 2 is to patrol two neighboring delay clock signals
It collects operation and obtains a wide clock pulses, therefore, the number of delay clock signals needs the broad pulses such as ratio in the present embodiment
More one.
In addition, multidiameter delay data prediction circuit can be serial to the multidiameter delay data progress first order in the present embodiment
Processing, can also carry out multistage serial process, be not construed as limiting in the present embodiment to this.Can as shown in prior art figure 1, it will
Four channel parallel datas carry out the serial processing of the first order, obtain two-way serial data, then pass through multiplex electronics for two-way
Serial data carries out second level serial process again, obtains final serial data stream all the way.When parallel data is more, may be used also
To carry out at least one level serial process, such as two-stage or level Four, for example, by 8 channel parallel datas by pre-processing, the pre- place
Reason includes two-stage serial process, to obtain 2 tunnel serial datas, 2 tunnel serial datas are input in multiplex electronics again, is carried out
Last serial process, obtains serial data stream.Due to needing 2 tunnel serial datas (q0 and q1), then in requisition for 2 wide clocks
Pulse (p0 and p1), then in requisition for three delay clock pulse signals (clk0-clk2).
The working principle of the multi-phase clock serializer provided in the embodiment of the present invention to clearly illustrate, with 8 in the present embodiment
It is illustrated for channel parallel data, first order string is carried out to 8 channel parallel datas in the multidiameter delay data prediction circuit
Row processing, obtains the serial preprocessed data in 4 roads.
Specific shown in Figure 4, multidiameter delay data prediction circuit structure includes: sample circuit 11 and multiple 2:1
Multiplex electronics 12；The sample circuit 11 samples the multichannel simultaneously when the initial clock signal clk failing edge triggers
Part circuit-switched data (D<4>-D<7>) in row data, obtains multi-channel sampling output data (dout<4>-dout<7>)；Each institute
It states 2:1 multiplex electronics 12 and receives a circuit-switched data (one in D<0>-D<3>in the multidiameter delay data in remainder
Road)；And under the action of delay clock signals (one in clk0-clk3), the pretreatment is gone here and there all the way for output
Row data (in q0-q3 all the way).
The structure of sample circuit is not limited in the present embodiment, as shown in Figure 4, sample circuit includes multiple in the present embodiment
D type flip flop (DFF)；One input terminal of each d type flip flop receives the initial clock signal clk；Another input terminal
Receive the circuit-switched data in partial data in the multidiameter delay data (D<4>-D<7>)；The d type flip flop is used for described first
When beginning clock signal clk failing edge, a circuit-switched data (D<4>-D<7>) received to another input terminal is sampled, and is adopted
Sample output data (dout<4>-dout<7>).
The multidiameter delay data prediction circuit provided in the embodiment of the present invention is while realizing that the first order is serial, under
Level-one serially provides sufficient settling time and phase margin.
Wide continuous impulse signal generating circuit described in the present embodiment, for generating the continuously broad pulses letters such as multiple
Number, as shown in Figure 5, the wide continuous impulse signal generating circuit includes:
Multiple delay cells (DELAY CELL) and multiple XOR gates (XOR)；
The delay cell (DELAY CELL) receives the initial clock signal clk and adjusts value signal (trm), according to
The adjusting value signal changes the delay time of the initial clock signal clk, and exports multiple delay clock signals
(clk0-clk4)；It is homogeneous phase potential difference among clk0~clk4.Wherein delay cell can trim, pass through change trim letter
It number can change the delay time of input signal.It can use test pattern in the present embodiment and find suitable trim value, make more
Phase clock delay relationship is met the requirements.
Each XOR gate (XOR) is connected with the output end of adjacent two delay cells (DELAY CELL), is used for
XOR logic operation is carried out to received two neighboring delay clock signals, obtains multiple wide clock pulses (p0-p3).
Wide clock pulses p0-p3's is of same size in the present embodiment, and continuous on a timeline, namely from time shaft
On, pulse p0 high level terminates, and and then p1 high level starts, and p1 high level terminates, and p2 high level starts, and so on, institute
To say being continuous.It is wide because these pulse signal high level times are equal.
Multiplex electronics include multiple multiplexers in the present embodiment, and the multiple multiplexer forms (m+1):
1 multiplex electronics, wherein the value of (m+1) is identical as the quantity of the XOR gate.That is, multiplexer composition is more
Road multiplex circuit realizes the serial process of afterbody, and the road m that multidiameter delay data prediction circuit is obtained pre-processes serial
Data carry out serial process, obtain serial data stream sout all the way.
Fig. 6 is referred to, Fig. 6 is 4:1 multiplex electronics (MUX circuit) structural schematic diagram provided in an embodiment of the present invention；
It includes 5 multiplexers, before four multiplexers receive 4 tunnels pretreatment serial data (q0-q3) and 4 tunnels respectively
Wide clock pulses (p0-p3), the value of output in the subsequent multiplexer of input value, are realized again and merge 4 circuit-switched datas
For the purpose of a circuit-switched data, to export serial data stream sout.
It should be noted that not limiting the quantity of multidiameter delay data in the present embodiment, 2 multiple side Lu Binghang can be
Data, since multi-phase clock serializer provided by the present application is capable of handling more channel parallel datas, optionally, described more
The quantity of channel parallel data is greater than or equal to 8 tunnels.In addition, the source of initial clock signal is not limited in the present embodiment, optionally,
Multi-phase clock serializer can also include clock-signal generator in the present embodiment, for exporting the initial clock signal.
In conclusion the embodiment of the present invention provides a kind of multi-phase clock serializer, it is wide by being generated using delay cell
Continuous clock pulse signal successively gates multidiameter delay data, to generate highspeed serial data stream all the way.Wherein delay cell is
Configurable, by the trim value for changing delay cell input, thus it is possible to vary the delay time of input signal.Prolong when incremented by successively
When the trim value of slow unit, several equally spaced delay clock signals can be obtained, adjacent signals carry out XOR operation generation etc.
Wide continuous clock pulse, wherein the width of clock pulses is equal to the trim step of delay cell, by adjusting the drive of delay cell
Kinetic force and series, it is ensured that the precision of trim step, and then guarantee the precision of clock-pulse width.And clock pulses
Width is equal to serial data rate.
It is pre- that multidiameter delay data are devised in the present invention while using several delay clock signals that delay cell generates
Processing circuit, the pretreatment circuit serially provide sufficient settling time for next stage while realizing that the first order is serial.
Multi-phase clock serializer structure provided by the invention is simple, easy to accomplish, does not need the complexity such as Clock dividers
Clock control circuit, and when settling time and holding by that can guarantee abundance using the internal delay clock signals generated
Between, suitable for work the signal translating system of single-frequency, the signal translating system is not limited in the present embodiment, it is optional
, the signal translating system can be storage system, has test pattern in the storage system, can use test
Mode finds suitable adjusted value (trim value), so that being more easier for wide clock pulses, does not need phaselocked loop
To guarantee.
It should be noted that the circuit needs five for generating four (or m+1) wide continuous clock pulses
(or m+2) identical delay cell delay cell, and the trim value of delay cell delay cell is 3bit (or > log2
(m+2)).When trim value is incremented to 101 from 000,5 equally spaced delay clock signals clk0, clk1 can be sequentially generated,
clk2,clk3,clk4.Adjacent signals carry out XOR operation and obtain wide continuous clock pulse p0, p1, p2, p3.
The width of clock pulses is equal to the trim step of delay cell delay cell, by adjusting the drive of delay cell
Kinetic force and series, it is ensured that the precision of trim step, and then guarantee the precision of clock-pulse width.
Fig. 7 and Fig. 8 are referred to, Fig. 7 is the structural schematic diagram of 8:1 serializer, and Fig. 8 is corresponding timing diagram.
By taking the serializer of 8:1 as an example, need when design first to convert 4 channel parallel datas for 8 circuit-switched datas, then 4 tunnels are parallel
Data are converted into 1 tunnel.In conversion process twice, to guarantee reasonable time margin, devise as shown in top half in Fig. 7
Multidiameter delay data prediction circuit 1.Clk is input clock, and D<7:0>is 8 channel parallel datas of input, is firstly introduced into D touching
The failing edge that device is sent out in clk respectively samples four circuit-switched data D<7:4>, and then sampling output dout<7:4>and d<3:0>are input to
The MUX circuit of different delays signal control.
Wherein, D<0>and dout<4>is input to the mux circuit of clock clk control, when clk is high, output data q0 etc.
In D<0>, conversely, q0 is equal to dout<4>.Similarly D<1>and dout<5>is input in the mux circuit of delayed clock clk0 control,
D<2>and dout<6>is input to the mux circuit of delayed clock clk1 control, and D<3>and dout<7>are input to delayed clock clk2
In the mux circuit of control.Clk0, clk1, clk2 are the postpones signals generated in wide continuous clock pulse-generating circuit.
The circuit realize convert 4 channel parallel data for 8 circuit-switched datas while, provide and fill for the MUX of next stage 4:1
The settling time and retention time of foot.
The four circuit-switched data q0, q1, q2, q3 and wide continuous clock arteries and veins that 8:4 multidiameter delay data prediction circuit 1 generates
The four tunnel clock pulses p0, p1, p2 of the generation of generation circuit 2 are rushed, p3 can be sent into the mux circuit 3 of 4:1 as shown in Figure 7 simultaneously.
Four tunnel clock pulses can successively select four circuit-switched datas, ultimately generate serial data stream sout.
As shown in figure 8, wide clock pulses p0-p3 is generated by clk0-clk4 exclusive or, clk0-clk4 is postponed by clk
It generates, and the delay between adjacent clock is equal to Tstep, is also equal to the cycle T bit of sout.Failing edge quilt of the D<7:4>in clk
Sampling, gives first order 8:4mux circuit to provide time enough nargin.First order mux circuit is by using different clocks control
System, ensure that the time margin of second level 4:1mux circuit.Data q1-q3 corresponding settling time is Tbit, and the retention time is
The settling time of 2Tbit, data q0 are the intrinsic delay time Tint of delay cell.
Multi-phase clock serializer provided by the invention, is applied in the signal translating system with single-frequency, when multiphase
Clock serializer includes multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；It is logical
Excessive channel parallel data pretreatment circuit pre-processes multidiameter delay data, obtains multichannel pretreatment serial data, simultaneously
Sufficient settling time is serially provided to be subsequent；And the wide continuous impulse signal generating circuit can generate it is multiple wide
Pulse signal enables multiplex electronics to be carried out multichannel pretreatment serial data according to multiple wide clock pulses final
Serial data, to obtain serial data stream.
Since multi-phase clock serializer provided in the present invention is realized only with three above module by multidiameter delay data
It is converted into serial data stream, and wide continuous impulse signal generating circuit can generate multiple delay clock signals and multiple
Wide clock pulses, so as to avoid using the clock control in the prior art with the complicated component such as phaselocked loop, frequency divider
Circuit, and then simplify the structure of multiphase serializer.Simultaneously as multidiameter delay data prediction circuit can be subsequent serial
Settling time is provided, ensure that the phase margin of clock and data.
Based on identical inventive concept, the embodiment of the present invention also provides a kind of signal translating system, including above example
Described in multi-phase clock serializer, for multidiameter delay data to be converted to serial data stream.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of multi-phase clock serializer, which is characterized in that it applies in the signal translating system with single-frequency, it is described more
Phase clock serializer includes:
Multidiameter delay data prediction circuit, wide continuous impulse signal generating circuit and multiplex electronics；
The multidiameter delay data prediction circuit receives input and the initial clock signal of multidiameter delay data；
The wide continuous impulse signal generating circuit receives the initial clock signal, and carries out to the initial clock signal
Delay, obtains multiple delay clock signals, the delay time of the two neighboring delay clock signals is identical；To adjacent two
It is of same size that the delay clock signals carry out the multiple high level of logical operation generation, and continuous multiple wide on a timeline
Clock pulses；
The multidiameter delay data prediction circuit is according to the initial clock signal and multiple delay clock signals to described more
Channel parallel data carries out at least one level serial process, obtains multichannel pretreatment serial data；
The multiplex electronics carry out multichannel pretreatment serial data according to the multiple wide clock pulses serial
Processing, obtains serial data stream.
2. multi-phase clock serializer according to claim 1, which is characterized in that the multidiameter delay data prediction circuit
Include:
Sample circuit and multiple 2:1 multiplex electronics；
The sample circuit samples the part road in the multidiameter delay data when the initial clock signal failing edge triggers
Data obtain multi-channel sampling output data；
Each 2:1 multiplex electronics receive the circuit-switched data in the multidiameter delay data in remainder；And one
Under the action of a delay clock signals, the pretreatment serial data all the way is exported.
3. multi-phase clock serializer according to claim 2, which is characterized in that the sample circuit includes multiple D triggerings
Device；
One input terminal of each d type flip flop receives the initial clock signal；Another input terminal receives the multichannel
A circuit-switched data in parallel data in partial data；
The d type flip flop be used in the initial clock signal failing edge, a circuit-switched data received to another input terminal into
Row sampling obtains sampling output data.
4. multi-phase clock serializer according to claim 1, which is characterized in that the wide continuous impulse signal generates electricity
Road includes:
Multiple delay cells and multiple XOR gates；
The delay cell receives the initial clock signal and adjusts value signal, is changed according to the adjusting value signal described first
The delay time of beginning clock signal, and export multiple delay clock signals；
Each XOR gate is connected with the output end of two adjacent delay cells, when for received two neighboring delay
Clock signal carries out XOR logic operation, obtains multiple wide clock pulses.
5. multi-phase clock serializer according to claim 4, which is characterized in that the multiplex electronics include multiple more
Path multiplexer, the multiple multiplexer form (m+1): 1 multiplex electronics, wherein the value of (m+1) with it is described different
Or the quantity of door is identical.
6. multi-phase clock serializer according to claim 1, which is characterized in that the quantity of the multidiameter delay data is greater than
Or it is equal to 8, and be 2 multiple side.
7. multi-phase clock serializer according to claim 1, which is characterized in that further include clock-signal generator, be used for
Export the initial clock signal.
8. a kind of signal translating system, which is characterized in that serial including multi-phase clock described in claim 1-7 any one
Device, for multidiameter delay data to be converted to serial data stream.
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| CN109687860B (en) | 2022-12-02 |
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