CN112600567B

CN112600567B - High-speed multichannel parallel-serial conversion circuit

Info

Publication number: CN112600567B
Application number: CN202011510470.4A
Authority: CN
Inventors: 杨海玲
Original assignee: Shanghai Weijing Electronic Technology Co ltd
Current assignee: Shanghai Weijing Electronic Technology Co ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2023-08-22
Anticipated expiration: 2040-12-18
Also published as: CN112600567A

Abstract

The invention provides a high-speed multichannel parallel-serial conversion circuit, which is characterized in that a conversion pulse signal and a half-rate quadrature clock signal are driven and copied by M parallel-serial buffer units to generate M paths of conversion control signals and M paths of half-rate control signals; m paths of parallel data signals are respectively connected to the input ends of M half-rate parallel-serial conversion circuits, M primary serial signals are output by the output ends of the M half-rate parallel-serial conversion circuits, the primary serial signals are commonly connected to the input end of a selector, the control end of the selector is connected to the half-rate quadrature clock signal, and the output end outputs a serialization signal. By generating half-rate quadrature clocks and driving the half-rate quadrature clocks to each channel, the signal interference problem of a clock driving module and the consumption of dynamic current are reduced, meanwhile, absolute matching of paths is guaranteed, and the circuit can achieve higher time sequence performance and has remarkable significance.

Description

High-speed multichannel parallel-serial conversion circuit

Technical Field

The invention relates to the technical field of power supply, in particular to a high-speed multichannel parallel-serial conversion circuit.

Background

High-speed digital systems are often used for parallel processing of multi-bit data, and when data is exchanged externally, serial IO with high-speed driving capability is required to perform high-bandwidth data transmission, which relates to application of a parallel-serial conversion circuit for converting multi-bit bus data into high-speed serial bit streams.

In order to increase the IO bandwidth, in the prior art, a multi-channel serial interface is adopted, and fig. 1 is a multi-channel parallel-serial conversion circuit based on asynchronization FIFO (First Input First Output), as shown in fig. 1, in the prior art, the multi-channel parallel-serial conversion circuit generally includes a reset synchronous circuit, M paths of asynchronous FIFOs and a balance tree, the working principle is that after all parallel-serial conversion is implemented, all the paths are driven to the positions of all the paths, the positions of the different paths are limited by the IO circuit layout width, and the maximum of the multiple paths may have a driving length of several millimeters, so that all the time sequences are aligned by automatic design software. In this configuration, the write clock DCLK of the digital FIFO is the system clock frequency, the read clock SCLK of the digital FIFO is the serial interface clock frequency, which is typically N times DCLK, and the digital FIFO needs to operate at N×T _DCLK Causing the timing constraints of the FIFO to be strained. In addition, after the parallel-to-serial conversion of the M digital FIFOs is completed, M paths of data signals need to be driven to the corresponding positions of the interfaces IO, and crosstalk and larger crosstalk can occur in the transmission processResulting in signal misalignment and reduced signal quality between the final channels.

The realization of the circuit solves the problem of time sequence alignment among the multi-channel serial data by utilizing automatic design software, absolute matching of paths cannot be achieved, alignment is difficult to ensure under all corners of PVT, and when long-distance driving transmission is carried out on the multi-channel serial data, larger dynamic current is formed, and serious signal crosstalk problem is easy to occur, so that the interface rate is influenced; and the finally realized parallel-serial conversion rate also depends on the speed of the used basic unit library, and the working speed requirement of a high-speed digital system is difficult to reach. In addition, the DDR clock is generally output by dividing the serial clock provided by the system by two, and because the path of the DDR clock is inconsistent with the data serialization path, the timing alignment is difficult, which results in that the parallel-serial conversion circuit implemented by the digital circuit forms a constraint on the IO bandwidth of the system.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a high-speed multichannel parallel-serial conversion circuit.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a high-speed multichannel parallel-serial conversion circuit, comprising: the half-rate quadrature sampling clock generation module is connected with the system reset signal, the parallel clock signal and the serial clock signal at the input end, and outputs a conversion pulse signal and a half-rate quadrature clock signal at the output end;

The clock driving module is coupled with the half-rate quadrature sampling clock generating module and comprises M cascaded parallel-serial buffer units, the conversion pulse signals and the half-rate quadrature clock signals are driven and copied by the M parallel-serial buffer units to generate M paths of conversion control signals and M paths of half-rate control signals, and M corresponds to the number of output channels and is an integer larger than 1;

the half-rate parallel-serial conversion module is coupled with the clock driving module and comprises M half-rate parallel-serial conversion circuits and a selector, wherein the M half-rate parallel-serial conversion circuits are correspondingly coupled with the M parallel-serial buffer units, the input ends of the M half-rate parallel-serial conversion circuits are connected with the M paths of conversion control signals, the M paths of half-rate control signals and the M paths of parallel data signals, the output ends of the M half-rate parallel-serial conversion circuits output M primary serial signals, the primary serial signals are commonly connected to the input end of the selector, the control end of the selector is connected with the half-rate quadrature clock signals, and the output end of the selector outputs serialization signals; wherein, the liquid crystal display device comprises a liquid crystal display device,

the path lengths of the M parallel-serial buffer units are the same;

the rising edge of the half-rate quadrature clock signal is used for serializing sampling of even digits of the parallel data signal, the falling edge is used for serializing sampling of odd digits of the parallel data signal, the period of the conversion pulse signal is equal to the period of the sampling clock of the parallel data signal, and the serializing signal is aligned with the edge of the half-rate quadrature clock signal.

Preferably, the half-rate quadrature sampling clock generation module further outputs a half-rate clock signal, the half-rate quadrature sampling clock generation module includes a reset synchronization circuit, a conversion pulse generation circuit and a quadrature clock generation circuit, an input end of the reset synchronization circuit is connected to the system reset signal, the parallel clock signal and the serial clock signal, the system reset signal is synchronized by the parallel clock signal and the serial clock signal respectively and then outputs a synchronous reset signal, the synchronous reset signal is output to a reset end of the conversion pulse generation circuit and a reset end of the quadrature clock generation circuit through an output end of the reset synchronization circuit, the serial clock signal is input to the conversion pulse generation circuit and the quadrature clock generation circuit, the conversion pulse signal is output after the conversion pulse generation circuit is synchronized by N-frequency division and the serial clock signal, the synchronous reset signal is output by the half-rate clock signal after the quadrature clock generation circuit is synchronized by two-frequency division and the serial clock signal, the half-rate clock signal is output after the half-rate clock signal is synchronized by the serial clock signal, and the half-rate clock signal is output after the half-rate quadrature clock signal is synchronized by 90 ° and the clock signal is generated after the quadrature clock signal.

Preferably, the reset synchronization circuit comprises a first reset D trigger and a second reset D trigger which are coupled; the data end of the first reset D trigger is connected with the system reset signal, the clock end is connected with the parallel clock signal, the output end outputs a primary synchronous signal to the data end of the second reset D trigger, the clock end of the second reset D trigger is connected with the serial clock signal, and the primary synchronous signal is synchronized by the serial clock signal and then outputs the synchronous reset signal.

Preferably, the conversion pulse generating circuit includes a first frequency divider, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop, and an and gate; the clock ends of the first frequency divider, the first synchronous D trigger and the third synchronous D trigger are commonly connected with the serial clock signal, the reset zero end of the first synchronous D trigger, the second synchronous D trigger and the third synchronous D trigger are connected with the primary synchronous signal, the reset end of the first frequency divider is connected with the synchronous reset signal, the output end of the first frequency divider outputs a frequency division signal to the data input end of the first synchronous D trigger, the output end of the first synchronous D trigger outputs a primary synchronous signal to the data input end of the second synchronous D trigger and the first input end of the AND gate, the output end of the second synchronous D trigger outputs a secondary synchronous signal to the second input end of the AND gate, the output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger, and the output end of the third synchronous D trigger outputs the conversion pulse signal.

Preferably, the secondary synchronization signal is an inverted signal that lags the primary synchronization signal by one serial clock cycle.

Preferably, the quadrature clock generation circuit includes a second frequency divider, a first quadrature D flip-flop, and a second quadrature D flip-flop; the clock ends of the second frequency divider, the first orthogonal D trigger and the second orthogonal D trigger are commonly connected with the serial clock signal, the reset zero clearing ends of the first orthogonal D trigger and the second orthogonal D trigger are connected with the primary synchronous signal, the reset end of the second frequency divider is connected with the synchronous reset signal, the output end outputs a two-frequency division signal to the data input end of the first orthogonal D trigger, the output end of the first orthogonal D trigger outputs the half-rate clock signal to the data input end of the second orthogonal D trigger, and the output end of the second orthogonal D trigger outputs the half-rate orthogonal clock signal.

Preferably, the circuit further comprises a DDR clock generation circuit, and the half-rate quadrature clock signal is driven and output to the DDR clock generation circuit through the buffer unit.

Preferably, the DDR interface clock generating circuit includes a DDR selector, a control terminal of the DDR selector is connected to the half-rate clock signal, a first input terminal is connected to the low level, a second input terminal is connected to the high level, and an output terminal outputs a DDR clock signal, and the DDR clock signal is phase-aligned with the half-rate clock signal.

Preferably, the structure of the buffer unit includes an inverter structure or a CML structure.

Preferably, the half-rate parallel-serial conversion circuit comprises a first conversion circuit, a second conversion circuit and a conversion selector which are coupled, wherein the output ends of the first conversion circuit and the second conversion circuit are respectively connected with the input end of the selector, the output end of the first conversion circuit outputs a first conversion signal, the output end of the second conversion circuit outputs a second conversion signal, the input end of the selector is respectively connected with the first conversion signal and the second conversion signal, the control end is connected with the half-rate quadrature clock signal, and the output end of the selector outputs the serialization signal; wherein, the liquid crystal display device comprises a liquid crystal display device,

the half-rate quadrature clock signal is low level, and the serialization signal is the first conversion signal; the half-rate quadrature clock signal is high level, and the serialization signal is the second conversion signal.

According to the technical scheme, the invention provides the high-speed multichannel parallel-serial conversion circuit, delay among generation of the conversion pulse signal, the half-rate clock signal and the half-rate quadrature clock signal and rising edge of the parallel clock signal is kept in a plurality of serial clock cycles and is synchronous with the serial clock signal, so that control of internal sampling time sequence is realized. Meanwhile, by generating half-rate quadrature clocks and driving the half-rate quadrature clocks to each channel, the signal interference problem of a clock driving module and the consumption of dynamic current are reduced, meanwhile, absolute matching of paths is guaranteed, and higher time sequence performance of the circuit can be realized. In addition, the half-rate parallel-serial conversion module realizes a half-rate architecture through the coupled first conversion circuit, the second conversion circuit and the conversion selector, further reduces dynamic current consumption, is favorable for better time sequence alignment of a clock and a data channel, and has remarkable significance.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art asynchronous FIFO-based multichannel parallel-serial conversion circuit

FIG. 2 is a schematic diagram of a high-speed multi-channel parallel-to-serial conversion circuit according to an embodiment of the present invention

FIG. 3 is a schematic diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention

FIG. 4 is a timing chart corresponding to an embodiment of a switching control signal generating circuit according to the present invention

FIG. 5 is a timing diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention

FIG. 6 is a schematic diagram of clock tree balancing according to an embodiment of the invention

FIG. 7 is a schematic diagram of a half-rate parallel-to-serial conversion module according to an embodiment of the invention

FIG. 8 is a timing diagram corresponding to the half rate parallel to serial conversion module of FIG. 7

FIG. 9 is a schematic diagram of a DDR clock generation circuit according to an embodiment of the invention

Detailed Description

In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.

In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.

To make the objects, technical solutions and advantages of the present invention more apparent, a detailed description of the specific embodiments of the present invention will be given below with reference to the accompanying drawings, and fig. 2 shows a schematic diagram of a high-speed multi-channel parallel-serial conversion circuit according to an embodiment of the present invention. The high-speed multichannel parallel-serial conversion circuit comprises: a half-rate quadrature sampling clock generation module 1, a clock driving module 2 and a half-rate parallel-serial conversion module 3.

In this embodiment, the half-rate quadrature sampling clock generation module 1 is coupled to the clock driving module 2, and has an input terminal connected to the system reset signal RST, the parallel clock signal DCLK and the serial clock signal SCLK, and an output terminal outputting the switching pulse signal div_sel, the half-rate clock signal ddrclk_i and the half-rate quadrature clock signal ddrclk_q to the clock driving module 2. The delays between the generation of the converted pulse signal div_sel, the half-rate clock signal and the half-rate quadrature clock signal and the rising edge of the parallel clock signal DCLK are maintained within a number of serial clock cycles and are all clock-synchronized with the serial clock signal, thereby realizing control of internal sampling timing. In another embodiment, the output terminal of the rate quadrature sampling clock generation block 1 outputs a switching pulse signal div_sel and a half rate quadrature clock signal ddrclk_q to the clock driving block 2.

In this embodiment, the clock driving module 2 receives the switching pulse signal DIV_SEL, the half-rate clock signal DDRCLK_I and the half-rate quadrature clock signal DDRCLK_Q, and outputs a switching control signal DIV_SEL < M-1:0>, a half-rate control signal DDRCLK_Q < M-1:0> and a half-rate clock signal DDRCLK_I. Wherein M is an integer greater than 1, representing the number of high-speed IO data channels.

As shown in fig. 2, in this embodiment, the clock driving module 2 includes M parallel-serial buffer units (not shown) in cascade connection, where the path lengths of the M parallel-serial buffer units are the same, and M corresponds to the number of output channels and is an integer greater than 1. The conversion pulse signal div_sel and the half-rate quadrature clock signal ddrclk_q are driven and copied by the M parallel-serial buffer units to generate M paths of conversion control signals and M paths of half-rate control signals, and the conversion control signal div_sel < M-1:0> and the half-rate control signal ddrclk_q < M-1:0> are output to the input end of the half-rate parallel-serial conversion module 3. The high-speed multichannel parallel-serial conversion circuit can also comprise 1 DDR clock generation circuit 4 according to a serial IO protocol used by the system if the system supports forward clock transmission; if the system does not support forward clock transfer, then DDR interface clock generation circuitry is not required. In this embodiment, the half-rate clock signal ddrclk_i is driven by 1 clock buffer units and then output to the input end of the DDR clock generating circuit 4, where the path length of the clock buffer units is the same as that of the parallel-serial buffer units.

The half-rate parallel-serial conversion module 3 comprises M half-rate parallel-serial conversion circuits and a selector, wherein the M half-rate parallel-serial conversion circuits and the selector are correspondingly coupled with the M parallel-serial buffer units, M paths of parallel data signals D0< N-1:0> -DM-1<N-1:0 > are respectively connected to the input ends of the M paths of half-rate parallel-serial conversion circuits 3, N is an integer larger than 1 and represents the bit width of the parallel data signals, and M primary serial signals S < M-1:0> are output by the output ends 3 of the M half-rate parallel-serial conversion circuits.

Fig. 3 is a schematic diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention, and as shown in fig. 3, the half-rate quadrature sampling clock generation circuit 1 includes a reset synchronization circuit 11, a transition pulse generation circuit 12, and a quadrature clock generation circuit 13. The system reset signal RST is synchronized by a parallel clock signal DCLK and a serial clock signal SCLK, and then outputs a synchronous reset signal rst_syn, wherein the synchronous reset signal rst_syn is output to the reset end of the conversion pulse generating circuit 12 and the reset end of the quadrature clock generating circuit 13 through the output end of the reset synchronizing circuit 11, the serial clock signal SCLK is input to the conversion pulse generating circuit and the quadrature clock generating circuit, the synchronous reset signal rst_syn is output to a conversion pulse signal div_sel after the conversion pulse generating circuit is synchronized by the serial clock signal SCLK through N frequency division, the synchronous reset signal rst_syn is output to the half-rate clock signal ddrclk_i after the quadrature clock generating circuit is synchronized by two frequency division and the serial clock signal, the half-rate clock signal ddrclk_i is output to the half-rate quadrature clock signal ddrclk_q after the serial clock signal SCLK is synchronized, the half-rate quadrature clock signal ddrclk_q is phase-delayed from the half-rate clock signal 90 ° and the half-rate quadrature clock signal edge parallel to the data edge of the parallel data.

As shown in fig. 3, the input terminal of the reset synchronization circuit 11 is connected to the system reset signal RST, the parallel clock signal DCLK and the serial clock signal SCLK, wherein the system reset signal RST is synchronized to the parallel clock signal DCLK to control the start of parallel data serialization, and is synchronized to the serial clock signal SCLK to generate a synchronous reset signal rst_syn having a timing relationship with the parallel clock signal DCLK and the serial clock signal SCLK, respectively, and the synchronous reset signal rst_syn is connected to the reset terminals of the switching pulse generating circuit and the quadrature clock generating circuit to control the generation of the switching pulse signal div_sel, the half-rate clock signal ddrclk_i and the half-rate quadrature clock signal ddrclk_q, respectively, and the delay between the generation of the switching pulse signal div_sel, the half-rate clock signal and the rising edge of the parallel clock signal DCLK is kept within several serial clock cycles, and is synchronized with the serial clock signal, respectively, thereby realizing internal control of sampling.

The reset synchronization circuit 11 comprises a first reset D trigger and a second reset D trigger which are coupled; the data end of the first reset D trigger is connected to the system reset signal RST, the clock end is connected to the parallel clock signal DCLK, the output end outputs a primary synchronizing signal RST_1 to the data end of the second reset D trigger, the clock end of the second reset D trigger is connected to the serial clock signal SCLK, the primary synchronizing signal RST_1 is synchronized by the serial clock signal SCLK and then outputs a synchronizing reset signal RST_SYN, wherein the clock period of the parallel clock signal DCLK is T _DCLK The clock period of the serial clock signal SCLK is T _SCLK 。

The switching pulse generating circuit 12 includes a first frequency divider 121, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop, and an and gate. In this embodiment, the first frequency divider is an N frequency divider, N corresponds to the number of bits input to the parallel bus, and N is an integer greater than 1. The clock terminals of the first frequency divider 121, the first synchronous D flip-flop and the third synchronous D flip-flop are commonly connected to the serial clock signal SCLK, the reset clear terminals of the first synchronous D flip-flop, the second synchronous D flip-flop and the third synchronous D flip-flop are connected to the primary synchronous signal rst_1, the reset terminal of the first frequency divider is connected to the synchronous reset signal, the serial clock signal SCLK generates a signal frequency division signal div_n synchronous with the serial clock signal SCLK after passing through the first frequency divider, and the output terminal of the first frequency divider outputs the frequency division signal div_n. For a system with parallel data bit width of N bits, T is satisfied _DCLK ＝N*T _SCLK The synchronous reset signal is maintained within 1-2 serial clock cycles with a phase difference controlling the rising edge of the frequency division signal div_n and the rising edge of the parallel clock signal DCLK.

Fig. 4 is a timing chart corresponding to an embodiment of a conversion control signal generating circuit according to an embodiment of the present invention, please refer to fig. 3 and 4 in combination, the frequency division signal div_n is output to the data input terminal of the first synchronous D flip-flop, the output terminal of the first synchronous D flip-flop outputs a first-stage synchronization signal div_syn_0 to the data input terminal of the second synchronous D flip-flop and the first input terminal of the and gate, the output terminal of the second synchronous D flip-flop outputs a second-stage synchronization signal div_syn_1 to the second input terminal of the and gate, and the second-stage synchronization signal div_syn_1 is an inverted signal delayed by 1 clock cycle of the serial clock signal SCLK from the first-stage synchronization signal div_syn_0. The output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger. The conversion signal is a signal with a pulse width of 1 SCLK period and a period of N SCLK periods, the conversion signal is connected to the input end of the third synchronous D trigger and is synchronously sampled by SCLK, the output end of the third synchronous D trigger outputs a conversion pulse signal DIV_SEL, the period of the conversion pulse signal DIV_SEL is equal to the period of the parallel data sampling clock signal, and the serialization signal is aligned with the edge of the half-rate quadrature clock signal.

This embodiment represents only one implementation of the present invention, where the first frequency divider can freely select various circuit implementation structures, and the internal synchronization unit can be flexibly adjusted according to the timing constraint of the actual circuit.

In this embodiment, the quadrature clock generation circuit 13 includes a second frequency divider, a first quadrature D flip-flop, and a second quadrature D flip-flop.

As shown in fig. 3, clock terminals of the second frequency divider, the first orthogonal D flip-flop and the second orthogonal D flip-flop are commonly connected to the serial clock signal SCLK, reset clear terminals of the first orthogonal D flip-flop and the second orthogonal D flip-flop are connected to the primary synchronization signal, reset terminals of the second frequency divider are connected to the synchronization reset signal, and the serial clock signal SCLK generates a period of n×t through the second frequency divider _SCLK The output end of the second frequency divider outputs to the data input end of the first quadrature D flip-flop, and the phase difference between the rising edge of the frequency division signal and the rising edge of the parallel clock signal DCLK is kept within 1 SCLK period. Fig. 5 is a timing chart of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention, as shown in fig. 5, the half-rate clock signal ddrclk_i is generated by sampling the half-rate clock signal through SCLK synchronization, the half-rate clock signal ddrclk_i is generated after the half-rate clock signal is synchronized by the serial clock signal SCLK, the output terminal of the first quadrature D flip-flop outputs the half-rate clock signal ddrclk_i to the data input terminal of the second quadrature D flip-flop, and the half-rate clock signal ddrclk_i is sampled through the inverse clock of the serial clock signal SCLK, that is, the half-rate clock signal ddrclk_q is obtained after the half-rate clock signal ddrclk_i is synchronized through the inverse phase of SCLK, and the output terminal of the second quadrature D flip-flop outputs the half-rate quadrature clock signal ddrclk_q.

In this embodiment, the clock driving circuit 2 is a balanced tree, and the path lengths from the half-rate quadrature sampling clock generating circuit 1 to the M data channels and the number of parallel-serial buffer units are precisely matched, so as to realize precise matching.

Fig. 6 is a schematic diagram of clock tree balancing according to an embodiment of the present invention, as shown in fig. 6, in this embodiment, the clock driving circuit 2 adopts a balanced binary tree structure to realize absolute balance between paths, the clock driving module 2 includes M parallel-serial buffer units (not shown) in cascade connection, and the switching pulse signal div_sel and the half-rate quadrature clock signal are driven and copied by the M parallel-serial buffer units to generate M switching control signals and M half-rate control signals, where the number of buffer units on each driving path can be flexibly set according to load conditions and timing requirements. The buffer circuit can be implemented in various forms, and the structure of the buffer unit includes an inverter structure or a CML structure, and one common implementation circuit is an inverter structure. The structure of the buffer unit can flexibly set the driving circuit structure according to the frequency and the load condition of the driving signal, and is not limited to an inverter structure or a CML structure. The invention firstly generates half-rate quadrature clock signal DDRCLK_Q and drives the half-rate quadrature clock signal DDRCLK_Q to each channel by advancing the balance tree, thereby reducing the signal interference problem and the consumption of dynamic current on the balance tree.

The half-rate parallel-serial conversion module comprises M half-rate parallel-serial conversion circuits and a selector, wherein the M half-rate parallel-serial conversion circuits are correspondingly coupled with the M parallel-serial buffer units, M paths of parallel data signals are respectively connected to the input ends of the M half-rate parallel-serial conversion circuits, M primary serial signals are output by the output ends of the M half-rate parallel-serial conversion circuits, the primary serial signals are commonly connected to the input ends of the selector, the control end of the selector is connected to the half-rate orthogonal clock signal, and the serialization signals are output by the output ends.

The half-rate parallel-serial conversion circuit comprises a first conversion circuit, a second conversion circuit and a conversion selector which are coupled. The output ends of the first conversion circuit and the second conversion circuit are respectively connected with the input end of the selector, the output end of the first conversion circuit outputs a first conversion signal, the output end of the second conversion circuit outputs a second conversion signal, the input end of the selector is respectively connected with the first conversion signal and the second conversion signal, the control end is connected with the half-rate quadrature clock signal, and the output end outputs the serialization signal; wherein the half-rate quadrature clock signal is low level, and the serialization signal is the first conversion signal; the half-rate quadrature clock signal is high level, and the serialization signal is the second conversion signal.

In one embodiment, the half-rate parallel-to-serial conversion circuit includes (n+1) D flip-flop cells and (N-1) selector cells. Wherein (N-1) selectors and N D flip-flop units are used to realize sampling serialization paths of N-bit parallel data, and the remaining 1D flip-flop units are used to generate a conversion control signal synchronized with the quadrature clock. Wherein the rising edge of the half-rate quadrature clock signal ddrclk_q is used for the serialized sampled output of the even bits of the parallel data signal and the falling edge of the half-rate quadrature clock signal ddrclk_q is used for the serialized sampled output of the odd bits of the parallel data signal. For even bit serialization sampling output paths, when the conversion control signal DIV_SEL is low, the whole path is used as a shifter circuit, data is sequentially output from left to right, and when the conversion control signal DIV_SEL is high, even bits of parallel data are updated into each DFF on the path. Since the period of DIV_SEL is equal to the period of the parallel data sampling clock signal, it is ensured that each bit of information of the parallel data can be updated to output. The ODD bits operate on the same principle as the even bits, converting the control signal to DIV SEL ODD. Finally, the outputs of the odd and even two paths are combined through a selector controlled by a half-rate quadrature clock signal DDRCLK_Q, and a final serialization output serialization signal SOUT is obtained. The serialization signal SOUT is edge-aligned with the half-rate quadrature clock signal ddrclk_q, maintaining only one selector cell delay.

The input signals of the half-rate parallel-serial conversion circuit comprise M paths of parallel data signals D0< N-1:0> -DM-1<N-1:0 > besides a half-rate control signal DDRCLK_Q < M-1:0> and a conversion control signal DIV_SEL < M-1:0> from a clock tree, and the signals are converted into serial signals S < M-1:0> after parallel-serial conversion and are respectively output.

Fig. 7 is a schematic diagram of a half-rate parallel-serial conversion module according to an embodiment of the present invention, as shown in fig. 7, in this embodiment, N is an even number, and the first conversion circuit and the second conversion circuit each include N/2 conversion D flip-flop units and (N/2-1) conversion selector units. Wherein the rest (N/2-1) of the repeating cascade units are composed of one conversion selector plus one conversion D trigger except the conversion D trigger connected with the highest odd bit and the highest even bit data.

The input end of the conversion D trigger is sequentially connected with D < N-2>, DQ < N-4> … … DQ <0>, the output signals are sequentially Q < N-2>, Q < N-4> … … Q <0>, the input end of the conversion selector is respectively connected with one bit from the previous stage conversion D trigger and the parallel data signal, and the control signal of the conversion selector is DIV_SEL. The switching selector outputs the sampling output signals Q < N-2>, Q < N-4> … … Q <2> of the preceding stage D flip-flop, respectively, when DIV_SEL is low, and outputs the parallel data signals D < N-4>, D < N-6> … … D <0>, when DIV_SEL is high. Similarly, the second switching circuit is from the input end to the output end, the input end of the switching D trigger is sequentially connected with D < N-1>, DQ < N-3> … … DQ <1>, the output signals are sequentially Q < N-1>, Q < N-3> … … Q <1>, the input end of the switching selector MUX is respectively connected with one bit from the front-stage D trigger and the parallel data signal, the control signal of the switching selector is DIV_SEL_ODD, the signal is a signal of DIV_SEL after being synchronized by half-rate orthogonal clock signal DDRCLK_Q, and the signal is one serial clock period TSCLK later than the DIV_SEL signal. The switching selector outputs the sampling output signals Q < N-1>, Q < N-3> … … Q <3> of the previous stage D flip-flop, respectively, when DIV_SEL_ODD is low, and outputs the parallel data signals D < N-3>, D < N-5> … … D <1>, respectively, when DIV_SEL_ODD is high. The final output signal of the first conversion circuit is Q <0>, the final output signal of the second conversion circuit is Q <1>, the two signals of the first conversion circuit and the second conversion circuit are connected to two input ends of a conversion selector of the last stage, the conversion selector selects the control signal to be a half-rate quadrature clock signal DDRCLK_Q, when the half-rate quadrature clock signal DDRCLK_Q is low, the signal Q <0> of the first conversion circuit is selected to be output, and when the half-rate quadrature clock signal DDRCLK_Q is high, the signal Q <1> of the second conversion circuit is selected to be output. The half-rate parallel-serial conversion module adopts a half-rate architecture, further reduces dynamic current consumption, and is favorable for better time sequence alignment of clocks and data channels.

In this embodiment, the sampling clock of the D flip-flop of the first conversion circuit is a half-rate quadrature clock signal ddrclk_q, and the sampling clock of the D flip-flop of the second conversion circuit is an inverse signal of the half-rate quadrature clock signal ddrclk_q. The rising edge of the half-rate quadrature clock signal ddrclk_q is used for serializing samples of even bits of the parallel data signal, the falling edge is used for serializing samples of odd bits of the parallel data signal, the period of the conversion pulse signal div_sel is equal to the period of the sampling clock of the parallel data signal, and the serializing signal is aligned with the edges of the half-rate quadrature clock signal.

In another embodiment, N is an odd number, the first switching circuit includes (N-1)/2D flip-flop cells and ((N-1)/2-1) switching selector cells, and the second switching circuit includes (N+1)/2 switching D flip-flop cells and ((N+1)/2-1) switching selector cells. Similarly, in the first switching circuit and the second switching circuit, the following cascade units are each constituted by a switching selector plus a switching D flip-flop except for the switching D flip-flop to which the highest odd bit and the highest even bit are connected. And the input end of the conversion D trigger is sequentially connected with D < N-1>, DQ < N-3> … … DQ <0> from the input end to the output end of the second conversion circuit, and output signals are sequentially Q < N-1>, Q < N-3> … … Q <0>. The control signal of the switching selector is div_sel. The selector outputs the sampled output signals Q < N-1>, Q < N-3> … … Q <2> of the pre-stage conversion D flip-flop, respectively, when DIV_SEL is low, and the conversion selector outputs the parallel data signals D < N-3>, D < N-5> … … D <0>, respectively, when DIV_SEL is high. In the first conversion circuit, from the input end to the output end, the input end of the conversion D trigger is sequentially connected with D < N-2>, DQ < N-4> … … DQ <1>, and the output signals are sequentially Q < N-2>, Q < N-4>, … … Q <1>. The control signal of the switching selector is div_sel_odd. The switching selector outputs the sampling output signals Q < N-2>, Q < N-4> … … Q <3> of the preceding switching D flip-flop when DIV_SEL_ODD is low, respectively, and outputs the parallel data signals D < N-4>, D < N-6> … … D <1> when DIV_SEL_ODD is high. The final output signal of the second conversion circuit is Q <0>, the final output signal of the first conversion circuit is Q <1>, the two signals of the first conversion circuit and the second conversion circuit are connected to two input ends of a conversion selector of the last stage, the conversion selector selects the control signal to be a half-rate quadrature clock signal DDRCLK_Q, when the half-rate quadrature clock signal DDRCLK_Q is low, the Q <0> output of the second conversion circuit signal is selected, and when the half-rate quadrature clock signal DDRCLK_Q is high, the signal Q <1> output of the first conversion circuit is selected.

Fig. 8 is a timing chart corresponding to the half-rate parallel-serial conversion module of fig. seven, and as shown in fig. 8, the serializing output sequence of the above embodiment is that data starts from a low bit, and finally outputs a high bit. In some high-speed IO protocols, the requirement of outputting the high-order bits first is not excluded, and then the connection mode of the input signals D < N-1> to D <0> in the above embodiments can be changed to the corresponding connection mode of D <0> to D < N-1>, so that the serialization output from the high-order bits can be realized.

In this embodiment, the system supports forward clock transmission, the high-speed multi-channel parallel-serial conversion circuit further includes 1 DDR clock generating circuit, the half-rate quadrature sampling clock generating module further outputs a half-rate clock signal, the clock driving module further includes 1 clock buffer unit to drive the half-rate clock signal, that is, the clock driving module of the present invention includes (m+1) buffer units in total, and path lengths of the (m+1) buffer units are the same. In this embodiment, the half-rate clock signal is output to the DDR clock generating circuit after being driven by the buffer unit; the DDR interface clock generation circuit comprises a DDR selector, wherein the control end of the DDR selector is connected with the half-rate clock signal, the first input end of the DDR selector is connected with the low level, the second input end of the DDR interface clock generation circuit is connected with the high level, and the output end of the DDR selector outputs the DDR clock signal. The DDR clock signal is phase aligned with the half rate clock signal.

Fig. 9 is a schematic diagram of a DDR clock generating circuit according to an embodiment of the present invention, in which the DDR interface clock generating circuit includes a clock selector, a control terminal of the clock selector is connected to ddrclk_i, input terminals of the clock selector are respectively connected to a fixed low level and a fixed high level, the clock outputs a low half period when the half rate clock signal ddrclk_i is at a low level, and the clock outputs a high half period when the half rate clock signal ddrclk_i is at a high level. The output signal SCLK is thus phase-aligned with the half-rate clock signal ddrclk_i, keeping only one selector unit delay. The delay is consistent with the data channel. Accurate matching in time sequence is realized, and a more accurate channel alignment standard is achieved.

Based on the high-speed multichannel parallel-serial conversion circuit, the delay among the generation of the conversion pulse signal, the half-rate clock signal and the half-rate quadrature clock signal and the rising edge of the parallel clock signal is kept in a plurality of serial clock cycles and is synchronous with the serial clock signal, so that the control of internal sampling time sequence is realized. Meanwhile, by advancing the balance tree, half-rate quadrature clocks are generated and driven to each channel, the signal interference problem and the consumption of dynamic current on the balance tree are reduced, meanwhile, absolute matching of paths is guaranteed, and higher time sequence performance of the circuit can be realized. In addition, the half-rate parallel-serial conversion module comprises M half-rate parallel-serial conversion circuits and a selector, wherein the M half-rate parallel-serial conversion circuits and the selector are correspondingly coupled with the M parallel-serial buffer units, M paths of parallel data signals are respectively connected to the input ends of the M half-rate parallel-serial conversion circuits, the output ends of the M half-rate parallel-serial conversion circuits output M primary serial signals, the primary serial signals are commonly connected to the input ends of the selector, the control end of the selector is connected to the half-rate quadrature clock signals, the output end outputs the serialization signals, the half-rate architecture is realized through the first conversion circuit, the second conversion circuit and the conversion selector which are coupled, dynamic current consumption is further reduced, and better time sequence alignment of clocks and data channels is facilitated, and the half-rate parallel-serial conversion module has remarkable significance.

The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-speed multichannel parallel-serial conversion circuit, comprising:

the half-rate quadrature sampling clock generation module is connected with the system reset signal, the parallel clock signal and the serial clock signal at the input end, and outputs a conversion pulse signal and a half-rate quadrature clock signal at the output end;

the path lengths of the M parallel-serial buffer units are the same;

2. The high-speed multi-channel parallel-serial conversion circuit of claim 1, wherein the half-rate quadrature sampling clock generation module further outputs a half-rate clock signal, the clock driving module further comprises 1 clock buffer units driving the half-rate clock signal, the half-rate quadrature sampling clock generation module comprises a reset synchronization circuit, a conversion pulse generation circuit and a quadrature clock generation circuit, an input terminal of the reset synchronization circuit is connected to the system reset signal, the parallel clock signal and the serial clock signal, the system reset signal is synchronized by the parallel clock signal and the serial clock signal respectively, the synchronous reset signal is output to a reset terminal of the conversion pulse generation circuit and a reset terminal of the quadrature clock generation circuit through an output terminal of the reset synchronization circuit, the serial clock signal is input to the conversion pulse generation circuit and the quadrature clock generation circuit, the synchronous reset signal is synchronized by the conversion pulse signal after the conversion pulse generation circuit is divided by N and the serial clock signal, the synchronous reset signal is output to the half-rate clock signal after the quadrature clock signal is divided by two times, the half-rate clock signal is output by the quadrature clock signal after the half-rate clock signal is synchronized by half-rate, and the quadrature clock signal is output to the half-rate clock signal after the quadrature clock signal is synchronized by half-rate.

3. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, wherein the reset synchronization circuit comprises a first reset D flip-flop and a second reset D flip-flop coupled; the data end of the first reset D trigger is connected with the system reset signal, the clock end is connected with the parallel clock signal, the output end outputs a primary synchronous signal to the data end of the second reset D trigger, the clock end of the second reset D trigger is connected with the serial clock signal, and the primary synchronous signal is synchronized by the serial clock signal and then outputs the synchronous reset signal.

4. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, wherein the conversion pulse generation circuit comprises a first frequency divider, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop, and an and gate; the clock ends of the first frequency divider, the first synchronous D trigger and the third synchronous D trigger are commonly connected with the serial clock signal, the reset zero-clearing ends of the first synchronous D trigger, the second synchronous D trigger and the third synchronous D trigger are connected with the primary synchronous signal, the reset end of the first frequency divider is connected with the synchronous reset signal, the output end of the first frequency divider outputs a frequency division signal to the data input end of the first synchronous D trigger, the output end of the first synchronous D trigger outputs a primary synchronous signal to the data input end of the second synchronous D trigger and the first input end of the AND gate, the output end of the second synchronous D trigger outputs a secondary synchronous signal to the second input end of the AND gate, the output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger, and the output end of the third synchronous D trigger outputs the conversion pulse signal.

5. The high-speed multi-channel parallel-to-serial conversion circuit of claim 4, wherein the secondary synchronization signal is an inverted signal that lags the primary synchronization signal by one serial clock cycle.

6. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, wherein the quadrature clock generation circuit comprises a second frequency divider, a first quadrature D flip-flop, and a second quadrature D flip-flop; the clock ends of the second frequency divider, the first orthogonal D trigger and the second orthogonal D trigger are commonly connected with the serial clock signal, the reset zero clearing end of the first orthogonal D trigger and the second orthogonal D trigger is connected with a primary synchronous signal, the reset end of the second frequency divider is connected with the synchronous reset signal, the output end outputs a two-frequency dividing signal to the data input end of the first orthogonal D trigger, the output end of the first orthogonal D trigger outputs the half-rate clock signal to the data input end of the second orthogonal D trigger, and the output end of the second orthogonal D trigger outputs the half-rate orthogonal clock signal.

7. The high-speed multi-channel parallel-to-serial conversion circuit according to claim 2, further comprising a DDR clock generation circuit, the half-rate clock signal being driven out to the DDR clock generation circuit via the buffer unit.

8. The high-speed multi-channel parallel-to-serial conversion circuit of claim 7, wherein the DDR clock generation circuit comprises a DDR selector having a control terminal coupled to the half-rate clock signal, a first input terminal coupled to a low level, a second input terminal coupled to a high level, and an output terminal outputting a DDR clock signal, the DDR clock signal being phase-aligned with the half-rate clock signal.

9. The high-speed multi-channel parallel-to-serial conversion circuit of claim 1, wherein the structure of the buffer unit comprises an inverter structure or a CML structure.

10. The high-speed multi-channel parallel-to-serial conversion circuit according to claim 1, wherein the half-rate parallel-to-serial conversion circuit comprises a first conversion circuit, a second conversion circuit and a conversion selector which are coupled, wherein the output ends of the first conversion circuit and the second conversion circuit are respectively connected with the input end of the selector, the output end of the first conversion circuit outputs a first conversion signal, the output end of the second conversion circuit outputs a second conversion signal, the input end of the selector is respectively connected with the first conversion signal and the second conversion signal, the control end is connected with the half-rate orthogonal clock signal, and the output end of the selector outputs the serialization signal; wherein the half-rate quadrature clock signal is low level, and the serialization signal is the first conversion signal; the half-rate quadrature clock signal is high level, and the serialization signal is the second conversion signal.