JP4477372B2 - Signal processing circuit - Google Patents

Description

  The present invention relates to a signal processing circuit, and in particular, signal processing capable of performing signal transmission between LSI chips, signal transmission between a plurality of elements and circuit blocks in a chip, and signal transmission between boards and housings at high speed. Regarding the circuit.

(First background art)
The performance of components that make up computers and other information processing equipment has greatly improved. For example, the performance of SRAM, DRAM, processor, and switching LSI can be improved. Along with this, unless the signal transmission speed between these components or elements is improved, the performance of the system cannot be improved. For example, the speed gap between a memory such as SRAM or DRAM and a processor tends to increase, and in recent years, this speed gap is becoming an obstacle to improving the performance of computers. Further, not only the signal transmission between these chips but also the signal transmission speed between the elements and circuit blocks in the chip has become a major factor limiting the performance of the chip as the chip becomes larger. Furthermore, signal transmission between the peripheral device and the processor / chipset is also an element that limits the performance of the entire system.

  Further, in a communication backbone device, the signal bandwidth to be processed is a large value from 10 Gb / s to 40 Gb / s per channel. Since signals enter and exit these devices from a plurality of channels, the signal bandwidth that inevitably enters and exits a specific processing chip within the device reaches several hundred Gb / s. In order to transmit such a large-capacity signal, a signal transmission speed of several Gb / s to several tens Gb / s per signal line is required in these devices.

  A receiving circuit for receiving a high-speed signal and converting it to a lower-speed parallel signal is a major technical problem when transmitting and receiving such a high-speed signal (this is often referred to as a demultiplexer because demultiplexing is performed) Design. For example, in order to convert a high-speed signal of 40 Gb / s to a parallel signal, it is necessary to operate a high-speed comparator at very short time intervals to receive and determine the signal.

  Currently, receiver circuits for speeds from several Gb / s to 10 Gb / s are implemented using CMOS circuit technology. In a higher speed region, a compound semiconductor or SiGe mixed crystal semiconductor element is generally used. However, it is desired to realize a CMOS circuit because of cost and possibility of integration with a large-scale integrated circuit.

FIG. 42 shows the configuration of a demultiplexer according to the prior art. The demultiplexer circuits 4201, 4202, and 4203 have the same configuration, and convert a 1-bit input serial signal into a 2-bit parallel signal. The input signal is output as a first output signal through the master latch 4211, the slave latch 4212, and the master latch 4213, and is output as a second output signal through the master latch 4214 and the slave latch 4215. The latches 4211, 4213, and 4215 latch in synchronization with the rising edge of the clock signal. The latches 4212 and 4214 latch in synchronization with the falling edge of the clock signal. Details of the configuration of the latches 4111 to 4215 will be described later with reference to FIG.

  The frequency divider 4204 generates the 5 GHz clock signal CLK1 and the 2.5 GHz clock signals CLK2 and CLK_OUT based on the 10 GHz clock signal CLK_IN. The 10 GHz clock signal CLK_IN is input to the clock terminal of the flip-flop 4231. An inverter 4232 is connected between the output terminal and the input terminal of the flip-flop 4231. The flip-flop 4231 outputs a 5 GHz clock signal CLK1. The 5 GHz clock signal CLK1 is input to the clock terminal of the flip-flop 4241. An inverter 4242 is connected between the output terminal and the input terminal of the flip-flop 4241. The flip-flop 4241 outputs 2.5 GHz clock signals CLK2 and CLK_OUT.

  The demultiplexer circuit 4201 inputs a 10 Gb / s (bit / second) input signal DATA_IN in synchronization with the 5 GHz clock signal CLK1 and outputs 2-bit output signals D10 and D11. For example, the output signal D10 includes even-numbered data and the output signal D11 includes odd-numbered data.

  The demultiplexer circuit 4202 receives the input signal D10 in synchronization with the 2.5 GHz clock signal CLK2, and outputs 2-bit output signals D0 and D2. The demultiplexer circuit 4203 receives the input signal D11 in synchronization with the 2.5 GHz clock signal CLK2, and outputs 2-bit output signals D1 and D3. That is, the 1-bit serial signal DATA_IN is converted into 4-bit parallel signals D0, D1, D2, and D3. The input signal DATA_IN is converted in the order of data D0, D1, D2, D3.

  FIG. 43 shows the configuration of the latches 4211 to 4215. This latch is a differential latch (CML latch), latches the differential input signals in and inx in synchronization with the differential clock signals clk and clkx, and outputs the differential output signals out and outx.

  Hereinafter, a MOS field effect transistor (FET) is simply referred to as a transistor. The p-channel transistor 4301b has a gate connected to the ground, a source connected to the power supply potential (positive potential), and a drain connected to the line of the output signal out. The transistor 4301a has a gate connected to the ground, a source connected to the power supply potential, and a drain connected to the line of the output signal outx. The n-channel transistor 4302b has a gate connected to the input signal inx line, a drain connected to the output signal out line, and a source connected to the drain of the n-channel transistor 4303. The n-channel transistor 4302a has a gate connected to the input signal in line, a drain connected to the output signal outx line, and a source connected to the drain of the n-channel transistor 4303. The n-channel transistor 4303 has a gate connected to the line of the clock signal clk and a source connected to the drain of the n-channel transistor 4306. The n-channel transistor 4306 has a gate connected to the voltage vbn line and a source connected to the ground.

  The n-channel transistor 4304a has a gate connected to the output signal outx line, a drain connected to the output signal out line, and a source connected to the drain of the n-channel transistor 4305. The n-channel transistor 4304b has a gate connected to the output signal out line, a drain connected to the output signal outx line, and a source connected to the drain of the n-channel transistor 4305. The n-channel transistor 4305 has a gate connected to the line of the clock signal clkx and a source connected to the drain of the transistor 4306.

  When the clock signal clk is at a high level, the input signals in and inx are output as the output signals out and outx with the same logic and stored in the circuits of the transistors 4304a and 4304b. When the clock signal clk is at a low level (clock signal clk is at a high level), the stored contents of the circuits of the transistors 4304a and 4304b are maintained and output as output signals out and outx.

  As shown in FIG. 42, a receiving circuit (demultiplexer) generally used in CMOS is realized by arranging a tree type demultiplexer using a differential latch (CML latch) after the high gain amplifier circuit. The In the tree type demultiplexer, the first stage latch operates at the same maximum frequency as the Baud rate of the waveform to be received, and the subsequent stages operate at 1/2, 1/4, 1/8... Of the maximum frequency.

  In the conventional demultiplexer, the first stage latch needs to operate at a toggle frequency of the received signal Baud rate (40 GHz for a 40 Gb / s signal). However, with current CMOS technology, it is very difficult to make a latch that operates at a repetition rate of 40 GHz. This is because the upper limit frequency of circuit operation is determined by the intrinsic speed limit of the transistor.

  As a method for solving this, the frequency of repetition operation (repetition frequency or toggle frequency) of each latch is generally limited to the frequency within the range of movement of the circuit, and the missing amount is generally compensated by using a multiphase clock. For example, a two-phase clock (that is, a differential clock) is used to operate the latch with each clock. If the toggle frequency is f and the number of phases is n, data can be determined with an effective frequency of nf.

  However, in order to correctly perform data determination using a multiphase clock, a technique for generating a multiphase clock while accurately maintaining the time relationship between phases is necessary. Furthermore, it is necessary to perform clock distribution while maintaining this time relationship. That is, a technique for handling a clock with an accurate phase difference is required instead of the frequency being 1 / n.

  This is as difficult a technique as dealing with high frequencies. This is because the error included in the time difference between the phases is given by the delay error of element circuits such as a delay circuit used for generating a multi-phase clock and an amplifier circuit used for clock distribution, and these delays are also used transistors. This is because the amount is proportional to the delay.

  In addition to the technical difficulties of generating multi-phase clocks, there are other problems with receiver circuits that use multi-phase clocks. That is n times the number of latches and comparators connected to the input. When the number of latches and the like is increased by n times, the input capacitance is increased by n times and the signal band is limited. The total capacity of the clock wiring also becomes n times, and the power consumption of the clock distribution system increases.

(Second background technology)
A major technical issue in transmitting and receiving a high-speed signal is the design of a high-speed comparator for signal reception. In such a high frequency region, the signal amplitude transmitted through the signal line has a small value. In order to amplify the small signal to a logic amplitude that can be processed by a logic circuit, a comparator circuit having high sensitivity and operating at high speed is required.

  Currently, speeds of several Gb / s to 10 Gb / s are realized using CMOS circuit technology. In a higher speed region, a compound semiconductor or SiGe mixed crystal semiconductor element is generally used. However, it is desired to realize a CMOS circuit because of cost and possibility of integration with a large-scale integrated circuit.

  FIG. 44 shows a circuit called StrongARM latch (and its derivative circuit) as a comparator circuit used in a general CMOS. This comparator circuit inputs differential input signals in and inx in synchronization with the clock signal clk, and outputs differential output signals out and outx.

  In the p-channel transistor 4401b, the gate is connected to the clock signal clk line, the source is connected to the power supply potential, and the drain is connected to the signal im line. The p-channel transistor 4402b has a gate connected to the signal imx line, a source connected to the power supply potential, and a drain connected to the signal im line. In the p-channel transistor 4401a, the gate is connected to the clock signal clk line, the source is connected to the power supply potential, and the drain is connected to the signal imx line. In the p-channel transistor 4402a, the gate is connected to the signal im line, the source is connected to the power supply potential, and the drain is connected to the signal imx line.

  The n-channel transistor 4403b has a gate connected to the signal imx line, a drain connected to the signal im line, and a source connected to the drain of the n-channel transistor 4404b. The n-channel transistor 4403a has a gate connected to the signal im line, a drain connected to the signal imx line, and a source connected to the drain of the n-channel transistor 4404a. In the n-channel transistor 4404b, the gate is connected to the line of the input signal inx, and the source is connected to the drain of the n-channel transistor 4405. In the n-channel transistor 4404a, the gate is connected to the line of the input signal in, and the source is connected to the drain of the n-channel transistor 4405. The transistor 4405 has a gate connected to the line of the clock signal clk and a source connected to the ground.

  A NAND circuit 4406 calculates a NAND of the signal imx and the output signal outx and outputs an output signal out. The NAND circuit 4407 calculates NAND of the signal im and the output signal out, and outputs an output signal outx.

  In this circuit, when the clock signal clk rises, the signal is amplified by a regeneration action by positive feedback. The input circuit is reset (precharged) by the precharge elements of the p-channel transistors 4401a and 4401b while the clock signal clk is at a low level. In order to hold the output signals out and outx during the precharge period, an R-S flip-flop in which CMOS NAND gates 4406 and 4407 are cross-coupled (cross-coupled) is used. When the clock signal clk is at a low level, the signals im and imx are at a high level, and the RS flip-flop maintains and outputs the previous state.

  The StrongARM latch can be used as a comparator using a clock, and as a CMOS circuit, it has a feature that a CMOS signal of a full amplitude can be obtained at a single stage at a high speed. However, it was very difficult to increase the frequency at which the operation was repeated to 5 GHz or more.

  The reason is that StrongARM performs a regeneration operation with a push-pull type circuit using an n-channel transistor and a p-channel transistor, so that it is 100 ps or more from the reset state until both the n-channel transistor and the p-channel transistor are activated actively Because it will take a long time. For this reason, regeneration is not performed sufficiently with a clock of 5 GHz or more, and signal amplification cannot be performed. In addition, there is a problem that the internal state cannot be completely reset even during the reset period, and the output is fixed to a constant value determined by the past history regardless of the input signal.

  In addition to the problem that the repetition frequency (toggle frequency) cannot be increased, there is another important problem. That is, since the speed of regeneration is slow, intersymbol interference occurs internally when high-speed input data is received. In an amplifier circuit having a positive feedback, a phenomenon (reproduction) in which the signal increases exponentially occurs. Now, assuming that the time when the circuit is activated by the clock is t = 0, the signal increase by reproduction is given by the following equation.

    V (t) = V (0) exp [t / τ]

  Here, τ is a time constant of the reproducing circuit. This time constant is determined by the cutoff frequency of the p-channel transistor and the n-channel transistor, and is a value around 30 ps. For this reason, for example, when trying to receive a high-speed signal of 40 Gb / s, there arises a problem that malfunction occurs due to the influence of the bit subsequent to the bit at the timing when the clock enters. This is because the effective sampling aperture width for the input is determined by the reproduction time constant.

  Patent Document 1 below describes a demultiplexer, and Patent Document 2 describes a pulse synchronization circuit.

JP 59-52914 A JP 58-36088 A

  An object of the present invention is to provide a signal processing circuit (demultiplexer) that can receive a high-speed signal and perform accurate sampling.

According to one aspect of the present invention, a first delay line having a plurality of taps for delaying an input signal, a second delay line having a plurality of taps for delaying a clock signal, and each data input line Are connected to the tap of the first delay line, each clock input line is connected to the tap of the second delay line, and a plurality of clock control comparators configured by a connection circuit of the master latch and the slave latch, and a plurality of clocks A signal processing circuit is provided that is connected to a subsequent stage of the control comparator and has a selector for selecting the next series of the series having the largest data transition among the series of output signals of the plurality of clock control comparators . The difference between the input signal delay time by the first delay line and the clock signal delay time by the second delay line has a different value for each clock control comparator.

  By using the first and second delay lines, it is possible to obtain an accurate sampling interval required for high-speed signal reception, and to reduce the input band and drive the clock by driving a large number of clock control comparators. Since an increase in power can be prevented, a low-power circuit with a high speed and a large timing margin can be configured.

(Principle of the first to eleventh embodiments)
FIG. 1A shows a principle configuration example of a demultiplexer (signal processing circuit) according to first to eleventh embodiments of the present invention, and FIG. 2 shows a timing diagram for explaining the operation thereof.

  The high-speed input signal Data is delayed by propagating through the delay line 101 having a plurality of taps. The input signal Data is input from one end of the data delay line 101 and the other end is terminated by the characteristic impedance 102 of the delay line 101. As shown in FIG. 1B, the delay line 101 includes an inductor L and capacitors C and Cin, and each tap is represented by an inductor L and capacitors Cin and C. The characteristic impedance Z of this delay line is Z = √ (L / (C + Cin)).

  The clock signal Clock is delayed by propagating through the clock delay line 101 having a plurality of taps. The clock signal Clock is input from one end of the delay line 101 and the other end is terminated by the characteristic impedance 102 of the delay line 101. As shown in FIG. 1B, the delay line 101 includes an inductor L and capacitors C and Cin, and each tap is represented by an inductor L and capacitors Cin and C. The characteristic impedance Z of this delay line is Z = √ (L / (C + Cin)).

  In the plurality of latches 103, each data input line is connected to a tap of the delay line 101 of the input signal Data, and each clock input line is connected to a tap of the delay line 101 of the clock signal Clock. The direction in which the input signal Data propagates through the delay line 101 is different from the direction in which the clock signal Clock propagates through the delay line 101 with respect to the plurality of latches 103. As a result, for each latch 103, the difference between the input signal delay time due to the delay line of the input signal Data and the clock signal delay time due to the delay line of the clock signal Clock has a different value.

  The input differential signal Data has a time (1 UI) corresponding to, for example, 1 bit of 25 ps. The signals D0 to D5 are each tap signal obtained by delaying the input signal Data by time td ((2/15) UI). The clock signals C0 to C5 are each tap signal obtained by delaying the clock signal Clock by time tc ((1/5) UI).

  The first latch 103 latches the input signal D5 and outputs the output signal out0 in synchronization with the clock signal C0. The second latch 103 latches the input signal D4 and outputs the output signal out1 in synchronization with the clock signal C1. The third latch 103 latches the input signal D3 and outputs an output signal out2 in synchronization with the clock signal C2. The fourth latch 103 latches the input signal D2 and outputs the output signal out3 in synchronization with the clock signal C3. The fifth latch 103 latches the input signal D1 and outputs the output signal out4 in synchronization with the clock signal C4. The sixth latch 103 latches the input signal D0 and outputs the output signal out5 in synchronization with the clock signal C5.

  The 1-bit input signal Data is converted into 6-bit parallel signals out0 to out5. Three-times oversampling is realized by sampling three times within one UI of the input signal Data.

  The latch 103 is, for example, a clock control comparator (hereinafter referred to as a clock comparator) configured by a connection circuit of the master latch 4214 and the slave latch 4215 in FIG. In the present embodiment, a multi-tap delay line is used to effectively generate a multi-phase clock signal. Further, driving the clock comparator 103 through a multi-tap delay line can suppress a decrease in bandwidth and an increase in power consumption due to an increase in input capacitance.

  As shown in FIG. 1B, when one end of a multi-tap delay line is terminated and a signal or clock is input, these signals propagate through the delay line. Here, it is assumed that the delay line is a transmission line in which an equivalent circuit in a minute section is represented by an inductor L and a capacitor C. When the tap interval is sufficiently short, the input capacitance Cin of the circuit connected to each tap (input capacitance of the clock comparator) can be considered as the effective capacitance Ceff by incorporating it into the capacitance C 1. A signal (or clock) input from one end of the line propagates through this delay line and is absorbed by the matching impedance at the end. The line viewed from the signal input end is equal to the terminating resistance (matching impedance) regardless of the length. In other words, the delay line is a mechanism for generating an accurate time difference, and at the same time, there is a feature that even if a large number of elements are driven, the bandwidth is not reduced and the power consumption is not increased.

  Consider a case where the data input terminals and clock inputs of a large number of clock comparators 103 are driven by a multi-tap delay line as shown in FIG. In this case, the effective sampling interval is determined by how the difference between the delay of the data delay line and the delay of the clock delay line changes for each comparator. In this case, since the data and clock run directions are opposite, the sum td + tc of the tap delay interval td of the data delay line and the delay interval tc of the clock delay line is the effective sampling interval.

  Since the delay time of the input signal supplied to each clock comparator 103 is different from the delay time of the clock signal, sampling is possible. Oversampling in which sampling is performed three times or more in one UI is preferable.

  According to the present embodiment, it is possible to generate multi-phase clocks with accurate sampling intervals, and to drive a large number of clock comparators 103 with these clocks, and to reduce the input bandwidth due to an increase in input capacitance by the plurality of clock comparators 103. Since reduction can be prevented, a high-speed signal receiving circuit (demultiplexer) is realized.

(First embodiment)
FIG. 3 shows a configuration example of the demultiplexer according to the first embodiment of the present invention. Differences of this embodiment from FIG. 1A will be described. In the present embodiment, the 1-bit serial signal Data can be converted into 8-bit parallel signals out0 to out7. The clock signal Clock is delayed by a DLL (Delay Locked Loop). The clock signal Clock is terminated by the resistor 102 via a plurality of buffers 301. A tap between each buffer 301 is connected to a clock terminal of each clock comparator 103. The phase detector 302 detects the phase difference between the input clock signal Clock and the output clock signal of the final stage buffer 301. The charge pump 303 outputs a control voltage Vc corresponding to the phase difference to each buffer 301. The delay time of each buffer 301 is adjusted according to the control voltage Vc. The delay time of the clock signal Clock can be adjusted by this DLL.

  Each of the data delay line and the clock delay line has eight taps. The eight taps of the data delay line are connected to the data input terminal of the clock comparator, and the eight taps of the clock delay line are connected to the clock input terminal of the clock comparator. In this embodiment, the input signal Data is 10 Gb / s.

  In this embodiment, the data delay line is configured by a delay line using an LC delay unit. On the other hand, the clock delay line is an active delay line using DLL. The clock frequency is 2.5 GHz, and the clock delay line has a total delay of 2 UI corresponding to 10 Gb / s, that is, 200 ps. The delay per stage of the clock delay line is 25 ps, and the whole is composed of 8 delay stages. The delay of the LC delay unit is 25 ps per tap.

  According to this embodiment, double oversampling that performs sampling at the center and boundary of a 10 Gb / s data bit cell is realized using a 2.5 GHz clock. In the present embodiment, eight clock comparators are driven from the data line. However, since the clock comparators are driven through the line, high-speed operation is possible without a decrease in bandwidth due to an increase in input capacitance.

(Second Embodiment)
FIG. 4 shows a configuration example of a demultiplexer according to the second embodiment of the present invention. This embodiment is different from FIG. 1A in that a 1-bit serial signal Data can be converted into 8-bit parallel signals out0 to out7.

  The difference between this embodiment and the first embodiment is that the clock delay line is also composed of an LC discrete line. In this embodiment, the data is 40 Gb / s and the clock frequency is 10 GHz. The clock is injected from one end of the multi-tap delay line, and terminated at the other end. As in the first embodiment, the number of taps is 8 for each data and clock delay line. In this embodiment, although the clock driver (VCO) needs to drive the characteristic impedance of the line, it is easy to make the delay between taps very small, so that a high-speed signal of 40 Gb / s can be received. .

(Third embodiment)
FIG. 5 shows a configuration example of a demultiplexer according to the third embodiment of the present invention. In this embodiment, the delay lines of the clock signals C0 to C7 are connected in a ring shape. The four negative resistance elements 501 are connected between the clock signals C0 and C4, between the clock signals C1 and C5, between the clock signals C2 and C6, and between the clock signals C3 and C7, respectively.

  FIG. 6A shows a configuration example of the negative resistance element 501. The negative resistance element 501 can generate clock signals 601a and 601b having opposite phases to each other. The p-channel transistor 602a has a gate connected to the clock signal 601b line, a source connected to the power supply potential, and a drain connected to the clock signal 601a line. The p-channel transistor 602b has a gate connected to the line of the clock signal 601a, a source connected to the power supply potential, and a drain connected to the line of the clock signal 601b. The n-channel transistor 603a has a gate connected to the clock signal 601b line, a drain connected to the clock signal 601a line, and a source connected to the drain of the n-channel transistor 604a. The n-channel transistor 603b has a gate connected to the clock signal 601a line, a drain connected to the clock signal 601b line, and a source connected to the drain of the n-channel transistor 604b. The n-channel transistors 604a and 604b have their gates connected to the voltage Vbn line and their sources connected to the ground.

  FIG. 6B illustrates a configuration example of the phase shift circuit. The phase shift circuit is connected to the lines of the clock signals C0 to C7 in FIG. 5, and determines the phase rotation direction (clock signal propagation direction). The n-channel transistor 611 has a gate connected to the clock signal C0 line, a drain connected to the clock signal C1 line, and a source connected to the ground. The n-channel transistor 612 has a gate connected to the clock signal C1 line, a drain connected to the clock signal C2 line, and a source connected to the ground. The n-channel transistor 613 has a gate connected to the clock signal C2 line, a drain connected to the clock signal C3 line, and a source connected to the ground. The n-channel transistor 614 has a gate connected to the clock signal C3 line, a drain connected to the clock signal C4 line, and a source connected to the ground. The n-channel transistor 615 has a gate connected to the clock signal C4 line, a drain connected to the clock signal C5 line, and a source connected to the ground. The n-channel transistor 616 has a gate connected to the clock signal C5 line, a drain connected to the clock signal C6 line, and a source connected to the ground. The n-channel transistor 617 has a gate connected to the clock signal C6 line, a drain connected to the clock signal C7 line, and a source connected to the ground. The n-channel transistor 618 has a gate connected to the clock signal C7 line, a drain connected to the clock signal C0 line, and a source connected to the ground. The delay is in order from the clock signal C0 to C7.

  FIG. 7 shows another configuration example of the phase shift circuit. The n-channel transistor 701a has a gate connected to the clock signal C7 line, a drain connected to the clock signal C5 line, and a source connected to the drain of the n-channel transistor 705. The n-channel transistor 701b has a gate connected to the clock signal C3 line, a drain connected to the clock signal C1 line, and a source connected to the drain of the n-channel transistor 705. The n-channel transistor 702a has a gate connected to the clock signal C6 line, a drain connected to the clock signal C4 line, and a source connected to the drain of the n-channel transistor 706. The n-channel transistor 702b has a gate connected to the clock signal C2 line, a drain connected to the clock signal C0 line, and a source connected to the drain of the n-channel transistor 706. The n-channel transistor 703a has a gate connected to the clock signal C5 line, a drain connected to the clock signal C3 line, and a source connected to the drain of the n-channel transistor 707. The n-channel transistor 703b has a gate connected to the clock signal C1 line, a drain connected to the clock signal C7 line, and a source connected to the drain of the n-channel transistor 707. The n-channel transistor 704a has a gate connected to the clock signal C4 line, a drain connected to the clock signal C2 line, and a source connected to the drain of the n-channel transistor 708. The n-channel transistor 704b has a gate connected to the clock signal C0 line, a drain connected to the clock signal C6 line, and a source connected to the drain of the n-channel transistor 708. The transistors 705 to 708 have drains connected to a predetermined voltage and sources connected to the ground.

  In the present embodiment, as in the second embodiment, the data and clock delay lines are both LC discrete delay lines. The difference from the second embodiment is that the clock is not injected from the end of the delay line and terminated last. In this embodiment, the delay lines are connected in a ring shape, and the clock propagates in one direction in the ring. A negative resistance element 501 using positive feedback is inserted for each delay stage in order to compensate for clock attenuation by the delay line. In order to ensure that the clock propagates in one direction, a small-size n-channel transistor differential pair element (FIG. 7) is added. The present embodiment has an advantage that the power consumption of the clock buffer 301 can be significantly reduced because the power of the clock buffer 301 (FIG. 3) is not consumed by the termination resistor 102.

(Fourth embodiment)
FIG. 8 shows a configuration example of a demultiplexer according to the fourth embodiment of the present invention, and FIG. 9 shows a timing diagram for explaining its operation. In the present embodiment, the delay times of the delay lines of the input signal Data and the clock signal Clock are not uniform. Delay time between input signals D1 and D2 is 0.1 UI, delay time between input signals D2 and D3 is 0.1 UI, delay time between input signals D3 and D4 is 0.15 UI, delay between input signals D4 and D5 Time is 0.15 UI. Delay time between clock signals C2 and C3 is 0.15 UI, Delay time between clock signals C3 and C4 is 0.15 UI, Delay time between clock signals C4 and C5 is 0.1 UI, Delay between clock signals C5 and C6 Time is 0.1 UI. 1 UI is 25 ps.

  In this embodiment, the data is 40 Gb / s and the clock is 10 GHz. The number of comparators per UI is four. Three of them are used to sample data at the center of the data eye, and one is used to sample the boundary of the eye.

  In this embodiment, since there are three comparators for sampling data, even if the clock jitter is large and the timing of data sampling is greatly shifted, correct data can be obtained by taking the majority of the outputs of the three comparators. There is an advantage that it can be received.

(Fifth embodiment)
FIG. 10 shows a configuration example of a demultiplexer according to the fifth embodiment of the present invention. In this embodiment, the tap delay of the data delay line is selected as (1/6) UI of 40 Gb / s, and the delay between taps of the clock delay line is also selected as (1/6) UI. There are twelve taps, and the number of comparators 103 is twelve.

  In the present embodiment, three samplings per UI, that is, three times oversampling (see FIG. 2) are performed. Correct data can be obtained by processing the determination result obtained by sampling with a logic circuit. As the number of samplings in one UI is increased, there is an advantage that correct data can be easily obtained. On the other hand, there is a disadvantage that the circuit becomes complicated. Triple oversampling is a balance between the two.

(Sixth embodiment)
FIG. 11 shows a configuration example of a demultiplexer according to the sixth embodiment of the present invention, and FIG. 12 shows a timing diagram for explaining its operation. In the present embodiment, the direction in which the input signal Data propagates through the data delay line and the direction in which the clock signal Clock propagates through the clock delay line are the same for the plurality of clock comparators 103. The delay time between each tap of the data delay line is (1/3) UI, and the delay time between each tap of the clock delay line is (2/3) UI.

  In the present embodiment, as in the third embodiment, the clock signal Clock propagates in one direction through the clock delay line connected in a ring shape, and data propagates in one direction from one end of the data delay line to the other end. This embodiment is different from the third embodiment in that the direction in which the clock propagates and the direction in which the data propagates are the same. The data delay line produces a delay of 8 UI of 40 GHz as a whole, the delay between taps is (2/3) UI, and the total number of taps is 12. On the other hand, the clock causes a delay of 4 UI in the entire ring, the delay between taps is (1/3) UI, and the total number of taps is 12.

  In this embodiment, since the effective sampling interval is determined by the time difference between the inter-tap delay time of the input signal Data and the inter-tap delay time of the clock signal Clock, higher timing accuracy can be obtained with the same delay line processing accuracy. There are advantages. On the other hand, when the clock and data are propagated in the opposite directions, there is another advantage that the delay amount of the data and the clock delay line can be reduced.

(Seventh embodiment)
FIG. 13 shows a configuration example of a demultiplexer according to the seventh embodiment of the present invention. In the present embodiment, the direction in which the clock propagates and the direction in which the data propagates are the same as in the sixth embodiment. The inter-tap delay time of the input signal Data is (2/3) UI, and the inter-tap delay time of the clock signal Clock is (1/3) UI. Since the propagation directions of data and clock are the same, the comparator performs the same operation as the distributed constant amplifier circuit and can obtain a high band.

  The clock comparator 103 has a configuration in which a plurality of clock comparators 103 share an output. By connecting the outputs of a plurality of (for example, three) clock comparators 103, an output corresponding to the average value of the three sample values can be obtained. By such connection, an equivalently large input transistor is used for the clock comparator 103, and there is an advantage that the offset voltage due to element variation is small and the sensitivity can be increased. Further, there is an advantage that the bandwidth is not reduced by the input capacitance even though the input element is equivalently large in size. Usually, when the input transistor is large, the input capacitance increases, and the high frequency characteristics deteriorate. In the present embodiment, since the input capacitance of the clock comparator 103 is driven through the LC delay line, there is no characteristic deterioration.

(Eighth embodiment)
FIG. 14 shows a configuration example of a demultiplexer according to the eighth embodiment of the present invention, and FIG. 15 shows a timing diagram for explaining its operation. This embodiment is obtained by modifying the second embodiment, and the difference is that the clock signal Clock is not a single phase but a four phase. For this reason, four clock comparators are connected to one tap of the data delay line.

  The four-phase clock signal C0 includes clock signals CKA2, CKB2, CKC2, and CKD2. The four-phase clock signal C1 is a signal obtained by delaying the clock signal C0 by (1/6) UI, and includes clock signals CKA1, CKB1, CKC1, and CKD1. The four-phase clock signal C2 is a signal obtained by delaying the clock signal C1 by (1/6) UI, and includes clock signals CKA0, CKB0, CKC0, and CKD0. 1 UI is 25 ps.

  The four clock comparators 1402 latch the same input signal D2 in synchronization with the clock signals CKA2, CKB2, CKC2, and CKD2, respectively, and output the output signals DTA2, DTB2, DTC2, and DTD2.

  The four clock comparators 1401 latch the same input signal D1 in synchronization with the clock signals CKA1, CKB1, CKC1, and CKD1, respectively, and output the output signals DTA1, DTB1, DTC1, and DTD1.

  The four clock comparators 1400 latch the same input signal D0 in synchronization with the clock signals CKA0, CKB0, CKC0, and CKD0, and output the output signals DTA0, DTB0, DTC0, and DTD0.

  Since the total delay amount of the delay line can be reduced (1/4) in this embodiment, there is an advantage that signal distortion due to delay line attenuation can be reduced. The clock signal is preferably three or more phases.

(Ninth embodiment)
FIG. 16 shows a configuration example of a demultiplexer according to the ninth embodiment of the present invention. This embodiment uses clock delay lines connected in a ring shape as in the third embodiment. The difference from the third embodiment is that the total number of taps of the data delay line is ½ of the total number of taps of the clock delay line, and two comparators are connected to each tap of the data delay line. . FIG. 16 is different in that the clock delay line is connected in a ring shape, and FIG. 17 is the same in the other points in that the clock delay line is terminated.

  In FIG. 16, clock delay lines are connected in a ring shape, and the clock signal Clock is sequentially delayed by 0 °, 90 °, 180 °, and 270 °. The clock comparator 103 includes a clock comparator 103a that latches at the rising edge of the clock signal and a clock comparator 103b that latches at the falling edge of the clock signal. The clock comparator 103a uses the 0 ° clock signal to latch at the rising edge of the clock signal. The clock comparator 103b uses the 180 ° clock signal to latch at the falling edge of the clock signal. A dummy circuit 1603 equivalent to the clock comparator 103 is connected to the 90 ° and 270 ° clock delay lines.

  FIG. 18 is a timing diagram for explaining the operation of the circuit of FIG. In FIG. 17, each of the six clock comparators 103a latches the input signals D5 to D0 and outputs the output signals out0 to out5 in synchronization with the rising edges of the clock signals C0 to C5. The six clock comparators 103b latch the input signals D5 to D0 and output the output signals out6 to out11 in synchronization with the falling edges of the clock signals C0 to C5, respectively. When the delay time between taps of the data delay line and the clock delay line is (1/6) UI, and 1 UI is 25 ps, three times oversampling can be realized.

  As in the eighth embodiment, the present embodiment has an advantage that the total delay amount of the data delay line is small (in this case, 1/2), so that the signal distortion of the data delay line is small. As shown in FIG. 17, it is possible to configure a circuit similar to FIG. 16 through a delay line that terminates the clock.

(Tenth embodiment)
FIG. 19 is a configuration example of the demultiplexer according to the tenth embodiment of the present invention, and shows a circuit connected to the subsequent stage of the circuits of the first to ninth embodiments. In this embodiment, a logic circuit for processing the outputs of the plurality of clock comparators 103 is provided. This logic circuit processes 16 × 3 = 48 pieces of data obtained by oversampling 16 UI three times. If the 48 data din are numbered from 1 to 48, a series of 1, 4, 7,... (Series 1), a series of 2, 5, 8,... (Series 2), 3, 6, There are 9,... Series (series 3). Which series is selected as the correct data from series 1 to series 3 has the largest number of data (number of data in which data transition is detected) that has become different from the previous sampling value in these series. Do something based. For example, if the series 1 has the most data transition, the series 2 is selected as the correct data. If the series 2 has the largest data transition, the series 3 is selected. If the series 3 has the maximum number of data transitions, the series 1 is selected as the correct data.

  The sorter 1901 sorts the data din and outputs data s. 54 pieces of data c are generated by the flip-flop 1902. The selector 1904 is controlled by the controller 1903 and selects correct 16 data from 54 data. The flip-flop 1905 outputs 16 pieces of data dout in synchronization with the clock signal clkin.

  FIG. 29 shows an example of a circuit for generating a recovered clock having a correct frequency. The comparator 2901 corresponds to, for example, the demultiplexers according to the first to ninth embodiments, oversamples the 40 Gb / s input signal Data three times, and outputs a 10 Gb / s 3 × 4 bit parallel signal. The selector 2902 converts a 3 × 4 bit signal of 10 Gb / s into a 3 × 16 bit signal of 2.5 Gb / s, selects one of the three sequences, and correct 16 of 2.5 Gb / s. A bit output signal Output is output, and a signal E / L (early / late) indicating a phase difference of the clock signal with respect to the input signal Data is output to the phase interpolator (PI) 2904. A PLL (phase locked loop) 2903 generates a 4-phase clock signal of 10 GHz based on the reference clock signal. The phase interpolator 2903 receives a 4-phase clock signal, adjusts and outputs a recovered clock having a correct frequency according to the signal E / L. The recovered clock is output to the outside together with the output signal Output.

  That is, the selector 2902 compares which series has been selected with the past, and increases when the number of selected series increases (internal clock delay tends to increase), and decreases when the number of series decreases (internal clock). Signal E / L) is generated. This signal E / L is used to adjust the phase control signal of the phase interpolator 2904 for generating the recovered clock and generate the recovered clock of the correct frequency.

  In the present embodiment, the correct data sequence is extracted from the data obtained by oversampling, and at the same time, the frequency of the recovered clock generation circuit (FIG. 29) can be adjusted, so that the data output from the receiving circuit (demultiplexer) can be adjusted. There is an advantage that the bit width is always kept constant. In a general oversampling receiving circuit, there is no restored clock, and the bit width of data output from the receiving circuit may increase or decrease by 1 bit according to the frequency difference between the clock frequency generating data and the internal clock. This is very difficult to use depending on the purpose.

  FIG. 20 shows a circuit more specifically showing the circuit of FIG. The front end 2001 is, for example, the demultiplexer of the ninth embodiment, converts a 40 Gb / s serial signal into a 24-bit parallel signal, and adjusts the delay time of the clock signal by the VCO 2003.

  The CDR2002 will be described. The demultiplexer 2011 converts a 24-bit signal into a 48-bit signal. The 48-bit signal is added with bits by the flip-flop 2012 to become a 54-bit signal. The 54-bit signal is adjusted in latency by a plurality of flip-flops and input to the selector 2014. The 54-bit signal is supplied to the selector controller 2018 and the charge pump controller 2019 via the Tally & Vote circuit 2015, the up / down generator 2016, and the up / down counter 2017. The selector 2014 selects and outputs one series of 2.5 Gb / s 16-bit signals from three series of 54-bit signals under the control of the selector controller 2018. The charge pump 2020 outputs a control voltage Vcntl to the VCO 2003 under the control of the charge pump controller 2019. The VCO 2003 adjusts the delay time of the clock signal to an appropriate value based on the control voltage Vcntl.

  FIG. 21 shows a more specific circuit of the CDR 2002 of FIG. The 54-bit signal C [0:53] is divided into signals C [2:26] and C [27:51]. The signal C [2:26] is supplied to the selector controller 2018a and the charge pump 2019 via the edge generator 2101a, the Tally & Vote circuit 2015a, the up / down generator 2016a, and the up / down counter 2017. The signal C [27:51] is supplied to the selector controller 2018b via the edge generator 2101b, the Tally & Vote circuit 2015b, the up / down generator 2016b, and the up / down counter 2017. The selector 2014a converts a 27-bit signal into an 8-bit signal under the control of the selector controller 2018a. The selector 2014b converts a 27-bit signal into an 8-bit signal under the control of the selector controller 2018b. The outputs of the selectors 2014a and 2014b are 2.5 Gb / s 16-bit signals.

  FIG. 22 shows a configuration example of the edge generators 2101a and 2101b in FIG. A plurality of exclusive OR (ExOR) circuits 2201 calculate an exclusive OR based on the 24-bit input signals in [0] to in [24] and generate three sets of 8-bit signals edge0, edge1, and edge2. Output.

  FIG. 23 shows a configuration example of the Tally & Vote circuits 2015a and 2015b in FIG. First, the Tally comparator circuit 2301 will be described. The Tally comparators 2311 to 2313 receive two input signals A and B and output an output signal D. In this case, if A + 0.5> B, D = 1. The Tally comparator 2311 receives the 8-bit signals edge0 and edge1 and outputs a signal X. The Tally comparator 2312 receives the 8-bit signals edge1 and edge2 and outputs a signal Y. The Tally comparator 2313 receives the 8-bit signals edge2 and edge0 and outputs a signal Z.

  The voting logic circuit 2302 receives the signals X, Y, and Z, and outputs signals R, S, and T according to the following logic.

XYZRST
0 0 0 (previous value)
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 0 0 1
1 1 0 1 0 0
1 1 1 (previous value)

  FIG. 24 shows a configuration example of the Tally comparators 2311 to 2313 in FIG. Three input signals A, B and C are input. The circuit 2401 is a circuit for calculating AB. The circuit 2402 is a circuit for calculating C / 2.

  FIG. 25 shows a configuration example of the up / down generators 2016a and 2016b of FIG. A NAND circuit 2501 receives signals R [n] and T [n−1] and outputs the NAND. The NAND circuit 2502 receives the signals S [n] and R [n−1] and outputs the NAND. The NAND circuit 2503 receives the signals T [n] and S [n−1] and outputs the NAND. The NAND circuit 2504 receives the output signals of the NAND circuits 2501 to 2503 and outputs the NAND as a signal UP.

  The NAND circuit 2511 receives the signals S [n] and T [n−1] and outputs the NAND. The NAND circuit 2512 receives the signals R [n] and S [n−1] and outputs the NAND. The NAND circuit 2513 receives the signals T [n] and R [n−1] and outputs the NAND. The NAND circuit 2514 receives the output signals of the NAND circuits 2511 to 2513 and outputs the NAND as a signal DOWN.

  FIG. 26 shows a configuration example of the up / down counter 2017 of FIG. The selector (shifter) 2601 is “1” when the signal (U0, D0) is (0, 1), the output signal of the flip-flop 2612 when it is (0, 0), and “0” when it is (1, 0). Output. The flip-flop 2602 receives the output signal of the selector 2601 in synchronization with the 2.5 GHz clock signal and outputs an upper 8-bit signal.

  The selector (shifter) 2611 outputs “1” when the signal (U1, D1) is (0, 1), the output signal of the selector 2601 when (0, 0), and “0” when it is (1, 0). To do. The flip-flop 2612 receives the output signal of the selector 2611 in synchronization with the 2.5 GHz clock signal, and outputs a lower 8-bit signal.

  FIG. 27A shows a configuration example of the selector controllers 2018a and 2018b in FIG. The logical operation is performed on the data in the registers q0 to q7 of the up / down counter (FIG. 26), and the control signals n0, n1, n2, m0, m1, and m2 are output.

  FIG. 27B shows a configuration example of the selectors 2014a and 2014b in FIG. The plurality of three-series switches select and output one of the three signals according to the control signals n0, n1, n2, m0, m1, and m2.

  FIG. 28 shows a configuration example of the charge pump 2019 of FIG. Of the upper 8-bit registers q0 to q7 of the up / down counter (FIG. 26), the data of registers q0 to q3 is supplied to the p-channel transistor of the charge pump, and the data of registers q4 to q7 is supplied to the n-channel transistor of the charge pump. Supplied.

(Eleventh embodiment)
FIG. 30 shows a configuration example of a demultiplexer according to the eleventh embodiment of the present invention. In the present embodiment, the output frequency of the internal clock generation circuit is controlled according to the up / down signal E / L generated in the tenth embodiment.

  Similar to the tenth embodiment, the comparator 2901 corresponds to, for example, the demultiplexer according to the first to ninth embodiments. The comparator 2901 oversamples the 40 Gb / s input signal Data three times, and 3 × 4 of 10 Gb / s. A bit parallel signal is output. The selector 2902 converts a 3 × 4 bit signal of 10 Gb / s into a 3 × 16 bit signal of 2.5 Gb / s, selects one of the three sequences, and correct 16 of 2.5 Gb / s. A bit output signal Output is output, and a signal E / L (early / late) indicating a phase difference of the clock signal with respect to the input signal Data is output to the charge pump 3001. The VCO 3002 generates a 10 GHz four-phase recovery clock signal in accordance with the control voltage output from the charge pump 3001.

  In the present embodiment, the output frequency of the internal clock generation circuit is controlled according to the up / down signal E / L. In this embodiment, the internal clock is synchronized with the clock generating data. Oversampling has the advantage that correct signal reception is possible even when there is a jitter component of high frequency, and at the same time has the advantage that a recovered clock with small jitter can be obtained in the same way as a normal clock recovery circuit.

  As described above, in the first to eleventh embodiments, it is possible to obtain an accurate sampling interval necessary for high-speed data reception, and to reduce the input band and drive the clock by driving many comparators. Since an increase in power can be prevented, a low-power receiving circuit with a high speed and a large timing margin can be configured.

(Principle of the twelfth to twentieth embodiments)
FIGS. 31A and 31B show principle configuration examples of comparator circuits (signal processing circuits) according to the twelfth to twentieth embodiments of the present invention.

  In FIG. 31A, an input circuit 3101 processes the input signal in and outputs an output signal so that the signal transfer characteristic from the input signal in to the output signal is changed by the clock signal clk. Specifically, the input circuit 3101 is activated when the clock signal clk is at a low level, performs signal transmission from the input signal in to the output signal, and is deactivated when the clock signal clk is at a high level. The signal transmission from the input signal in to the output signal is not performed. In the inactive state, the output signal is reset or held, preferably reset. The clock comparator (amplifier circuit) 3102 amplifies the output signal of the input circuit 3101 and outputs the output signal out during a period of being activated by the high level of the clock signal clk.

  When the clock signal clk becomes high level, the input circuit 3101 becomes inactive, resets the output signal, and outputs it. As a result, the state of the previous input signal in can be reset, the influence of the previous state can be eliminated when the next input signal in is processed, and the input signal in can be processed at high speed. However, when the input circuit 3101 is reset, the output signal is gradually reset with some delay. When the clock signal becomes high level, the input circuit 3101 is reset and the clock comparator 3102 is activated. The clock comparator 3102 amplifies the output signal before the input circuit 3101 is completely reset, and outputs an appropriate output signal out.

  FIG. 31B is different from FIG. 31A in that the input circuit 3111 is activated when the clock signal clk is at a high level. The input circuit 3111 is activated when the clock signal clk is at a high level and transmits a signal from the input signal in to the output signal, and is deactivated when the clock signal clk is at a low level. No signal transmission from to the output signal. In the inactive state, the output signal is reset. The clock comparator (amplifier circuit) 3102 amplifies the output signal of the input circuit 3101 and outputs the output signal out during a period of being activated by the high level of the clock signal clk.

  When the clock signal clk becomes low level, the input circuit 3111 becomes inactive, resets the output signal, and outputs it. As a result, the state of the previous input signal in can be reset, the influence of the previous state can be eliminated when the next input signal in is processed, and the input signal in can be processed at high speed. Thereafter, when the clock signal becomes a high level, the input circuit 3101 and the clock comparator 3102 are activated. That is, the input circuit 3101 becomes conductive and outputs an output signal, and the clock comparator 3102 amplifies the output signal of the input circuit 3101 and outputs an appropriate output signal out.

  In this embodiment, input circuits 3101 and 3111 are provided in front of the stage 3102 for obtaining a large amplification degree by the reproducing action. By adopting such a two-stage configuration, the sampling aperture for the input can be set to a small value separately from the sampling aperture of the subsequent playback stage 3102. That is, the input circuits 3101 and 3111 are configured to effectively obtain a small sampling aperture, and a large gain due to reproduction is obtained in the subsequent stage 3102.

  An input circuit for realizing a small sampling aperture includes a sampling switch circuit 3101 that is turned off at the same time that the reproduction circuit 3102 is activated as shown in FIG. 31A, and a reproduction circuit 3102 as shown in FIG. There is a circuit 3111 that becomes active as soon as is activated.

  The input circuit (sampling switch) 3101 in FIG. 31A is assumed to have a sufficiently large band in the on state (conductive state). When the switch 3101 is realized by using an amplifier circuit capable of switching between a state in which the transmission from the input to the output is performed and a state in which the switch 3101 is not performed by the clock signal clk, the gain in the state in which the transmission is performed is reduced. It is necessary to make the bandwidth sufficiently large. On the contrary, when the switch 3101 is turned off (no transmission is performed), it is desired that the bandwidth of the output node is reduced. Otherwise, the signal will not be retained and will disappear immediately. In order to make the band of the output node large in the conductive state and small in the non-conductive state, there is a method of providing a circuit whose impedance changes with the clock at the output node.

  In the case of the input circuit 3111 in FIG. 31B, the subsequent circuit 3102 is controlled by a clock so as to become active at the same time as the reproduction is started. In this case, in order to reduce the influence of the bit after the received bit, the frequency characteristic is selected so that the signal of the first bit lasts as long as possible. For example, the influence of subsequent bits is reduced by using an integration circuit.

  In the activated state, the input circuits 3101 and 3111 amplify by integration characteristics or regenerative characteristics (the signal increases with time by the action of positive feedback), and the clock comparator 3102 receives the output signals of the input circuits 3101 and 3111. Amplification can be performed with a large gain by the regenerative action of the positive feedback loop.

  According to the present embodiment, a comparator capable of toggling at high speed and having a small input sampling aperture can be realized, so that a high-speed and low-power signal receiving circuit can be realized with a simpler circuit architecture.

(Twelfth embodiment)
FIG. 32 shows a configuration example of a comparator circuit according to the twelfth embodiment of the present invention. The comparator circuit inputs the differential input signals in and inx in synchronization with the differential clock signals clk and clkx, and outputs the differential output signals out and outx.

  First, the structure of the input circuit 3111 (FIG. 31B) will be described. The p-channel transistor 3201 has a gate connected to the clock signal clkx line, and a source and a drain connected to the input signal inx and signal imx lines. The n-channel transistor 3202 has a gate connected to the clock signal clk line, and a source and a drain connected to the input signal inx and signal imx lines. The p-channel transistor 3203 has a gate connected to the clock signal clkx line, and a source and a drain connected to the input signal in and the signal im line. The n-channel transistor 3204 has a gate connected to the clock signal clk line and a source and drain connected to the input signal in and signal im lines. The p-channel transistor 3205 has a gate connected to the clock signal clk line and a source and drain connected to the signal im and signal imx lines. The n-channel transistor 3206 has a gate connected to the line of the clock signal clkx, and a source and a drain connected to the lines of the signal im and the signal imx.

  Next, the configuration of the clock comparator 3102 will be described. The p-channel transistor 3211b has a gate connected to the ground, a source connected to the power supply potential, and a drain connected to the line of the output signal outx. In the p-channel transistor 3211a, the gate is connected to the ground, the source is connected to the power supply potential, and the drain is connected to the line of the output signal out. The n-channel transistor 3212b has a gate connected to the signal im line, a drain connected to the output signal outx line, and a source connected to the drain of the n-channel transistor 3213. The n-channel transistor 3212 a has a gate connected to the signal imx line, a drain connected to the output signal out line, and a source connected to the drain of the n-channel transistor 3213. The n-channel transistor 3213 has a gate connected to the line of the clock signal clk and a source connected to the ground.

  The n-channel transistor 3221b has a gate connected to the output signal out line, a drain connected to the output signal outx line, and a source connected to the drain of the n-channel transistor 3222. The n-channel transistor 3221a has a gate connected to the output signal outx line, a drain connected to the output signal out line, and a source connected to the drain of the n-channel transistor 3222. The n-channel transistor 3222 has a gate connected to the line of the clock signal clk and a source connected to the ground.

  The combination of the p-channel transistor 3201 and the n-channel transistor 3202 and the combination of the p-channel transistor 3203 and the n-channel transistor 3204 constitute a transfer gate switch, respectively, and when the clock signal clk becomes high level, the lines of the input signals in and im And signal inx and imx lines are connected to each other. Input signals in and inx become signals im and imx as they are. When the clock signal clk becomes low level, the transfer gate switch is disconnected.

  The combination of the p-channel transistor 3205 and the n-channel transistor 3206 constitutes a transfer gate switch, and connects the signal im line and the signal imx line when the clock signal clk goes low. The signals im and imx are reset to the same potential. When the clock signal clk goes high, this transfer gate switch is disconnected.

  The clock comparator 3102 includes an input element 3231 using a differential pair of n-channel transistors 3212a and 3212b and a regenerative amplifier circuit 3232 using a cross-coupled differential pair of n-channel transistors 3221a and 3221b. The clock comparator 3102 amplifies with a gain larger than that of the input circuit 3111 by the regenerative action of the positive feedback loop. In the input circuit 3111, when the clock signal clk becomes more positive than the clock signal clkx having a complementary relationship thereto, the transfer gate becomes conductive, and the lines of the signals in and inx and the lines of the signals im and imx are connected. At the same time, the n-channel transistor 3213 connected to the sources of the differential pair transistors 3212a and 3212b of the clock comparator is turned on by the clock signal clk, and the operation of the clock comparator 3102 is started. The frequency of the clock signals clk and clkx for controlling the input circuit 3111 and the clock comparator 3102 is 10 GHz, and the input signals in and inx are 40 Gb / s NRZ (non-return-to-zero) signals (the amplitudes are complementary to each other). 300 mVpp in line).

  By providing a switch using a transfer gate, 40 Gbps data can be correctly received by a circuit using a 0.13 um CMOS process. This is because by providing a switch, there is no intersymbol interference from the data bit before the switch is turned on, and the interference from the bit after the bit to be judged by the effect of the band limitation of the switch is also reduced. by.

(13th Embodiment)
FIG. 33 shows a configuration example of a comparator circuit according to the thirteenth embodiment of the present invention. The difference between the present embodiment and the twelfth embodiment is that the transistors for activating the clock comparator 3102 are not source-grounded transistors 3213 and 3222, but n-channel differential pair transistors 3301a, 3301b, 3311a, and 3311b. It is composed of.

  The n-channel transistor 3301a has a gate connected to the line of the clock signal clk, a drain connected to the sources of the transistors 3212a and 3212b, and a source connected to the drain of the n-channel transistor 3303. The dummy circuit 3302 is a circuit equivalent to a circuit including the transistors 3211a, 3211b, 3312a, and 3212b. The n-channel transistor 3301b has a gate connected to the line of the clock signal clkx, a drain connected to the dummy circuit 3302, and a source connected to the drain of the n-channel transistor 3303. The n-channel transistor 3303 has a gate connected to the voltage vbn line and a source connected to the ground.

  The dummy circuit 3312 is a circuit equivalent to the circuit including the transistors 3221a and 3221b. The n-channel transistor 3311b has a gate connected to the line of the clock signal clkx, a drain connected to the dummy circuit 3312, and a source connected to the drain of the n-channel transistor 3313. The n-channel transistor 3311a has a gate connected to the line of the clock signal clk, a drain connected to the sources of the transistors 3221a and 3221b, and a source connected to the drain of the n-channel transistor 3313. The n-channel transistor 3313 has a gate connected to the voltage vbn line and a source connected to the ground.

  When complementary clock signals clk and clkx are added to the differential pair transistors 3301a and 3301b and the differential pair transistors 3311a and 3311b, the current is transferred to the differential pair transistors 3212a and 3212b of the clock comparator, thereby activating the comparator 3102. . The present embodiment has an advantage that the timing variation due to the element variation is small because the timing at which the clock comparator 2102 is activated is determined by the difference between the two differential clock signals clk and clkx.

(Fourteenth embodiment)
FIG. 34 shows a configuration example of a comparator circuit according to the fourteenth embodiment of the present invention. The difference between this embodiment and the twelfth embodiment is that the input circuit 3111 is not a transfer gate switch but a differential amplifier circuit in which the tail current is controlled by a clock signal.

  A configuration of the input circuit 3111 will be described. In the p-channel transistors 3401a and 3401b, the gate is connected to the ground, and the source is connected to the power supply potential. The drain of the transistor 3401b is connected to the signal im line, and the drain of the transistor 3401a is connected to the signal imx line. The n-channel transistor 3402b has a gate connected to the line of the input signal inx, a drain connected to the signal im line, and a source connected to the drain of the n-channel transistor 3403a. The n-channel transistor 3402a has a gate connected to the input signal in line, a drain connected to the signal imx line, and a source connected to the drain of the n-channel transistor 3403a. The n-channel transistor 3403a has a gate connected to the line of the clock signal clk and a source connected to the drain of the n-channel transistor 3405. The dummy circuit 3404 is a circuit equivalent to a circuit including the transistors 3401a, 3401b, 3402a, and 3402b. The n-channel transistor 3403b has a gate connected to the line of the clock signal clkx, a drain connected to the dummy circuit 3404, and a source connected to the drain of the n-channel transistor 3405. The n-channel transistor 3405 has a gate connected to the voltage vbn line and a source connected to the ground.

  In this case, the input circuit 3111 may be activated by the common source transistor 3213 connected to the differential pair similarly to the clock comparator 3102 of the twelfth embodiment, but the input circuit 3111 may be activated by the clock comparator 3102 of the thirteenth embodiment. Similarly, it is activated by current transfer of the differential pair. In this embodiment, unlike the transfer gate, the timing at which the input circuit 3111 switches between the conductive state and the non-conductive state does not depend on the levels of the input signals in and inx, and therefore there is an advantage that no data-dependent timing error occurs.

  In the embodiment, the input circuit 3111 uses differential pairs 3402a and 3402b in which the tail current is switched by current transfer. The input circuit 3111 is activated at the same time as the clock comparator 3102 at the subsequent stage is activated. The gain of the input circuit 3111 is about 3 to 5 times, and the output waveform is obtained by band-limiting the input signals in and inx. That is, the input circuit 3111 operates as an incomplete integration circuit.

  This embodiment has the following advantages. First, since the input circuit 3111 has no gain in the reset state, it is not affected by the input in this state (no intersymbol interference from past bits). Since the clock comparator 3102 starts amplification at the same time as the input circuit 3111 is activated, the comparator 3102 determines the first bit in the activation period. Since there is an integration circuit, the sign of the input signal of the clock comparator 3102 maintains the value determined by the first bit even if the decision bit and the bit after it are inverted, so that no malfunction occurs. In this way, there is an advantage that signal determination that is not affected by the bit before and after the determination bit can be performed.

(Fifteenth embodiment)
FIG. 35 shows a configuration example of a comparator circuit according to the fifteenth embodiment of the present invention. In this embodiment, the period during which the input circuit 3101 (FIG. 31A) transmits a signal is opposite to that of the input circuit 3111 (FIG. 31B) of the third embodiment. The input circuit 3101 includes a differential pair 3402a and 3402b activated by current transfer and a differential pair 3501a and 3051b activated in the opposite phase.

  The gate of the transistor 3403a is connected to the clock signal clkx line, and the gate of the transistor 3403b is connected to the clock signal clk line. The n-channel transistor 3501a has a gate connected to the power supply potential, a drain connected to the signal im line, and a source connected to the drain of the n-channel transistor 3403b. The n-channel transistor 3501b has a gate connected to the power supply potential, a drain connected to the signal imx line, and a source connected to the drain of the n-channel transistor 3403b.

  The gates of the first differential pair 3402a and 3402b are connected to the input signals in and inx, and the gates of the second differential pair 3501a and 3501b are simply connected to the power supply potential. Accordingly, the input circuit 3101 transmits a signal when the first differential pair 3402a and 3402b are activated, but the output of the input circuit 3101 is the period during which the second differential pair 3501a and 3501b is activated. It decays. The clock comparator 3102 amplifies the signal using a period until the output of the input circuit 3101 is attenuated.

  In this embodiment, the input circuit 3101 does not transmit the input change to the output during the period in which the clock comparator 3102 operates, and the comparator input only attenuates during the operation period of the comparator 3102 to reflect the bit changes in the input signals in and inx. do not do. Therefore, there is an advantage that there is no interference between codes inside the comparator 3102.

  FIG. 36 is a modification of the fifteenth embodiment of the present invention. In this embodiment, the gate connection of the differential pair 3501a and 3501b connected to the power supply potential in the embodiment of FIG. 35 is changed to a cross-couple type. The gate of the transistor 3501a is connected to the signal imx line, and the gate of the transistor 3501b is connected to the signal im line. Although the cross-coupled positive feedback (in this embodiment, the gain is smaller than 1) is not so large as to amplify the signal, the signal attenuation rate during the signal holding period can be slowed, and the output amplitude of the clock comparator is the same as that in the embodiment of FIG. There is an advantage that it becomes larger than that.

(Sixteenth embodiment)
FIG. 37 shows a configuration example of a comparator circuit according to the sixteenth embodiment of the present invention. In the present embodiment, the load impedance (output impedance) of the input circuit 3101 is lowered in order to increase the bandwidth when the input circuit 3101 is on (a state in which signal transmission is performed). Therefore, a p-channel transistor 3701 that is always on is inserted between the differential signals im and imx in the circuit of FIG. In the p-channel transistor 3701, the gate is connected to the ground, and the source and drain are connected to the signal im and imx lines. As a result, although the gain of the input circuit 3101 decreases, the clock comparator 3102 at the subsequent stage has a large amplification level, so that sufficient signal amplification is performed as a whole. In this embodiment, the intersymbol interference generated in the input circuit 3101 can be reduced, and the decrease in gain is compensated for in the subsequent stage 3102, so that there is an advantage that a signal with a higher frequency can be received.

(Seventeenth embodiment)
FIG. 38 shows a configuration example of a comparator circuit according to the seventeenth embodiment of the present invention. In the present embodiment, in contrast to the sixteenth embodiment, the p-channel transistor 3701 connected between the differential outputs im and imx is driven by a clock signal in order to increase the bandwidth of the period during which the input circuit 3101 performs signal transmission. Is different. The gate of the p-channel transistor 3701 is connected to the line of the clock signal clkx. As a result, the band of the input circuit 3101 is sufficiently high during the signal transmission period, and the intersymbol interference can be minimized. On the other hand, during the period of holding the signal (actually, the signal is attenuated), the impedance is increased, so that the rate of attenuation is reduced, and a time margin for sufficient amplification by the subsequent clock comparator 3102 is generated. This embodiment has the advantage that both small intersymbol interference and high amplification can be achieved because it is possible to simultaneously increase the band in the signal transmission period of the input circuit 3101 and slow down the attenuation rate in the holding period. is there.

(Eighteenth embodiment)
FIG. 39 shows a configuration example of a comparator circuit according to the eighteenth embodiment of the present invention. The difference between this embodiment and the fourteenth embodiment is that a load of the input circuit 3111 is added with a p-channel transistor 3901 containing the clock signal clk. In the p-channel transistor 3901, the gate is connected to the clock signal clk line, and the source and drain are connected to the signal im and imx lines. The input circuit 3111 is activated simultaneously with the activation of the clock comparator 3102 at the subsequent stage. In the inactive state, the input circuit 3111 is reset because the load (output) of the p-channel transistor 3901 has a low impedance, and simultaneously activated, the load of the p-channel transistor 3901 becomes a high impedance. For this reason, the input circuit 3111 operates as an integral-and-dump type integration circuit. This embodiment has an advantage that the influence of past data can be sufficiently reduced because the impedance of the output node of the input circuit 3111 is kept low in the reset state.

(Nineteenth embodiment)
FIG. 40 shows a configuration example of a comparator circuit according to the nineteenth embodiment of the present invention. In the present embodiment, n-channel transistor differential pairs 4001a and 4001b are used in place of the reset circuit of the p-channel transistor 3901 used in the eighteenth embodiment. The n-channel transistor 4001a has a gate connected to the signal im line, a drain connected to the signal im line, and a source connected to the drain of the n-channel transistor 3403b. The n-channel transistor 4001b has a gate connected to the signal imx line, a drain connected to the signal imx line, and a source connected to the drain of the n-channel transistor 3403b.

  During the reset period, current is transferred to the differential pairs 4001a and 4001b. The differential pair 4001a and 4001b have their gates and outputs connected so as to provide negative feedback. When the differential pair 4001a and 4001b is activated, a low impedance is observed from the input side. The reset is performed by this low impedance. In this embodiment, the reset timing is determined by the differential clock signals clk and clkx as compared with the case where the clock signal clk is directly input to the gate of the p-channel transistor 3901 (FIG. 39) and reset, and therefore the timing depends on the process variation. There is an advantage of not.

(20th embodiment)
FIG. 41 shows a configuration example of a comparator circuit according to the twentieth embodiment of the present invention. In the present embodiment, the following circuit is added to the input circuit 3111 with respect to the fourteenth embodiment. The p-channel transistor 3401c has a gate connected to the ground, a source connected to the power supply potential, and a drain connected to the drain of the n-channel transistor 4103b. The n-channel transistor 4103b has a gate connected to the line of the clock signal clk and a source connected to the drain of the n-channel transistor 4105. The dummy circuit 4104 is a circuit equivalent to the transistor 3401c. The n-channel transistor 4103a has a gate connected to the line of the clock signal clkx, a drain connected to the dummy circuit 4104, and a source connected to the drain of the n-channel transistor 4105. The n-channel transistor 4105 has a gate connected to the voltage vbn line and a source connected to the ground. The n-channel transistors 4101a and 4101b have gates connected to the drains of the transistors 3401c and 4103b. The transistor 4101b has a drain connected to the signal im line and a source connected to the drain of the transistor 3402b. The transistor 4101a has a drain connected to the signal imx line and a source connected to the drain of the transistor 3402a.

  In this embodiment, the input circuit 3111 uses differential pairs 3402a and 3402b that are activated by current transfer. The differential pairs 3402a and 3402b are connected to the load device via the cascode-connected switches of the n-channel transistors 4101a and 4101b on the drain side. The gate of the cascode switch is driven by a dummy circuit 3401c, 4103a, 4103b, 4104, 4105 equivalent to the clock comparator 3102 at the subsequent stage, and the switch 4101a, 4101b is turned off almost simultaneously with the output of the comparator 3102 increasing, The connection between the load and the input is lost. The output signals im and imx are amplified by a clock comparator 3102 that is activated simultaneously with the operation of the input circuit 3111. According to this embodiment, since the reproduction node 3102 is automatically disconnected from the input signals in and inx at a timing when the output of the clock comparator 3102 becomes sufficiently large, there is an advantage that there is no intersymbol interference from the bits after the determination bit. is there. The input circuit 3111 includes a deactivation circuit (including transistors 4101a and 4101b) for deactivation after a predetermined delay time from the activation state. Further, since it is not necessary to reduce the intersymbol interference by lowering the gain of the input circuit 3111, there is an advantage that the amplification degree can be increased.

  As described above, in the twelfth to twentieth embodiments, the operation of the comparator (small aperture time and large amplification) is realized by dividing it into two stages of the input circuit and the clock comparator. A circuit for receiving without any problem is realized.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A first delay line having a plurality of taps for delaying the input signal;
A second delay line having a plurality of taps for delaying the clock signal;
A plurality of clock control comparators each connected to a tap of the first delay line and each clock input line connected to a tap of the second delay line;
A signal processing circuit in which a difference between an input signal delay time by the first delay line and a clock signal delay time by the second delay line is different for each clock control comparator.
(Appendix 2)
In the first delay line, an input signal is input from one end of the delay line and the other end is terminated by the characteristic impedance of the delay line,
The signal processing circuit according to claim 1, wherein the second delay line has a clock signal input from one end of the delay line and the other end terminated with a characteristic impedance of the delay line.
(Appendix 3)
In the first delay line, an input signal is input from one end of the delay line and the other end is terminated by the characteristic impedance of the delay line,
The signal processing circuit according to appendix 1, wherein the second delay line is connected in a ring shape.
(Appendix 4)
The signal processing circuit according to claim 1, wherein delay times between taps of the first and second delay lines are non-uniform.
(Appendix 5)
The signal processing circuit according to appendix 1, wherein the plurality of clock control comparators realize oversampling in which sampling is performed three times or more within a time corresponding to one bit of an input signal.
(Appendix 6)
The signal processing circuit according to claim 1, wherein a direction in which an input signal propagates through the first delay line differs from a direction in which a clock signal propagates through the second delay line with respect to the plurality of clock control comparators.
(Appendix 7)
The signal processing circuit according to appendix 1, wherein the direction in which an input signal propagates through the first delay line and the direction in which a clock signal propagates through the second delay line are the same for the plurality of clock control comparators.
(Appendix 8)
The second delay line is a delay line for delaying clock signals of three or more phases,
2. The signal processing circuit according to claim 1, wherein clock signals obtained by delaying the three or more phase clocks by the second delay line are supplied to the plurality of clock control comparators.
(Appendix 9)
One tap of the first delay line is connected to data input lines of a plurality of clock control comparators, and the clock input line of the plurality of clock control comparators is connected to a different tap of the second delay line. The signal processing circuit described.
(Appendix 10)
The signal processing circuit according to appendix 1, further comprising a selector for selecting a correct input signal based on outputs of the plurality of clock control comparators.
(Appendix 11)
The signal processing circuit according to claim 1, further comprising phase difference output means for outputting a signal representing a phase difference between the input signal and the clock signal based on outputs of the plurality of clock control comparators.
(Appendix 12)
Furthermore, the signal processing circuit of Claim 11 which has a clock signal adjustment means which adjusts the frequency of a clock signal based on the signal showing the phase difference of the said input signal and the said clock signal.
(Appendix 13)
An input circuit that processes the input signal so that the signal transfer characteristic from the input signal to the output signal changes according to the clock signal, and outputs the output signal;
A signal processing circuit having an amplification circuit for amplifying an output signal of the input circuit during a period of being activated by a clock signal;
(Appendix 14)
14. The signal processing circuit according to appendix 13, wherein the amplifier circuit is activated by performing a current switching operation of a differential pair in accordance with a clock signal and causing a current to flow.
(Appendix 15)
14. The signal processing circuit according to appendix 13, wherein the input circuit performs signal transmission from an input signal to an output signal in an activated state and does not perform signal transmission in an inactivated state.
(Appendix 16)
The signal processing circuit according to claim 15, wherein the input circuit is inactivated when the amplifier circuit is activated.
(Appendix 17)
The signal processing circuit according to claim 15, wherein the input circuit is activated when the amplifier circuit is activated.
(Appendix 18)
16. The signal processing circuit according to appendix 15, wherein the amplification circuit amplifies with a gain larger than that of the input circuit by a reproducing action of a positive feedback loop.
(Appendix 19)
The signal processing circuit according to supplementary note 16, wherein the input circuit includes an impedance changing circuit that lowers the output impedance in the activated state.
(Appendix 20)
19. The signal processing circuit according to appendix 18, wherein the input circuit amplifies with an integral characteristic or a reproduction type characteristic in an activated state.
(Appendix 21)
18. The signal processing circuit according to appendix 17, wherein the input circuit includes an impedance changing circuit that sets an output impedance to a low value in an inactive state.
(Appendix 22)
The signal processing circuit according to appendix 19, wherein the impedance changing circuit sets the output impedance to a low value according to a clock signal.
(Appendix 23)
The signal processing circuit according to supplementary note 15, wherein the input circuit includes a deactivation circuit for deactivation after a predetermined time after the activation.

FIGS. 1A and 1B are circuit diagrams showing examples of the principle configuration of demultiplexers (signal processing circuits) according to first to eleventh embodiments of the present invention. FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. It is a circuit diagram which shows the structural example of the demultiplexer by the 1st Embodiment of this invention. It is a circuit diagram which shows the structural example of the demultiplexer by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the demultiplexer by the 3rd Embodiment of this invention. FIG. 6A is a circuit diagram illustrating a configuration example of a negative resistance element, and FIG. 6B is a circuit diagram illustrating a configuration example of a phase shift circuit. It is a circuit diagram which shows the structural example of a phase shift circuit. It is a circuit diagram which shows the structural example of the demultiplexer by the 4th Embodiment of this invention. FIG. 9 is a timing chart for explaining the operation of the circuit of FIG. 8. It is a circuit diagram which shows the structural example of the demultiplexer by the 5th Embodiment of this invention. It is a circuit diagram which shows the structural example of the demultiplexer by the 6th Embodiment of this invention. FIG. 12 is a timing chart for explaining the operation of the circuit of FIG. 11. It is a circuit diagram which shows the structural example of the demultiplexer by the 7th Embodiment of this invention. It is a circuit diagram which shows the structural example of the demultiplexer by the 8th Embodiment of this invention. FIG. 15 is a timing chart for explaining the operation of the circuit of FIG. 14. It is a circuit diagram which shows the structural example of the demultiplexer by the 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the modification of the demultiplexer by the 9th Embodiment of this invention. FIG. 18 is a timing chart for explaining the operation of the circuit of FIG. 17. It is a circuit diagram which shows the structural example of the demultiplexer by the 10th Embodiment of this invention. FIG. 20 is a circuit diagram showing the circuit of FIG. 19 more specifically. FIG. 21 is a circuit diagram showing a more specific circuit of the CDR of FIG. 20. It is a circuit diagram which shows the structural example of the edge generator of FIG. It is a circuit diagram which shows the structural example of the Tally & Vote circuit of FIG. FIG. 24 is a circuit diagram illustrating a configuration example of a Tally comparator in FIG. 23. FIG. 22 is a circuit diagram illustrating a configuration example of an up / down generator of FIG. 21. FIG. 22 is a circuit diagram illustrating a configuration example of an up / down counter in FIG. 21. 27A is a circuit diagram showing a configuration example of the selector controller in FIG. 21, and FIG. 27B is a circuit diagram showing a configuration example of the selector in FIG. FIG. 22 is a circuit diagram illustrating a configuration example of the charge pump in FIG. 21. It is a circuit diagram of a circuit for generating a recovery clock having a correct frequency. It is a circuit diagram which shows the structural example of the demultiplexer by the 11th Embodiment of this invention. FIGS. 31A and 31B are diagrams showing a principle configuration example of a comparator circuit (signal processing circuit) according to the twelfth to twentieth embodiments of the present invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 12th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 13th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 14th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 15th Embodiment of this invention. It is a circuit diagram which shows the structure of the modification of the 15th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 16th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 17th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 18th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 19th Embodiment of this invention. It is a circuit diagram which shows the structural example of the comparator circuit by the 20th Embodiment of this invention. It is a block diagram which shows the structure of the demultiplexer by a prior art. It is a circuit diagram which shows the structure of a latch. It is a circuit diagram of a comparator circuit.

Explanation of symbols

101 delay line 102 characteristic impedance (resistance)
103 Clock comparator (latch)
301 Buffer 302 Phase Detector 303 Charge Pumps 3101 and 3111 Input Circuit 3102 Clock Comparator

Claims (7)

A first delay line having a plurality of taps for delaying the input signal;
A second delay line having a plurality of taps for delaying the clock signal;
Each data input line is connected to a tap of the first delay line, each clock input line is connected to a tap of the second delay line, and a plurality of clocks configured by a connection circuit of a master latch and a slave latch A control comparator;
A selector connected to a subsequent stage of the plurality of clock control comparators, and a selector for selecting the next series of the series having the most data transitions among the series of output signals of the plurality of clock control comparators ;
Have
A signal processing circuit in which a difference between an input signal delay time by the first delay line and a clock signal delay time by the second delay line is different for each clock control comparator. In the first delay line, an input signal is input from one end of the delay line and the other end is terminated by the characteristic impedance of the delay line,
The signal processing circuit according to claim 1, wherein the second delay line has a clock signal input from one end of the delay line and the other end terminated with a characteristic impedance of the delay line. In the first delay line, an input signal is input from one end of the delay line and the other end is terminated by the characteristic impedance of the delay line,
The signal processing circuit according to claim 1, wherein the second delay line is connected in a ring shape.   2. The signal processing circuit according to claim 1, wherein a direction in which an input signal propagates through the first delay line differs from a direction in which a clock signal propagates through the second delay line with respect to the plurality of clock control comparators.   2. The signal processing circuit according to claim 1, wherein the direction in which an input signal propagates through the first delay line and the direction in which a clock signal propagates through the second delay line are the same for the plurality of clock control comparators. . 2. The signal processing circuit according to claim 1, further comprising phase difference output means for outputting a signal representing a phase difference between the input signal and the clock signal based on outputs of the plurality of clock control comparators. 7. The signal processing circuit according to claim 6, further comprising clock signal adjusting means for adjusting a frequency of the clock signal based on a signal representing a phase difference between the input signal and the clock signal.

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