CN215642687U - Daisy chain type data synchronous generating system - Google Patents
Daisy chain type data synchronous generating system Download PDFInfo
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- CN215642687U CN215642687U CN202121415029.8U CN202121415029U CN215642687U CN 215642687 U CN215642687 U CN 215642687U CN 202121415029 U CN202121415029 U CN 202121415029U CN 215642687 U CN215642687 U CN 215642687U
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Abstract
The utility model provides a daisy chain type data synchronous generation system, which is characterized in that a plurality of groups of cascade-connected data generation systems are arranged, and a trigger signal and a clock signal are synchronously processed in a cascade mode, so that multi-channel data synchronous generation is realized. Compared with the prior art, the multi-channel synchronous data generation method and the device have the advantages that the multi-channel synchronous data generation with low cost, high precision and multiple channels can be realized, and the channels can be simply and conveniently deleted and added.
Description
Technical Field
The utility model belongs to the technical field of signal source digital testing, and particularly relates to a daisy chain type data synchronous generation system.
Background
The signal source is widely applied to scenes of electronic equipment, equipment development, production and maintenance guarantee. With the wide application of computers and various digital signal processing technologies, the proportion of the digital part of the digital signal processing technology is developing at an extremely fast speed, and the digital signal processing technology plays an important role in the field of modern digital testing as an important component of a universal signal source, namely a data generation system. For example, under test environments such as nuclear explosion signal parametric analysis, electronic warfare monitoring system test and the like in which real signal scenes are difficult to reproduce or risk cost is extremely high, the data generation system can be matched with the data processing system and the conditioning module to form an arbitrary waveform generator, and the arbitrary waveform generator can accurately simulate and restore the 'real signals'; the data generation system can also be used for verifying the high-speed digital-to-analog conversion chip, performing function test on the semiconductor device, performing compliance and interoperability test meeting emerging standards, and the like. However, as technology develops, the integration of digital system devices becomes higher, and during the testing of these devices, it is often necessary to provide multiple data output signals with precise phase relationships. For example, the operation of a quantum computer needs multiple voltage signals with permitted phase relation, the parallel bus test needs to provide multiple parallel data, and a 3D digital imaging system needs multiple digital excitation sources to be matched with each other to test the whole system. From the above examples, it is obvious that modern digital test systems often require multiple data signals with precise phase relationships.
The multi-channel data generation system needs to solve the problems of clock synchronization and trigger signal synchronization. The current scheme generally selects the number of buffer fan-out or clock fan-out chips corresponding to the number of channels according to the actually required number of channels. And the subsystems buffering the fan-out chip to each channel adopt cables with the same length and material, so that the clock and trigger synchronization of each channel is ensured.
The conventional multi-channel data generation system has the following disadvantages:
SUMMERY OF THE UTILITY MODEL
Aiming at the defects in the prior art, the utility model provides a daisy chain type data synchronous generation system, which is characterized in that a plurality of groups of cascade-connected data generation systems are arranged, and a trigger signal and a clock signal are synchronously processed in a cascade mode, so that multi-channel data synchronous generation is realized. Compared with the prior art, the multi-channel synchronous data generation method and the device have the advantages that the multi-channel synchronous data generation with low cost, high precision and multiple channels can be realized, and the channels can be simply and conveniently deleted and added.
The specific implementation content of the utility model is as follows:
the utility model provides a daisy chain type data synchronous generation system which is connected with an external trigger signal and used for carrying out multichannel synchronous generation of data and outputting of the data, and is characterized by comprising an upper computer and a plurality of groups of data generation systems, wherein each group of data generation systems is connected with the upper computer, and the data generation systems are connected with each other in a cascading manner by a clock signal and a trigger signal;
a set of said data generating systems comprising: the system comprises an FPGA unit, a trigger signal generation module, a first buffer fan-out unit, a crystal oscillator unit, a second buffer fan-out unit, a PLL unit, a clock fan-out unit, an SDRAM storage unit and an FMC connector; a counting delay module is arranged in the FPGA unit;
the trigger signal generation module is connected with the FPGA unit through enabling signals; the trigger signal generation module is also connected with the first buffering fan-out unit through a trigger signal and is connected with the counting delay module of the FPGA unit through the first buffering fan-out unit; the FPGA unit is respectively connected with the upper computer and the FMC connector;
the second buffer fan-out unit is connected with the PLL unit, then connected with the clock fan-out unit and respectively connected with the SDRAM storage unit and the FMC connector through the clock fan-out unit; the FMC connector outputs the generated data;
the cascade structure formed between each group of data generation systems is as follows:
the trigger signal generating module of the first-stage data generating system is connected with an external trigger signal and is connected with the trigger signal generating module of the second-stage data generating system through a first buffering fan-out unit in sequence; the trigger signal generating modules in the data generating systems after the second level are connected with the first buffer fan-out units of the corresponding data generating systems at the upper level through trigger signals;
the second buffer fan-out unit of the first-stage data generation system is connected with the crystal oscillator unit in the first-stage data generation system through a clock signal, and the second buffer fan-out unit of the second-stage data generation system is connected with the clock signal through the second buffer fan-out unit; and the second buffer fan-out unit of the data generation system after the second stage is connected with the buffer fan-out unit of the corresponding data generation system at the upper stage by a clock signal.
In order to better implement the present invention, the data generating system is further provided with a first delay line unit, the first delay line unit includes a delay line chip, an input end of the delay line chip is connected to the counting delay module, and an output end of the first delay line unit is connected to the FPGA unit.
In order to better implement the present invention, a power module is further disposed in the data generating system, and the power module is connected to the delay line core sheet of the first delay line unit.
In order to better implement the present invention, the data generating system is further provided with a second delay line unit, the second delay line unit includes a delay line chip, an input end of the delay line chip is connected to the clock fan-out unit, and an output end of the second delay line unit is connected to the FPGA unit.
In order to better implement the present invention, a power module is further disposed in the data generating system, and the power module is connected to the delay line core sheet of the second delay line unit.
In order to better implement the utility model, further, the time delay core chip adopts a SY100EP195 chip of ADI company.
In order to better implement the utility model, further, the clock fan-out unit adopts an HMC7044 chip of ADI company.
In order to better implement the utility model, a power module is further arranged in the data generation system, and the power module is respectively connected with the trigger signal generation module, the FPGA unit, the first buffer fan-out unit, the second buffer fan-out unit, the crystal oscillator unit, the PLL unit, the clock fan-out unit, and the buffer fan-out unit.
In order to better implement the utility model, further, the clock fan-out unit adopts an HMC7044 chip of ADI company.
Compared with the prior art, the utility model has the following advantages and beneficial effects:
the utility model realizes decentralization in a daisy chain mode, and solves the problems of structure and wiring caused by a central node; in addition, each stage in the chrysanthemum lotus is only required to be expanded to the next stage, so that high clock fan-out is not needed, and the load of a starting signal is reduced; for expansibility, the chrysanthemum lotus needs to be expanded by one stage, and the expansion capability is not influenced by the fan-out capability of the clock. After the output channel is added, the synchronization of the clock and the trigger can be realized only by changing the delay of the front n-1 level from software, and hardware does not need to be changed, so the expansion capability is very strong.
Drawings
FIG. 1 is a schematic diagram of a multi-stage cascaded data generation system of the present invention;
FIG. 2 is a schematic diagram of the sampling clock and trigger signal phases versus the data output duty cycle thereunder in accordance with the present invention;
FIG. 3 is a schematic diagram of a cascaded system structure of two data generating systems according to the present invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
the embodiment provides a daisy chain type data synchronous generation system, which is connected with an external trigger signal as shown in fig. 1 and fig. 3, and is used for performing multi-channel synchronous data generation and outputting data, and the daisy chain type data synchronous generation system is characterized by comprising an upper computer and a plurality of groups of data generation systems, wherein each group of data generation systems is connected with the upper computer, and the data generation systems are connected with each other in a cascading manner through clock signals and the trigger signal;
a set of said data generating systems comprising: the system comprises an FPGA unit, a trigger signal generation module, a first buffer fan-out unit, a crystal oscillator unit, a second buffer fan-out unit, a PLL unit, a clock fan-out unit, an SDRAM storage unit and an FMC connector; a counting delay module is arranged in the FPGA unit;
the trigger signal generation module is connected with the FPGA unit through enabling signals; the trigger signal generation module is also connected with the first buffering fan-out unit through a trigger signal and is connected with the counting delay module of the FPGA unit through the first buffering fan-out unit; the FPGA unit is respectively connected with the upper computer and the FMC connector;
the second buffer fan-out unit is connected with the PLL unit, then connected with the clock fan-out unit and respectively connected with the SDRAM storage unit and the FMC connector through the clock fan-out unit; the FMC connector outputs the generated data;
the cascade structure formed between each group of data generation systems is as follows:
the trigger signal generating module of the first-stage data generating system is connected with an external trigger signal and is connected with the trigger signal generating module of the second-stage data generating system through a first buffering fan-out unit in sequence; the trigger signal generating modules in the data generating systems after the second level are connected with the first buffer fan-out units of the corresponding data generating systems at the upper level through trigger signals;
the second buffer fan-out unit of the first-stage data generation system is connected with the crystal oscillator unit in the first-stage data generation system through a clock signal, and the second buffer fan-out unit of the second-stage data generation system is connected with the clock signal through the second buffer fan-out unit; and the second buffer fan-out unit of the data generation system after the second stage is connected with the buffer fan-out unit of the corresponding data generation system at the upper stage by a clock signal.
Furthermore, a first delay line unit is further arranged in the data generation system, the first delay line unit comprises a delay line chip, the input end of the delay line chip is connected with the counting delay module, and the output end of the first delay line unit is connected with the FPGA unit.
Furthermore, a power supply module is further arranged in the data generation system, and the power supply module is connected with the delay line core sheet of the first delay line unit.
Furthermore, a second delay line unit is further arranged in the data generation system, the second delay line unit comprises a delay line chip, the input end of the delay line chip is connected with the clock fan-out unit, and the output end of the second delay line unit is connected with the FPGA unit.
Further, the time delay core chip adopts a SY100EP195 chip of ADI company.
Further, the clock fan-out unit adopts an HMC7044 chip of ADI company.
Furthermore, a power module is further arranged in the data generation system, and the power module is respectively connected with the trigger signal generation module, the FPGA unit, the first buffer fan-out unit, the second buffer fan-out unit, the crystal oscillator unit, the PLL unit, the clock fan-out unit, the buffer fan-out unit and the delay line core sheet.
Further, the clock fan-out unit adopts an HMC7044 chip of ADI company.
The working principle is as follows: the data generation system and the upper computer communicate through a PCIe bus. The data generation system mainly comprises a clock module, a power module, a trigger module, a storage module, an FPGA (field programmable gate array) and an FMC (frequency modulation controller) connector. Wherein: the clock module is responsible for selecting a clock source to serve as a clock circuit of the system and provide a programmable reference clock and a working clock for the whole system; the trigger module is responsible for completing a trigger function and outputting a trigger signal; the storage module is responsible for storing data to be output; the FPGA is responsible for controlling the whole system; the FMC connector is used as a general data interface and is a channel for outputting system data.
Example 2:
the embodiment further provides an application of the daisy chain data synchronous generation system, which specifically comprises:
a data synchronization generation method based on a daisy chain cascade data generation system is connected with an external trigger signal, and is used for carrying out multi-channel synchronization to generate data and outputting the data, and the method comprises the following steps:
step 1: setting a plurality of groups of data generation systems with corresponding quantity according to actual processing requirements;
step 2: setting a series order for a plurality of groups of data generation systems, and then constructing a cascaded data generation system, wherein the constructed operation is as follows: connecting the data generating system of the first stage with an external trigger signal, and then sequentially connecting the trigger signal of the previous stage from the data generating system of the second stage as the trigger signal of the current stage; a crystal oscillator unit is arranged in a first-stage data generation system to generate clock signals, and then the clock signals of the previous stage are sequentially connected from a second-stage data generation system as the clock signals of the current stage;
and step 3: step-by-step synchronous alignment of a clock signal and a trigger signal is carried out on the cascaded data generation system;
and 4, step 4: sending chip configuration data and data to be generated to the FPGA unit through the upper computer;
and 5: the FPGA unit stores data to be generated to an SDRAM storage module and then performs related configuration of data generation;
step 6: respectively adjusting the output signal phases of the clock fan-out units of the previous n-1 level system by taking the clock signals sent by the clock fan-out units of the nth level data generation system as a reference;
and 7: respectively adjusting the phases of the trigger signals of the previous n-1-level data generation systems by taking the trigger signal of the nth-level data generation system as a reference;
and 8: when the trigger signal and the clock signal of the n-stage system are simultaneously effective, the data generation systems of all stages start to output the generated data stream under the sampling clock.
Further, a set of the data generation systems employed in the step 1 includes: the system comprises an FPGA unit, a trigger signal generation module, a first buffer fan-out unit, a crystal oscillator unit, a second buffer fan-out unit, a PLL unit, a clock fan-out unit, an SDRAM storage unit and an FMC connector; a counting delay module is arranged in the FPGA unit;
the trigger signal generation module is connected with the FPGA unit through enabling signals; the trigger signal generation module is also connected with the first buffering fan-out unit through a trigger signal and is connected with the counting delay module of the FPGA unit through the first buffering fan-out unit; the FPGA unit is respectively connected with the upper computer and the FMC connector;
the second buffer fan-out unit is connected with the PLL unit, then connected with the clock fan-out unit and respectively connected with the SDRAM storage unit and the FMC connector through the clock fan-out unit; the FMC connector outputs the generated data.
Further, in step 2, the specific operation of the cascade building of the trigger signal in the cascaded data generation system is as follows:
connecting an external trigger signal as an initial trigger signal on a trigger signal generating module of a first-stage data generating system; then, a trigger signal output by a trigger signal generating module of the first-stage data generating system is processed by a first buffering fan-out unit of the first-stage data generating system and then is connected to a trigger signal generating module of the second-stage data generating system to be used as a trigger signal of the second-stage data generating system; and in sequence, starting from the second-stage data generation system, the trigger signal output by the trigger signal generation module of the previous-stage data generation system is processed by the corresponding first buffering fan-out unit and then is connected to the trigger signal generation module of the current-stage data generation system to serve as the trigger signal of the current-stage data generation system.
Further, in the step 2, the specific operation of the cascade building of the clock signal in the cascaded data generation system is as follows:
connecting a crystal oscillator unit of the first-stage data generation system to a second buffer fan-out unit to serve as an initial clock signal, and then connecting a clock signal output by the second buffer fan-out unit of the first-stage data generation system to a second-stage data generation system to serve as a clock signal of the second-stage data generation system; and in sequence, starting from the second-stage data generation system, the clock signal output by the second buffer fan-out unit of the data generation system of the previous stage is sequentially sent to the second buffer fan-out unit of the data generation system of the current stage as the clock signal of the data generation system of the current stage.
Further, in step 6, when the interval between the clock signal output by the clock fan-out unit of the data generation system at the k-1 th stage and the clock signal time of the clock fan-out unit of the data generation system at the k-1 th stage is tL, the clock fan-out chip of the system at the k-th stage is delayed by (n-k) × tL and then the clock signal is output, so that the phase alignment of the clock signals in the cascaded data generation system is realized.
Furthermore, a first delay line unit is also arranged in the data generation system, the first delay line unit comprises a delay line chip, the input end of the delay line chip is connected with the counting delay module, and the output end of the first delay line unit is connected with the FPGA unit; the trigger signal in the data generation system of the current stage is adjusted again by the first delay line unit.
Further, in step 7, when the time interval between the trigger signal of the k-1 th-stage data generating system and the trigger signal of the k-th-stage data generating system is tD, two-stage adjustment is performed through the counting delay module and the first delay line unit of the k-th-stage system, and the trigger signal is delayed by (n-k) × tD and then sent back to the FPGA unit, so that the trigger signals of the n-stage cascaded data generating systems are all within one sampling clock period.
Furthermore, a second delay line unit is also arranged in the data generation system, the second delay line unit comprises a delay line chip, the input end of the delay line chip is connected with the clock fan-out unit, and the output end of the second delay line unit is connected with the FPGA unit; and the clock fan-out unit regulates the clock signal again through the second delay line unit.
The working principle is as follows: the specific thought steps of the utility model are as follows:
1) and the data generation systems are cascaded in a daisy chain topology mode through the special coaxial lines with uniform specifications.
2) And the upper computer sends the configuration data of each chip and the data to be generated to the FPGA through a PCIe bus interface.
3) Each level of data generation module corresponds to an upper computer, and the upper computer sends configuration information of each module and data to be generated to an FPGA chip of the data generation system through a PCIe bus interface.
4) The FPGA stores data to be generated to a storage module, and then other modules are configured.
5) And respectively adjusting the output signal phase of the clock fan-out chip of the previous n-1 level system by taking the nth level system clock fan-out signal as a reference. Ensuring n-level system clock fan-out signal phase alignment.
6) And connecting an external trigger signal to a trigger module of the first-level system, and completing triggering.
7) And respectively adjusting the phases of the trigger signals of the previous n-1 level systems by taking the nth level trigger signal as a reference. And the precise alignment of the phases of the trigger signals of the n-level system is ensured.
8) When the trigger signals of the n-level system are simultaneously effective, the system starts to output the data stream.
Among them, it should be noted that:
1. the hardware layout of each level of system is the same, and a coaxial line with a special uniform specification is selected during cascading;
2. the first-stage system selects a crystal oscillator as a clock source of the first-stage system, selects an external trigger signal as a trigger source, and selects a buffer fan-out signal and a trigger output signal of a previous stage as a clock source and a trigger source of the first-stage system respectively;
3. after physical cascade, each level system determines the level to which the system belongs, and immediately selects the time of corresponding delay of the clock fan-out chip. Supposing that the time interval between the k-1 level clock fan-out signal and the k level clock fan-out signal is tL, the k level system clock fan-out chip should delay (n-k) tL and then output the clock signal;
4. after physical cascading, each level system determines the level to which the level system belongs so as to adjust the delay time of the trigger signal. Assuming that the time interval between the k-1 stage trigger signal and the k stage trigger signal is tD, the counting delay module and the delay line module of the k stage system perform two-stage adjustment, namely, the trigger signal is delayed by (n-k) tD and then sent back to the FPGA;
the delay of the trigger signal is provided with a coarse adjustment module and a fine adjustment module, the coarse adjustment is completed by a counting delay module in the FPGA, and the fine adjustment is completed by a delay wire core sheet.
Example 3:
based on the above embodiment 2, the present embodiment provides a data synchronization generation method based on a daisy chain cascade data generation system based on the requirement of a modern digital test system analyzed by the background technology for generating multiple data signals with precise phase relationship, and finally generates multiple data outputs with precise phase relationship by precisely adjusting clock signals and trigger signals of each stage of system, and the number of channels can be expanded. The system cascade block diagram is shown in fig. 1.
In order to achieve the above purpose, the utility model provides the following technical scheme: an inter-system multi-channel precision synchronization technology. The technical key is the synchronization of the sampling clock signal and the trigger signal, namely, the phase alignment of the sampling clock and the trigger signal of each data generation system is required. The precondition of clock signal phase alignment is to ensure that n systems have the same clock source, and then the phase of the system working clock is programmed through a clock fan-out chip. After the phases of the trigger signals of n systems are ensured to be the same, the n data generating modules start to output data when the synchronous trigger signals are true. The phase alignment of the clock signals mainly means that the working clocks of the data output must be synchronous, the synchronization of the trigger signals means that the rising edges of the synchronous trigger signals are in the same working clock period of the data output, and the specific periodic signal relationship is shown in fig. 2.
The method comprises the following specific steps:
a) and the data generation systems are cascaded in a daisy chain topology mode through the special coaxial lines with uniform specifications. The first-stage system selects a crystal oscillator as a clock source of the first-stage system, selects an external trigger signal as a trigger source, and selects a buffering fan-out signal and a trigger output signal of a previous stage as a clock source and a trigger source of the second-stage system respectively.
b) Each system upper computer sends each chip configuration data and data to be generated to an FPGA (field programmable gate array) through a PCIe (peripheral component interface express) bus interface.
c) The FPGA stores data to be generated to a storage module, and then other modules are configured.
d) And respectively adjusting the output signal phase of the clock fan-out chip of the previous n-1 level system by taking the nth level system clock fan-out signal as a reference. Assuming that the time interval between the k-1 th level clock fan-out signal and the k-th level clock fan-out signal is tL, the k-th level system clock fan-out chip should delay (n-k) × tL and then output the clock signal. It is most important to ensure that the n-level system sampling clock signals are phase aligned.
e) And respectively adjusting the phases of the trigger signals of the previous n-1 level systems by taking the nth level trigger signal as a reference. And assuming that the time interval between the k-1 stage trigger signal and the k stage trigger signal is tD, the counting delay module and the delay line module of the k stage system perform two-stage adjustment, and the trigger signal is delayed by (n-k) × tD and then sent back to the FPGA, so that the trigger signals of the n stage system are ensured to be in one sampling clock period.
When the trigger signals of the n-level systems are simultaneously effective, the systems of all levels start to output data streams under the sampling clock.
The other parts of this embodiment are the same as those of embodiment 2, and thus are not described again.
Example 4:
this embodiment is based on any of the above embodiments 2-3, and is described with reference to fig. 1, fig. 2, and fig. 3, by taking a two-stage data generation system cascade as an example, so as to enable those skilled in the art to better understand the present invention. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
First, as shown in fig. 3, the SMA1 of the first stage system is connected to the input port of the external trigger source of the trigger signal generating module of the second stage, and the SMA3 of the first stage system is connected to the SMA2 of the second stage system. And the upper computer sends the configuration data of each chip and the data to be generated to the FPGA through a PCIe bus interface. The first-stage system is externally connected with an external trigger source, and the first-stage system and the second-stage system select clock signals at the self crystal oscillator and the SMA2 as clock sources of a clock circuit of the self system through two-out-of-one selectors respectively. The clock circuit includes a clock source, a PLL, and a clock fan-out chip, which plays a very important role in distributing a programmable clock signal for the entire system. The clock fan-out chip selects HMC7044 of ADI company, which can realize 14-path clock fan-out and can program respective delay, the resolution bit of delay adjustment is 25ps, and the maximum adjustable delay is 300 ns. Considering that the sampling clock of the two-stage system data output needs to keep a precise phase relation, the path of signal needs to be adjusted again by a delay line chip with higher adjustment resolution. The delay line chip selects SY100EP195 of ADI, the maximum adjustable delay of the delay line chip is 12.2ns, and the adjustment precision is 10 ps. This ensures that the sampling clock maintains a precise phase relationship. And the trigger signal generation module completes triggering and outputs a trigger signal after receiving the trigger enable signal of the FPGA under the excitation of the trigger source. And an improved single clock carry counting method is adopted to carry out coarse delay on the trigger signal. Counting and delaying are carried out in the FPGA, and the trigger signal is released after the specified time is reached, so that the trigger signal is allowed to reach the delay line chip. And then the trigger signal is subjected to phase fine adjustment through the delay line chip. When the two system trigger signals are simultaneously effective, the FPGA reads the data in the storage module, and the 2 data generation systems start to output the data. Ideally the phase error of the two system outputs should be zero, thus achieving a synchronous output for the 2 data generating system.
Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.
Claims (9)
1. A daisy chain type data synchronous generation system is connected with an external trigger signal, performs multi-channel synchronous data generation and outputs data, and is characterized by comprising an upper computer and a plurality of groups of data generation systems, wherein each group of data generation systems is connected with the upper computer, and the data generation systems are connected with each other in a cascading manner by a clock signal and a trigger signal;
a set of said data generating systems comprising: the system comprises an FPGA unit, a trigger signal generation module, a first buffer fan-out unit, a crystal oscillator unit, a second buffer fan-out unit, a PLL unit, a clock fan-out unit, an SDRAM storage unit and an FMC connector; a counting delay module is arranged in the FPGA unit;
the trigger signal generation module is connected with the FPGA unit through enabling signals; the trigger signal generation module is also connected with the first buffering fan-out unit through a trigger signal and is connected with the counting delay module of the FPGA unit through the first buffering fan-out unit; the FPGA unit is respectively connected with the upper computer and the FMC connector;
the second buffer fan-out unit is connected with the PLL unit, then connected with the clock fan-out unit and respectively connected with the SDRAM storage unit and the FMC connector through the clock fan-out unit; the FMC connector outputs the generated data;
the cascade structure formed between each group of data generation systems is as follows:
the trigger signal generating module of the first-stage data generating system is connected with an external trigger signal and is connected with the trigger signal generating module of the second-stage data generating system through a first buffering fan-out unit in sequence; the trigger signal generating modules in the data generating systems after the second level are connected with the first buffer fan-out units of the corresponding data generating systems at the upper level through trigger signals;
the second buffer fan-out unit of the first-stage data generation system is connected with the crystal oscillator unit in the first-stage data generation system through a clock signal, and the second buffer fan-out unit of the second-stage data generation system is connected with the clock signal through the second buffer fan-out unit; and the second buffer fan-out unit of the data generation system after the second stage is connected with the buffer fan-out unit of the corresponding data generation system at the upper stage by a clock signal.
2. The daisy-chained data synchronous generation system as claimed in claim 1, wherein a first delay line unit is further arranged in the data generation system, the first delay line unit includes a delay line chip, an input end of the delay line chip is connected to the counting delay module, and an output end of the first delay line unit is connected to the FPGA unit.
3. The daisy-chained data synchronous generating system as claimed in claim 2, wherein a power module is further provided in the data generating system, and the power module is connected to the delay line core of the first delay line unit.
4. The daisy-chained data synchronous generating system as claimed in claim 1, wherein a second delay line unit is further disposed in the data generating system, the second delay line unit includes a delay line chip, an input end of the delay line chip is connected to the clock fan-out unit, and an output end of the second delay line unit is connected to the FPGA unit.
5. The daisy-chained data synchronous generating system as claimed in claim 4, wherein a power module is further provided in the data generating system, and the power module is connected to the delay line chip of the second delay line unit.
6. The daisy-chained data synchronization system as claimed in claim 2, 3, 4 or 5, wherein said delay line chip is SY100EP195 chip from ADI.
7. The daisy-chained data synchronization generation system of claim 6, wherein the clock fan-out unit is implemented using an ADI HMC7044 chip.
8. The daisy-chained data synchronous generating system as claimed in claim 1, wherein a power module is further provided in the data generating system, and the power module is respectively connected to the trigger signal generating module, the FPGA unit, the first buffer fan-out unit, the second buffer fan-out unit, the crystal oscillator unit, the PLL unit, the clock fan-out unit, and the buffer fan-out unit.
9. The daisy chained data synchronization generating system as claimed in claim 1, 2, 3, 4, 5 or 8, wherein said clock fan-out unit is implemented by ADI HMC7044 chip.
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| CN117278188B (en) * | 2023-11-21 | 2024-02-23 | 深圳市鼎阳科技股份有限公司 | Signal source synchronization system and synchronization method thereof |
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