TWI658700B - Integrated circuit, multi-channels transmission apparatus and signal transmission method thereof - Google Patents

Abstract

An integrated circuit, a multi-channel transmission device, and a signal transmission method thereof. The multi-channel transmission device includes a pre-stage circuit, a clock signal generator, and a post-stage circuit. The pre-stage circuit receives a plurality of first clock signals and a plurality of data signals, selects one of the first clock signals as a reference clock signal, transmits a data signal according to the reference clock signal, and generates a plurality of relays respectively. signal. The clock signal generator generates a first clock signal according to the second clock signal, wherein the frequency of the second clock signal is higher than the frequency of the first clock signal. The subsequent circuit transmits the relay signal according to the second clock signal to generate a plurality of output signals, respectively. Among them, the pre-stage circuit is a digital circuit, and the post-stage circuit is an analog circuit.

Description

Integrated circuit, multi-channel transmission device and signal transmission method thereof

The invention relates to an integrated circuit, a multi-channel transmission device and a signal transmission method thereof, and in particular to an integrated circuit, a multi-channel transmission device and a signal transmission method thereof for reducing data transmission skew.

With the advancement of electronic technology, electronic equipment has become an important tool in people's lives. Integrated circuits in electronic equipment are often provided with multi-channel transmission devices to provide high-frequency data transmission capabilities.

However, in a multi-channel transmission device, a skew in data transmission may often occur and cause a delay in data transmission. The skew of data transmission may be caused by the difference in the routing of clock signal transmission wires between multiple channels, the analog circuits between multiple channels and the phase of high-speed (serial) clock signals and slow (parallel) clock signals after frequency division And other factors such as Clock Domain Crossing (CDC).

In particular, when a metastability state occurs, a data transmission offset that may be generated by a multi-channel transmission device is enlarged, resulting in more serious data transmission delays.

The invention provides an integrated circuit, a multi-channel transmission device and a signal transmission method thereof, which can effectively reduce the transmission delay generated during data transmission.

The multi-channel transmission device of the present invention includes a pre-stage circuit, a clock signal generator, and a post-stage circuit. The pre-stage circuit receives a plurality of first clock signals and a plurality of data signals, selects one of the first clock signals as a reference clock signal, transmits a data signal according to the reference clock signal, and generates a plurality of relays respectively. signal. The clock signal generator receives the second clock signal and generates a clock signal according to the second clock signal, wherein the frequency of the second clock signal is higher than the frequency of the first clock signal. The post-stage circuit is coupled to the pre-stage circuit and the clock signal generator, and transmits a relay signal to generate a plurality of output signals respectively according to the second clock signal. The preceding circuit includes a parallel flag signal synchronization circuit. The parallel flag signal synchronization circuit receives the flag signal and synchronizes the flag signal according to the reference clock signal to generate a first synchronization flag signal. The preceding circuit combines the first synchronization flag signal into each relay signal, and Transfer to the subsequent circuit. Among them, the pre-stage circuit is a digital circuit, and the post-stage circuit is an analog circuit.

The integrated circuit of the present invention includes a multi-channel transmission device. The multi-channel transmission device includes the clock signal generator as described above, at least one preceding stage circuit as described above, and at least one subsequent stage circuit as described above.

The multi-channel signal transmission method of the present invention includes: providing a pre-stage circuit to receive a plurality of first clock signals and a plurality of data signals, selecting one of the first clock signals as a reference clock signal, and according to the reference clock A clock signal is used to transmit data signals and generate multiple relay signals respectively; a clock signal generator is provided to generate a first clock signal based on a second clock signal, wherein the frequency of the second clock signal is higher than the first clock signal The frequency of the signal; providing a post-stage circuit to transmit the relay signal to generate multiple output signals according to the second clock signal; and causing the pre-stage circuit to receive the flag signal and synchronizing the flag signal based on the reference clock signal to A first synchronization flag signal is generated, wherein the first-stage circuit combines the first synchronization flag signal into each relay signal and transmits it to the subsequent-stage circuit. The pre-stage circuit is a digital circuit, and the post-stage circuit is an analog circuit.

Based on the above, the present invention distinguishes a multi-channel transmission device into a pre-stage circuit of a digital circuit and a post-stage circuit of an analog circuit. The subsequent stage circuit, which is an analog circuit, performs data transmission based on a relatively high frequency second clock signal. In this way, even when metastability occurs, it can effectively reduce the possible data transmission skew and increase the speed of data transmission.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Please refer to FIG. 1, which is a schematic diagram of a multi-channel transmission device according to an embodiment of the present invention. The multi-channel transmission device 100 includes a pre-stage circuit 110, a post-stage circuit 120, and a clock signal generator 130. The pre-stage circuit 110 is coupled to the clock signal generator 130. The pre-stage circuit 110 receives a multi-channel clock CKx (p) and a multi-channel data DTx (p). The multi-channel clock CKx (p) includes multiple first clock signals PMAD_CK0 ~ PMAD_CKN, and the multi-channel data DTx ( p) Contains multiple parallel data signals DT0 ~ DTN. The pre-stage circuit 110 selects the first clock signal PMAD_CK0 ~ PMAD_CKN as one of the multi-channel clocks CKx (p) as the reference clock signal. The pre-stage circuit 110 receives multi-channel data DTx (p) and outputs a multi-channel relay signal MSx (p) according to the reference clock signal. The multi-channel relay signal MSx (p) includes multiple parallel relays. Signals MS0 ~ MSN.

The post-stage circuit 120 is coupled to the pre-stage circuit 110 and the clock signal generator 130. The post-stage circuit 120 receives the multi-channel relay signal MSx (p) and outputs a multi-channel output signal TXPNx (s) according to the second clock signal CK (s). The multi-channel output signal TXPNx (s) includes multiple signals. The output signals TXPN0 ~ TXPNN of each sequence. The clock signal generator 130 is configured to receive the second clock signal CK (s) and generate a multi-channel clock CKx (p) according to the second clock signal CK (s). Among them, the frequency of the multi-channel clock CKx (p) is lower than the frequency of the second clock signal CK (s).

In this embodiment, the clock signal generator 130 performs a frequency division operation on the second clock signal CK (s) according to a plurality of different divisors to generate a multi-channel clock CKx (p). The pulse CKx (p) has a plurality of first clock signals PMAD_CK0 ~ PMAD_CKN with the same frequency and different phases. The above divisor may be any real number greater than 1, and is not particularly limited.

It should be noted that in this embodiment, the pre-stage circuit 110 is a digital circuit, and the post-stage circuit 120 is an analog circuit. In addition, the pre-stage circuit 110 selects the first clock signal PMAD_CK0 ~ PMAD_CKN of one of the multi-channel clocks CKx (p) as the reference clock signal, and performs multi-channel data DTx according to the reference clock signal having a relatively low frequency. (p) The transmission action. Because the pre-stage circuit 110 is a digital circuit, the state of the data skew generated by the pre-stage circuit 110 can be controlled by using Static Timing Analysis (STA) technology.

On the other hand, in the post-stage circuit 120, the transmission operation of the multi-channel relay signal MSx (p) is performed according to the second clock signal CK (s) having a relatively high frequency. In this way, the post-stage circuit 120 in the form of an analog circuit can be designed based on a single clock signal, which can reduce the design complexity of the design to overcome the state of data skew. In addition, by performing a data transmission operation based on a relatively high-frequency second clock signal CK (s), even when a phenomenon of a metastability state occurs, the degree of data shift can be reduced to lowest.

Please refer to FIG. 2 below, which illustrates a schematic circuit diagram of a multi-channel transmission device according to another embodiment of the present invention. The multi-channel transmission device 200 includes a pre-stage circuit 210, a post-stage circuit 220, and a clock signal generator 230. The pre-stage circuit 210 includes a plurality of digital transmission channels LANE [0] to LANE [3], a parallel flag signal synchronization circuit SYNC1 (p), and a selector SEL (p). The digital transmission channels LANE [0] ~ LANE [3] respectively receive parallel data signals DT0 ~ DT3, wherein each data signal DT0 ~ DT3 is a parallel signal having multiple bits. The selector SEL (p) receives the multi-channel clock CKx (p) generated by the clock signal generator 230, and selects one of the multi-channel clock CKx (p) to generate a reference clock signal CK (p).

The digital transmission channels LANE [0] ~ LANE [3] respectively have a flip-flop group 211-214, and the input ends of the flip-flop group 211-214 receive data signals DT0 ~ DT3, respectively. An appropriate transmission delay circuit DE1 to DE3 can be set (or not set) between the clock ends of the flip-flop groups 211 to 214 and the selector SEL (p) so that the flip-flop groups 211 to 214 are based on the reference clock signal CK. (p) The timings of the triggered actions are substantially the same.

The flip-flop groups 211 to 214 perform data transmission operations of the data signals DT0 to DT3 according to the reference clock signal CK (p), and generate parallel relay signals MS0 to MS3 at the outputs of the flip-flop groups 211 to 214 respectively .

On the other hand, the parallel flag signal synchronization circuit SYNC1 (p) receives a flag signal TXFLAG (p), and performs a synchronization operation of the flag signal TXFLAG (p) according to the reference clock signal CK (p) to generate a synchronization flag. The flag signal FLAG (p), and the source of the flag signal TXFLAG (p) in the foregoing may be a reset signal or a start signal. In addition, the pre-stage circuit 210 combines the synchronization flag signal FLAG (p) into each of the relay signals MS0 ~ MS3, and transmits the combined signal to the post-stage circuit 220.

It is worth mentioning that each of the flip-flop groups 211 to 214 can have multiple flip-flops. The number of flip-flops in each of the flip-flop groups 211-214 can be compared with the number of bits of each data signal DT0-DT3 Match.

The post-stage circuit 220 includes a plurality of analog transmission channels ALANE [0] ~ ALANE [3] corresponding to the digital transmission channels LANE [0] ~ LANE [3], respectively. The analog transmission channels ALANE [0] ~ ALANE [3] include flip-flop groups 221 ~ 224, sequence flag signal synchronization circuits SYNC2 ~ SYNC5, parallel sequence signal conversion circuits 250 ~ 253, and output stage flip-flops 225 ~ 228, respectively.

The flip-flop groups 221 to 224 are respectively coupled to the flip-flop groups 211 to 214 and the parallel flag signal synchronization circuit SYNC1 (p), and are respectively used to receive the relay signals MS0 to MS3 and the synchronization flag signal FLAG (p ). The flip-flop groups 221 to 224 transmit the relay signals MS0 to MS3 and the synchronization flag signal FLAG (p) to the sequence flag signal synchronization circuits SYNC2 to SYNC5 of the subsequent circuit 220 according to the reference clock signal CK (p) and Parallel sequence signal conversion circuits 250 ~ 253. In the foregoing, the number of flip-flops in each of the flip-flop groups 221 to 224 is substantially larger than the number of flip-flops in each of the flip-flop groups 211 to 214. It is worth mentioning that appropriate transmission delay circuits DE4 to DE7 can be respectively set on the clock ends of the flip-flop groups 221 to 224 to adjust the triggered time points of the flip-flop groups 221 to 224 to be substantially the same.

In this embodiment, the flip-flop groups 221 to 224 generate the first data signals DP0 to DP3 and the flags DP_FLAG0 to DP_FLAG3 respectively, wherein each of the first data signals DP0 to DP3 is a parallel signal having multiple bits. The first data signals DP0 ~ DP3 are respectively transmitted to the parallel sequence signal conversion circuits 250 ~ 253, and the flags DP_FLAG0 ~ DP_FLAG3 are respectively transmitted to the sequence flag signal synchronization circuits SYNC2 ~ SYNC5. The sequence flag signal synchronization circuits SYNC2 to SYNC5 synchronize with the flags DP_FLAG0 to DP_FLAG3 respectively according to the second clock signal CK (s), and generate multiple synchronization flag signals FLAG (s) respectively. Please note here that between the paths of the sequence flag signal synchronization circuits SYNC2 ~ SYNC5 receiving the second clock signal CK (s), the sequence flag signals can be set (or not set) with appropriate transmission delay circuits DEA8 ~ DEA10. The triggered time points of the synchronization circuits SYNC2 to SYNC5 are substantially the same. Among them, in this embodiment, the length of the time delay provided by the transmission delay circuits DEA8 to DAE10 can be all the same, all different or partly the same, and can be set by the designer according to the circuit layout, process parameters and operating status. Special restrictions.

Continuing the above description, the parallel sequence signal conversion circuits 250 to 253 receive the first data signals DP0 to DP3, the synchronization flag signal FLAG (s), and the second clock signal CK (s), respectively. Each of the parallel sequence conversion circuits 250 to 253 sets the start time of the conversion operation according to the received synchronization flag signal FLAG (s), and transmits each first data in sequence according to the second clock signal CK (s). The bits of the signals DP0 ~ DP3 are used to generate the second data signals DS0 ~ DS3 respectively. The second data signals DS0 to DS3 are sequence signals.

The second data signals DS0 ~ DS3 are transmitted to the output stage flip-flops 225 ~ 228, respectively. The output stage flip-flops 225 to 228 respectively transmit the second data signals DS0 to DS3 according to the second clock signal CK (s) to generate output signals TXPN0 to TXPN3. It is worth mentioning that between the paths where the clock ends of the output stage flip-flops 225 ~ 228 receive the second clock signal CK (s), an appropriate transmission delay circuit (such as the transmission delay circuit DE11 ~) can be configured (or not configured). DE13), to adjust the triggering time points of the output stage flip-flops 225 to 228 are substantially the same.

In another aspect, the clock signal generator 230 may be constructed by one or more frequency dividers, where the clock signal generator 230 may provide multiple divisors to divide the second clock signal CK (s). It also generates a multi-channel clock CKx (p) with multiple first clock signals PMAD_CK0 ~ PMAD_CKN with the same frequency and different phases. Regarding the hardware architecture of the frequency divider, it can be implemented according to the frequency divider architecture well known to those having ordinary knowledge in the art, and there is no specific limitation.

It is worth mentioning that, in the embodiment of the present invention, the pre-stage circuit 210 does not simply transmit the synchronization flag signal FLAG (p) to the post-stage circuit 220 through a transmission wire, but applies the flip-flop groups 221 to 224 according to the reference time. The pulse signal CK (p) is transmitted to the subsequent circuit 220. In this way, the time delays of the flags DP_FLAG0 ~ DP_FLAG3 obtained by the post-stage circuit 220 can be well controlled to reduce the possible data offset.

Please refer to the waveform diagram of the clock signal shown in FIG. 3. The clock signal generator 230 receives a relatively high frequency and generates a multi-channel clock CKx (p) of a relatively low frequency by dividing the frequency. In this embodiment, the frequency of the second clock signal CK (s) may be twice the frequency of the multi-channel clock CKx (p). Of course, in other embodiments of the present invention, the frequency of the second clock signal CK (s) may be A times the frequency of the multi-channel clock CKx (p), and A is any real number greater than 1.

In addition, the second clock signal CK (s) can be generated through a phase-locked loop circuit. The phase-locked loop circuit can receive the source clock signal and perform a frequency multiplication operation on the source clock signal to generate a second clock signal CK (s). Here, the embodiments of the present invention can be implemented by applying a phase-locked loop circuit well known to those skilled in the art, and there is no particular limitation.

Please refer to FIG. 2 again. Incidentally, the above-mentioned transmission delay circuit in this embodiment can be implemented through one or more serially connected buffers or inverters, or any other semiconductor device that can provide time delay. There are no specific restrictions. In addition, the parallel flag signal synchronization circuit SYNC1 can be constructed using digital flip-flops, and the serial flag signal synchronization circuits SYNC2 ~ SYNC4 can be constructed using analog flip-flops.

According to the above description, it can be known that, in the embodiment of the present invention, the pre-stage circuit 210 can make the data shift generated by the static timing analysis method under the influence of temperature, voltage, and process drift not greater than 500 picoseconds. (Picosecond). It is worth mentioning that on the premise that the post-stage circuit 220 performs data transmission based on the second clock signal CK (s), the data offset that the post-stage circuit 220 may generate may not be greater than twice the UI (Unit Interval ), Where UI is equal to the period of the second clock signal CK (s).

Please refer to FIG. 4 below, which illustrates a schematic diagram of an implementation manner of a parallel sequence signal conversion circuit according to an embodiment of the present invention. The parallel signal conversion circuit 400 includes a plurality of registers 410, a selector 420, and a shift counter 430. The plurality of registers 410 respectively receive a plurality of bits of the first data signal DP0. An output terminal of the register 410 is coupled to the selector 420. The shift counter 430 receives a synchronization flag FLAG (s) and a second clock signal CK (s). The shift counter 430 starts a counting operation according to the synchronization flag FLAG (s), and performs a counting operation according to the second clock signal CK (s) to generate a counting result. The selector 420 sequentially selects data stored in one of the plurality of registers 410 for output according to the counting result of the shift counter 430, and generates a second data signal DS0.

Please refer to FIG. 5, which illustrates a schematic diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 500 includes a core circuit 501 and a multi-channel transmission device 510. The multi-channel transmission device 510 is coupled to the core circuit 501 for transmitting data signals generated in the core circuit 501. The multi-channel transmission device 510 includes a clock signal generator 513, front-stage circuits 511, 521, and post-stage circuits 512, 522. The pre-stage circuit 511 is coupled to the post-stage circuit 512, and the pre-stage circuit 521 is coupled to the post-stage circuit 522. The number of the pre-stage circuits and the post-stage circuits that can be provided in the integrated circuit 500 may be one or more groups, and there is no particular limitation.

The implementation details of the clock signal generator 513, the pre-stage circuits 511, 521, and the post-stage circuits 512, 522 have been described in detail in the foregoing embodiments, and will not be repeated here.

Please refer to FIG. 6, which is a flowchart of a multi-channel signal transmission method according to an embodiment of the present invention. Step S610 provides a pre-stage circuit to receive a plurality of first clock signals and a plurality of data signals, select one of the first clock signals as a reference clock signal, and transmit the data signal according to the reference clock signal and Generate multiple relay signals respectively; step S620 provides a clock signal generator to generate a first clock signal according to the second clock signal, wherein the frequency of the second clock signal is higher than the frequency of the first clock signal; Step S630 provides a post-stage circuit to transmit a relay signal according to the second clock signal to generate multiple output signals respectively; and step S640 provides a pre-stage circuit to receive a flag signal and synchronizes the flag according to the reference clock signal Signal to generate a first synchronization flag signal. The first-stage circuit combines the first synchronization flag signal into each relay signal and transmits it to the subsequent-stage circuit. In this embodiment, the previous-stage circuit is a digital circuit, and the subsequent-stage circuit is an analog circuit.

Regarding the implementation details of the above steps, the foregoing embodiments and implementation manners have been described in detail, and will not be repeated here.

To sum up, the present invention enables a multi-channel transmission device to perform data signal transmission based on the internal consistency of the post-stage circuit in the form of an analog circuit with a relatively high frequency second clock signal, which can effectively reduce the possibility of occurrence The extent of the data offset. In addition, in the case of a metastable state, the degree of data shift can also be effectively reduced.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200‧‧‧ multi-channel transmission device

110、210‧‧‧Previous circuit

120, 220‧‧‧ after-stage circuit

130, 230‧‧‧ clock signal generator

CKx (p) ‧‧‧Multi-channel clock

DTx (p) ‧‧‧Multi-channel data

PMAD_CK0 ~ PMAD_CKN‧‧‧First clock signal

DT0 ~ DTN‧‧‧Data signal

MSx (p) ‧‧‧Multi-channel relay signal

TXPNx (s) ‧‧‧Multi-channel output signal

MS0 ~ MSN‧‧‧Relay signal

CK (s) ‧‧‧Second clock signal

TXPN0 ~ TXPNN‧‧‧Output signal

LANE [0] ~ LANE [3] ‧‧‧Digital transmission channel

SYNC (p) ‧‧‧parallel flag synchronization circuit

SYNC2 ~ SYNC5‧‧‧Sequence flag signal synchronization

SEL (p) ‧‧‧Selector

CK (p) ‧‧‧reference clock signal

211 ~ 214, 221 ~ 224‧‧‧‧Inverter unit

DE1 ~ DE7, DEA8 ~ DEA11, DEA1‧‧‧ Transmission Delay Circuit

ALANE [0] ~ ALANE [3] ‧‧‧Analog transmission channel

251 ~ 254, 400‧‧‧ Parallel Sequence Signal Conversion Circuit

225 ~ 228‧‧‧Output stage flip-flop

TXFLAG (p) ‧‧‧flag signal

DP_FLAG0 ~ DP_FLAG3 ‧‧‧ flag

DS0 ~ DS3‧‧‧Second data signal

410‧‧‧Register

420‧‧‧ selector

430‧‧‧Shift Counter

FLAG (s), FLAG (p) ‧‧‧Synchronous flag signals

500‧‧‧Integrated Circuit

501‧‧‧core circuit

510‧‧‧Multi-channel transmission device

511,521‧‧‧Previous circuit

512, 522‧‧‧ post circuit

S610 ~ S640‧‧‧Multi-channel data transmission method steps

FIG. 1 is a schematic diagram of a multi-channel transmission device according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a multi-channel transmission device according to another embodiment of the present invention. FIG. 3 is a schematic waveform diagram of a clock signal. FIG. 4 is a schematic diagram of an implementation of a parallel sequence signal conversion circuit according to an embodiment of the present invention. FIG. 5 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. FIG. 6 is a flowchart of a multi-channel signal transmission method according to an embodiment of the present invention.

Claims (21)

A multi-channel transmission device includes: a pre-stage circuit, receiving a plurality of first clock signals and a plurality of data signals, selecting one of the first clock signals as a reference clock signal, and according to the reference The clock signal transmits the data signals and generates multiple relay signals respectively; a clock signal generator receives a second clock signal, and generates the first clock signals according to the second clock signal, wherein The frequency of the second clock signal is higher than the frequencies of the first clock signals; and a post-stage circuit coupled to the pre-stage circuit and the clock signal generator to transmit the second clock signal according to the second clock signal These relay signals are used to generate a plurality of output signals, wherein the pre-stage circuit includes a parallel flag signal synchronization circuit, receives a flag signal, and synchronizes the flag signal according to the reference clock signal to generate a first signal. A synchronization flag signal, in which the first-stage circuit combines the first synchronization flag signal into each of the relay signals and transmits it to the subsequent-stage circuit, wherein the previous-stage circuit is a digital circuit and the subsequent-stage circuit For the analog circuits. The multi-channel transmission device according to item 1 of the scope of patent application, wherein the pre-stage circuit further includes: a plurality of digital transmission channels, respectively receiving the data signals, and transmitting the data signals according to the reference clock signal to generate the data signals respectively. The relay signals, wherein each of the data signals and each of the relay signals are parallel signals having multiple bits. The multi-channel transmission device according to item 1 of the scope of patent application, wherein the post-stage circuit includes: a plurality of analog transmission channels, respectively receiving the relay signals, and transmitting the relay signals according to the second clock signal to The output signals are generated, wherein each of the output signals is a sequence signal generated according to the second clock signal. The multi-channel transmission device according to item 3 of the scope of patent application, wherein each of the analog transmission channels includes: a flip-flop group, receiving each of the relay signal and the first synchronization flag signal, according to the reference clock signal To generate a plurality of first data signals and a flag; a sequence flag signal synchronization circuit to synchronize the first synchronization flag signal according to the second clock signal to generate a second synchronization flag signal; a parallel sequence signal A conversion circuit based on the second synchronization flag signal and sequentially transmitting each of the first data signals to generate a second data signal according to the second clock signal, wherein the second data signal is a sequence signal; and An output stage flip-flop synchronizes the second data signal and generates a corresponding output signal according to the second clock signal. The multi-channel transmission device according to item 4 of the scope of patent application, wherein the trigger timings of the flag signal synchronization circuits corresponding to the analog transmission channels are the same. The multi-channel transmission device according to item 4 of the scope of the patent application, wherein each of the analog transmission channels further includes: a transmission delay circuit connected in series between the sequence flag signal synchronization circuit and the path for receiving the second clock signal, It is used to adjust the triggered time point of the sequence flag signal synchronization circuit. The multi-channel transmission device according to item 4 of the scope of patent application, wherein the parallel-sequence signal conversion circuit includes: a plurality of registers, each of which receives and temporarily stores the first data signals; a shift counter according to the first Two synchronous flag signals to start a counting action, and execute the counting action according to the second clock signal to generate a counting result; and a selector coupled to the registers, and sequentially according to the counting result One of the first data signals stored in the registers is selected for output, and the second data signal is generated. The multi-channel transmission device according to item 4 of the scope of patent application, wherein each of the analog transmission channels further includes a transmission delay circuit connected in series between the output stage flip-flops receiving the second clock signal. To adjust the triggering time of the output stage flip-flop. The multi-channel transmission device as described in item 4 of the scope of patent application, wherein the trigger points of the output stage flip-flops corresponding to the analog transmission channels are the same. The multi-channel transmission device according to item 1 of the patent application scope further includes: a phase-locked loop circuit to generate the second clock signal according to a source clock signal. An integrated circuit includes: a multi-channel transmission device including: at least one pre-stage circuit, receiving a plurality of first clock signals and a plurality of data signals, and selecting one of the first clock signals as a The reference clock signal is used to transmit the data signals and generate multiple relay signals respectively according to the reference clock signal; a clock signal generator receives a second clock signal and generates the second clock signal according to the second clock signal. First clock signals, wherein the frequency of the second clock signal is higher than the frequency of the first clock signals; and at least one post-stage circuit coupled to the at least one pre-stage circuit and the clock signal generator. Transmitting the relay signals according to the second clock signal to generate multiple output signals respectively, wherein the at least one pre-stage circuit includes: a parallel flag signal synchronization circuit, receiving a flag signal, and according to the The reference clock signal synchronizes the flag signal to generate a first synchronization flag signal, wherein the pre-stage circuit combines the first synchronization flag signal into each of the relay signals and transmits it to the at least one Circuit, wherein the at least one former circuit are digital circuits, the at least one subsequent stage circuit analog circuit. The integrated circuit according to item 11 of the scope of patent application, wherein the at least one pre-stage circuit further includes: a plurality of digital transmission channels, respectively receiving the data signals, and transmitting the data signals according to the reference clock signal to respectively The relay signals are generated, wherein each of the data signals and each of the relay signals are parallel signals having multiple bits. The integrated circuit according to item 11 of the scope of patent application, wherein the at least one post-stage circuit includes a plurality of analog transmission channels, respectively receiving the relay signals, and transmitting the relay signals according to the second clock signal. To generate the output signals, each of the output signals is a sequence signal generated according to the second clock signal. The integrated circuit according to item 13 of the scope of the patent application, wherein each of the analog transmission channels includes: a flip-flop group that receives each of the relay signal and the first synchronization flag signal, and uses the reference clock signal to Generating a plurality of first data signals and a flag; a sequence flag signal synchronization circuit that synchronizes the first synchronization flag signal according to the second clock signal to generate a second synchronization flag signal; a parallel sequence signal conversion A circuit based on the second synchronization flag signal and sequentially transmitting each of the first data signals according to the second clock signal to generate a second data signal, wherein the second data signal is a sequence signal; and The output stage flip-flop synchronizes the second data signal and generates a corresponding output signal according to the second clock signal. The integrated circuit according to item 14 of the scope of the patent application, wherein the trigger timings of the flag signal synchronization circuits corresponding to the analog transmission channels are the same. The integrated circuit according to item 14 of the scope of patent application, wherein each of the analog transmission channels further includes a transmission delay circuit connected in series between the sequence flag signal synchronization circuit and the path for receiving the second clock signal. To adjust the triggering time of the sequence flag signal synchronization circuit. The integrated circuit according to item 14 of the scope of patent application, wherein the parallel-sequence signal conversion circuit includes: a plurality of temporary registers respectively receiving and temporarily storing the first data signals; a shift counter according to the second Synchronize the flag signal to start a counting operation, and execute the counting operation according to the second clock signal to generate a counting result; and a selector, coupled to the registers, and selecting sequentially according to the counting result One of the first data signals stored by the registers is outputted, and the second data signal is generated. The integrated circuit according to item 14 of the scope of patent application, wherein each of the analog transmission channels further includes: a transmission delay circuit connected in series between the output stage flip-flops receiving the second clock signal for Adjust the triggering time of the output stage flip-flop. The integrated circuit according to item 14 of the scope of application for a patent, wherein the trigger points of the output stage flip-flops corresponding to the analog transmission channels are the same. The integrated circuit according to item 11 of the scope of patent application, wherein the multi-channel transmission device further includes: a phase-locked loop circuit to generate the second clock signal according to a source clock signal. A multi-channel signal transmission method includes: providing a pre-stage circuit to receive a plurality of first clock signals and a plurality of data signals, selecting one of the first clock signals as a reference clock signal, and Transmitting the data signals and generating a plurality of relay signals respectively according to the reference clock signal; providing a clock signal generator to generate the first clock signals according to a second clock signal, wherein the second clock The frequency of the pulse signal is higher than the frequencies of the first clock signals; providing a post-stage circuit to transmit the relay signals according to the second clock signal to generate a plurality of output signals respectively; and the pre-stage circuit Receiving a flag signal and synchronizing the flag signal according to the reference clock signal to generate a first synchronization flag signal, wherein the pre-stage circuit combines the first synchronization flag signal into each of the relay signals, And transmitting to the post-stage circuit, wherein the pre-stage circuit is a digital circuit, and the post-stage circuit is an analog circuit.