CN117559972A - Signal generating circuit - Google Patents

Abstract

The invention provides a signal generating circuit and a signal generating method. The signal generating circuit includes: a first synchronization circuit configured to receive the beacon signal and the clock signal and synchronize first signal edges of the beacon signal and the clock signal to generate a first synchronization signal; the frequency-dividing element is configured to receive the clock signal and perform frequency-dividing operation on the clock signal to generate a frequency-dividing signal, wherein the working period of the frequency-dividing signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency-divided signal and synchronize second signal edges of the first synchronization signal and the frequency-divided signal to generate a second synchronization signal; and the synthesis circuit is configured to receive the second synchronous signal and the frequency-dividing signal and perform AND operation on the second synchronous signal and the frequency-dividing signal to output the complete periodic signals.

Description

Signal generating circuit

Technical Field

The present invention relates to the field of signal generation circuits, and more particularly to a technique that can output a plurality of complete periodic signals for a predetermined period of time.

Background

In transmitting a test signal, it is often required to transmit a test signal having a plurality of complete cycles, for example, LFPS (Low Frequency Periodic Signaling) signal required for USB 3.0 or more, within a predetermined time. However, when the period of the test signal is changed, the existing circuit design often cannot meet the requirement, and the period is incomplete.

Disclosure of Invention

In view of the above, some embodiments of the present invention provide a signal generating circuit and a signal generating method to improve the prior art.

An embodiment of the present invention provides a signal generating circuit for outputting a plurality of complete cycle signals within a signal time period of a beacon signal. The signal generating circuit comprises a first synchronous circuit, a frequency dividing element, a second synchronous circuit and a synthesizing circuit. The first synchronization circuit is configured to receive the beacon signal and the clock signal and synchronize a first signal edge of the beacon signal and the clock signal to generate a first synchronization signal; the frequency dividing element is configured to receive the clock signal and perform a frequency dividing operation (frequency division operation) on the clock signal to generate a frequency divided signal, wherein a duty cycle of the frequency divided signal is 50%; the second synchronizing circuit is configured to receive the first synchronizing signal and the frequency-dividing signal and synchronize second signal edges of the first synchronizing signal and the frequency-dividing signal to generate a second synchronizing signal; the synthesis circuit is configured to receive the second synchronization signal and the frequency-divided signal, and perform a sum operation on the second synchronization signal and the frequency-divided signal to output the complete cycle signals.

An embodiment of the present invention provides a signal generating method for outputting a plurality of full-period signals within a signal time period of a beacon signal. The signal generating method comprises the following steps: synchronizing a beacon signal with a first signal edge of a clock signal via a first synchronization circuit to generate a first synchronization signal; performing frequency-dividing operation on the clock signal through the frequency-dividing element to generate a frequency-dividing signal, wherein the working period of the frequency-dividing signal is 50%; synchronizing the first synchronization signal with a second signal edge of the frequency-divided signal through a second synchronization circuit to generate a second synchronization signal; and performing an AND operation on the second synchronous signal and the frequency-divided signal by using the synthesis circuit to output the complete cycle signals.

In view of the foregoing, some embodiments of the present invention provide a signal generating circuit and a signal generating method, which can output a plurality of complete periodic signals in a predetermined period by using a synchronization circuit and a frequency divider circuit.

Drawings

Fig. 1 is a block diagram of a signal generating circuit according to an embodiment of the present invention.

Fig. 2-1 is a schematic diagram illustrating operation of a first synchronization circuit according to some embodiments of the invention.

Fig. 2-2 are schematic diagrams illustrating operation of a first synchronization circuit according to some embodiments of the invention.

Fig. 3-1 is a block diagram of a frequency removing device according to some embodiments of the invention.

Fig. 3-2 is a block diagram of a frequency removing device according to some embodiments of the invention.

Fig. 4-1 is a block diagram of a second synchronization circuit shown in accordance with some embodiments of the present invention.

Fig. 4-2 is a schematic diagram illustrating operation of a second synchronization circuit according to some embodiments of the invention.

Fig. 4-3 are block diagrams of a second synchronization circuit according to some embodiments of the invention.

Fig. 5-1 is a block diagram of a second synchronization circuit shown in accordance with some embodiments of the present invention.

Fig. 5-2 is a schematic diagram illustrating operation of a second synchronization circuit according to some embodiments of the invention.

Fig. 6 is a block diagram of a signal generation circuit according to some embodiments of the invention.

Fig. 7 is a schematic diagram illustrating operation of a signal generation circuit according to some embodiments of the invention.

Fig. 8 is a block diagram of a signal generation circuit according to some embodiments of the invention.

Fig. 9 is a schematic diagram illustrating operation of a signal generation circuit according to some embodiments of the invention.

FIG. 10 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 11 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 12 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 13 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 14 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 15 is a flow chart of a signal generating method according to an embodiment of the invention.

FIG. 16 is a flow chart of a signal generating method according to an embodiment of the invention.

Symbol description

100: signal generating circuit

101: first synchronous circuit

102: frequency-removing element

103: second synchronous circuit

104: synthesis circuit

201. 204, 701, 901: beacon signal

202. 205, 702, 902: clock signal

203. 502, 903, 206, 403, 703: first synchronization signal

2021. 2022, 2051, 2052, 4041, 4042, 4051, 4052, 5031, 5032, 7021, 7022, 7041, 7042, 9021, 9022, 9041, 9042: pulse

2031. 2061, 4061, 5041, 7031, 7051, 9031, 9051: start time

2032. 2062, 4062, 5042, 7032, 7052, 9032, 9052: end time

301. 602: first frequency-dividing element

302. 608: second frequency-dividing element

303. 305, 401, 501, 601, 603, 605: positive edge trigger D type flip-flop (trigger)

304. 604: inverse gate (NAND gate)

3031. 3051, 4011, 4071, 5011: signal input terminal

3032. 3052, 4012, 4072, 5012: clock input terminal

3033. 3043, 3053, 4013, 4073, 5013: an output terminal

3034. 3054, 4014, 4074, 5014: complementary output terminal

3041. 3042: input terminal

402. 607: reverse circuit

4021. 6071: reverser

404. 503, 704, 904: frequency-divided signal

405: reverse frequency-divided signal

406. 504, 705, 905: second synchronizing signal

407: negative edge trigger D-type flip-flop

606: gate

6021: frequency-dividing element for dividing 6

706. 906: full period signal

S1001 to S1004, S1101, S1201, S1301 to S1302, S1401, S1501, S1601 to S1602: step (a)

Detailed Description

The foregoing and other technical content, features and technical effects of the present invention will be apparent from the following detailed description of the embodiments with reference to the accompanying drawings. The thickness or dimensions of the elements in the drawings are exaggerated or omitted or schematically shown for the understanding and reading of those skilled in the art, and the dimensions of each element are not completely the actual dimensions and are not intended to limit the applicable conditions of the present invention, so that any modification of the structure, the change of the proportional relationship or the adjustment of the size is not technically significant, and all the modifications or the changes of the size should still fall within the scope of the technical contents disclosed in the present invention without affecting the technical effects and the achievement of the present invention. The same reference numbers will be used throughout the drawings to refer to the same or like elements.

Fig. 1 is a block diagram of a signal generating circuit according to an embodiment of the present invention. Referring to fig. 1, the signal generating circuit 100 is configured to output a plurality of full-period signals within a signal time period of a beacon signal. The signal generating circuit 100 includes a first synchronizing circuit 101, a frequency dividing element 102, a second synchronizing circuit 103, and a synthesizing circuit 104. The first synchronization circuit 101 receives a beacon signal and a clock signal, wherein the clock signal is a periodic pulse, and the beacon signal is a high logic level signal. The clock signal may be generated by a clock management unit (clock management unit, clock management unit, CMU) external to the signal generating circuit 100 or by an oscillator external to the signal generating circuit 100. In the periodic pulse, the portion from low potential to high potential is called a positive edge (positive edge) of the periodic pulse; the portion from high to low is called the negative edge (negative edge) of the periodic pulse. One signal edge (signal edge) of the periodic pulse refers to either the positive edge of the periodic pulse or the negative edge of the periodic pulse. The portion of a pulse from low to high is referred to as the positive edge of the pulse (positive edge), and the portion from high to low is referred to as the negative edge of the pulse (negative edge).

The following describes in detail the signal generation method according to some embodiments of the present invention and how the modules of the signal generation circuit 100 cooperate with each other.

FIG. 10 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 1 and 10, in step S1001, the first synchronization circuit 101 synchronizes a beacon signal with a signal edge (e.g., a positive edge) of a clock signal when receiving the beacon signal. Here, the first synchronization circuit 101 synchronizes the beacon signal with one signal edge (for example, a positive edge) of the clock signal, which means that the first synchronization circuit 101 generates the first synchronization signal corresponding to the beacon signal based on the beacon signal such that a start time of the first synchronization signal is aligned with one of the signal edges (positive edges) of the clock signal closest to the start time of the beacon signal, and an end time of the first synchronization signal is aligned with one of the signal edges (positive edges) of the clock signal closest to the end time of the beacon signal. Step S1001 is further described below in some embodiments of the present invention.

Fig. 2-1 is a schematic diagram illustrating operation of a first synchronization circuit according to some embodiments of the invention. FIG. 11 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 1, fig. 2-1 and fig. 11, in this embodiment, the first synchronization circuit 101 includes a positive-edge-triggered D-type flip-flop, and the step S1001 includes a step S1101. In step S1101, the positive-edge-triggered D-type flip-flop is configured such that the signal input of the positive-edge-triggered D-type flip-flop receives the clock signal 201 and the clock input of the positive-edge-triggered D-type flip-flop receives the clock signal 202. Then based on the positive edge trigger characteristics of the positive edge triggered D-type flip-flop, the positive edge triggered D-type flip-flop in the first synchronization circuit 101 generates the first synchronization signal 203 based on the beacon signal 201, and the start time 2031 of the first synchronization signal 203 is aligned with one of the positive edges of the clock signal 202 (the positive edge of the pulse 2021) that is closest to the start time of the beacon signal 201, and the end time 2032 of the first synchronization signal 203 is aligned with one of the positive edges of the clock signal 202 (the positive edge of the pulse 2022) that is closest to the end time of the beacon signal 201. In this embodiment, the beacon signal 201 is said to be synchronous with the positive edge of the clock signal 202.

Fig. 2-2 are schematic diagrams illustrating operation of a first synchronization circuit according to some embodiments of the invention. FIG. 12 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 1, 2-2 and 12, in this embodiment, the first synchronization circuit 101 includes a negative edge triggered D-type flip-flop. The aforementioned step S1001 includes step S1201. In step S1201, the negative edge triggered D flip-flop is configured such that the signal input of the negative edge triggered D flip-flop receives the clock signal 204 and the clock input of the negative edge triggered D flip-flop receives the clock signal 205. The first synchronization circuit 101 generates the first synchronization signal 206 based on the beacon signal 204 based on the negative edge trigger characteristic of the negative edge trigger D-type flip-flop and the start time 2061 of the first synchronization signal 206 is aligned with one of the negative edges of the clock signal 205 (the negative edge of the pulse 2051) that is closest to the start time of the beacon signal 204 and the end time 2062 of the first synchronization signal 206 is aligned with one of the negative edges of the clock signal 205 (the negative edge of the pulse 2052) that is closest to the end time of the beacon signal 204. In this embodiment, the beacon signal 204 is said to be synchronous with the negative edge of the clock signal 205.

Please refer to fig. 1 and 10. In step S1002, the frequency dividing element 102 receives the clock signal and performs a frequency dividing operation (frequency division operation) on the clock signal to generate a frequency divided signal, where the duty cycle of the frequency divided signal is 50%. Step S1002 is further described below in some embodiments of the present invention.

Fig. 3-1 and 3-2 are block diagrams of frequency removing devices according to some embodiments of the invention. FIG. 13 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 3-1, fig. 3-2 and fig. 13, the frequency dividing element 102 includes a first frequency dividing element 301 and a second frequency dividing element 302. The first frequency divider 301 is a frequency divider. The first frequency-dividing element 301 is configured to receive the clock signal and reduce the frequency of the clock signal to generate a first frequency-divided signal, wherein the frequency of the first frequency-divided signal is twice the predetermined frequency of the frequency-divided signal. The second frequency divider 302 is a divide-by-two-2-frequency divider. The second frequency dividing element 302 is configured to receive the first frequency divided signal and perform a divide-by-two-2-frequency division operation operation on the first frequency divided signal to generate a frequency divided signal. The step S1002 includes the step S1601 and the step 1602, in which in the step S1601, the first frequency dividing element 301 receives the clock signal and reduces the frequency of the clock signal to generate a first frequency dividing signal, where the frequency of the first frequency dividing signal is twice the predetermined frequency as described above. In step S1602, the second frequency-dividing element 302 receives the first frequency-divided signal and performs a divide-by-two-2-frequency division operation (divide-by-two) on the first frequency-divided signal to generate a frequency-divided signal.

Please refer to fig. 3-1 again. In the embodiment shown in fig. 3-1, the second frequency divider 302 includes a positive-edge-triggered D-type flip-flop 303 and a NAND gate 304. The clock input 3032 of the positive edge triggered D-flip-flop 303 is configured to receive a first divided signal. The input 3041 and the input 3042 of the NAND gate 304 are configured to simultaneously receive the output of the output 3033 of the positive edge triggered D flip-flop 303. The signal input 3031 of the positive edge triggered D-type flip-flop 303 is configured to receive the output of the output 3043 of the nand gate 304. The output signal of the complementary output 3034 of the positive edge triggered D-type flip-flop 303 is not used in this embodiment. The output signal at the output terminal 3043 of the NAND gate 304 is used as a frequency-divided signal. It should be noted that in the embodiment shown in fig. 3-1, the configuration of the second frequency divider 302 results in a duty cycle of 50% of the output signal at the output terminal 3043 of the nand gate 304, and thus a duty cycle of 50% of the frequency divider.

Please refer to fig. 3-2 again. In the embodiment shown in fig. 3-2, the second frequency divider 302 includes a positive-edge-triggered D-type flip-flop 305. The clock input 3052 of the positive edge triggered D flip-flop 305 is configured to receive the first divided signal. The signal input 3051 of the positive-edge-triggered D-type flip-flop 305 is configured to receive the output signal of the complementary output 3054 of the positive-edge-triggered D-type flip-flop 305. The output signal of the positive edge triggered D-type flip-flop 305 at the output 3053 is not used in this embodiment. The positive edge triggers the output signal of the complementary output 3054 of the D-type flip-flop 305 as a divide signal. It should be noted that in the embodiment shown in fig. 3-1, the configuration of the second frequency divider 302 results in a duty cycle of 50% of the output signal of the complementary output 3054 of the positive edge triggered D-type flip-flop 305, and thus the duty cycle of the frequency divided signal is also 50%.

Please refer to fig. 1 and 10. The second synchronization circuit 103 is configured to receive the first synchronization signal and the frequency-divided signal. In step S1003, the first synchronization signal and the second signal edge of the frequency-divided signal are synchronized by the second synchronization circuit 103 to generate a second synchronization signal. Step S1003 is further described below in some embodiments of the present invention.

Fig. 4-1 is a block diagram of a second synchronization circuit shown in accordance with some embodiments of the present invention. Fig. 4-2 is a schematic diagram illustrating operation of a second synchronization circuit according to some embodiments of the invention. FIG. 14 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 4-1, fig. 4-2 and fig. 14, in this embodiment, the second signal edge of the frequency-divided signal is the negative edge of the frequency-divided signal. That is, the second synchronization circuit 103 synchronizes the first synchronization signal with the negative edge of the divided signal.

As shown in fig. 4-1 and 4-2, the second synchronization circuit 103 includes a positive-edge-triggered D-type flip-flop 401 and an inverting circuit 402, wherein the inverting circuit 402 is formed by an inverter 4021. The step S1003 includes steps S1301 and S1302. In step S1301, the frequency-divided signal 404 is received and inverted by the inverter 4021 to generate an inverted frequency-divided signal 405. In step S1302, the signal input 4011 of the positive-edge-triggered D-type flip-flop 401 receives the first synchronization signal 403, and the clock input 4012 of the positive-edge-triggered D-type flip-flop 401 receives the inverse frequency-divided signal 405. The first synchronization signal 403 is synchronized with the positive edge of the inverse frequency divider signal 405 based on the positive edge trigger characteristic of the positive edge trigger D-type flip-flop, and the output 4013 of the positive edge trigger D-type flip-flop 401 generates the second synchronization signal 406. The complementary output 4014 of the positive edge triggered D flip-flop 401 is not used herein. That is, the start time 4061 of the second synchronization signal 406 is aligned with the one of the positive edges of the inverse divided signal 405 closest to the start time of the first synchronization signal 403 (the positive edge of the pulse 4051), and the end time 4062 of the second synchronization signal 406 is aligned with the one of the positive edges of the inverse divided signal 405 closest to the end time of the first synchronization signal 403 (the positive edge of the pulse 4052).

Since the inverse divided signal 405 is an inverse of the divided signal 404, the first synchronization signal 403 is synchronous with the negative edge of the divided signal 404. That is, as shown in fig. 4-2, the start time 4061 of the second synchronization signal 406 is aligned with one of the negative edges of the divided signal 404 (the negative edge of the pulse 4041) closest to the start time of the first synchronization signal 403, and the end time 4062 of the second synchronization signal 406 is aligned with one of the negative edges of the divided signal 404 closest to the end of the first synchronization signal 403 (the negative edge of the pulse 4042).

Fig. 4-3 are block diagrams of a second synchronization circuit according to some embodiments of the invention. FIG. 15 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 4-2, fig. 4-3 and fig. 15, in this embodiment, the second signal edge of the frequency-divided signal is the negative edge of the frequency-divided signal. That is, the second synchronization circuit 103 synchronizes the first synchronization signal with the negative edge of the divided signal.

As shown in fig. 4-3, the second synchronization circuit 103 includes a negative edge triggered D-type flip-flop 407. The aforementioned step S1003 includes a step S1401. In step S1401, the signal input terminal 4071 of the negative edge-triggered D-type flip-flop 407 receives the first synchronization signal 403, and the clock input terminal 4072 of the negative edge-triggered D-type flip-flop 407 is configured to receive the frequency-divided signal 404. The first synchronizing signal 403 is synchronized with the negative edge of the frequency-divided signal 404 based on the negative edge triggering characteristic of the negative edge-triggered D-type flip-flop 407, and the output 4073 of the negative edge-triggered D-type flip-flop 407 generates the second synchronizing signal 406. The complementary output 4074 of the negative edge triggered D-type flip-flop 407 is not used in this embodiment.

Fig. 5-1 is a block diagram of a second synchronization circuit shown in accordance with some embodiments of the present invention. Fig. 5-2 is a schematic diagram illustrating operation of a second synchronization circuit according to some embodiments of the invention. FIG. 16 is a flow chart of a signal generating method according to an embodiment of the invention. Referring to fig. 5-1, fig. 5-2 and fig. 16, in this embodiment, the second signal edge of the frequency-divided signal is the positive edge of the frequency-divided signal. That is, the second synchronization circuit 103 synchronizes the first synchronization signal with the positive edge of the divided signal.

As shown in fig. 5-1, the second synchronization circuit 103 includes a positive-edge-triggered D-type flip-flop 501. The step S1003 includes a step S1501. In step S1501, the signal input 5011 of the positive-edge-triggered D-type flip-flop 501 receives the first synchronization signal 502, and the clock input 5012 of the positive-edge-triggered D-type flip-flop 501 receives the frequency-divided signal 503. The first synchronization signal 502 is synchronized with the positive edge of the divided signal 503 based on the positive edge trigger characteristic of the positive edge trigger D-type flip-flop 501, and the output 5013 of the positive edge trigger D-type flip-flop 501 generates the second synchronization signal 504. That is, the start time 5041 of the second synchronization signal 504 is aligned with one of the positive edges of the divided signal 503 (the positive edge of the pulse 5031) closest to the start time of the first synchronization signal 502, and the end time 5042 of the second synchronization signal 504 is aligned with one of the positive edges of the divided signal 503 (the positive edge of the pulse 5032) closest to the end time of the first synchronization signal 502. The complementary output 5014 of the positive edge triggered D-type flip-flop 501 is not used in this embodiment.

Please refer to fig. 1 and 10. In step S1004, the synthesizing circuit 104 receives the second synchronization signal and the frequency-divided signal, and performs a sum operation on the second synchronization signal and the frequency-divided signal to output a complete cycle signal. In some embodiments of the present invention, the synthesizing circuit 104 includes an AND gate (AND gate) that AND-sums the second synchronization signal and the frequency-divided signal to output the full period signal. It should be noted that the AND operation of the second synchronization signal and the frequency-divided signal by the AND gate can avoid the problem of time offset (timing skew) of the output complete period signal.

Fig. 6 is a block diagram of a signal generation circuit according to some embodiments of the invention. Fig. 7 is a schematic diagram illustrating operation of a signal generation circuit according to some embodiments of the invention. Please refer to fig. 1, fig. 6, fig. 7 and fig. 10. In the present embodiment, the signal generating circuit shown in fig. 6 is applied to generate LFPS (Low Frequency Periodic Signaling) signals required for USB 3.0 or more. The beacon signal 701 has a signal time length of 100ns, and the clock signal 702 is a periodic pulse with a frequency of 250 mhz and a period of 4ns. The circuit specification requirement is to output two full-period signals, each of which has a period of 48ns, within the signal time length of the beacon signal 701. Since the period of the frequency-divided signal is the same as the period of the full-period signal, the divisor of the frequency-divided element 102 is selected to be 12. With such a configuration, the period of the divided signal would be 48ns, and the product of the period of the divided signal and the number of full period signals would be 48×2=96, which is less than the signal time length of 100ns of the beacon signal 701. Thus, the first frequency divider 602 of the frequency divider 102 is configured to include a divide-by-6 frequency divider 6021, and the second frequency divider 608 of the frequency divider 102 includes a divide-by-two (frequency divider) consisting of a positive-edge-triggered D flip-flop 603 and a NAND gate 604.

As shown in fig. 6, in the present embodiment, the first synchronization circuit 101 includes a positive edge triggered D-type flip-flop 601. The second synchronization circuit 103 includes a positive-edge-triggered D-type flip-flop 605 and an inverting circuit 607, wherein the inverting circuit 607 is formed by an inverter 6071. The combining circuit 104 includes an AND gate 606.

In step S1001, the positive edge triggered D-type flip-flop 601 generates the first synchronization signal 703 based on the beacon signal 701 such that the start time 7031 of the first synchronization signal 703 is aligned with one of the positive edges of the clock signal 702 (the positive edge of the pulse 7021) closest to the start time of the beacon signal 701, and the end time 7032 of the first synchronization signal 703 is aligned with one of the positive edges of the clock signal 702 (the positive edge of the pulse 7022) closest to the end time of the beacon signal 701.

In step S1002, the frequency divider 102 receives the clock signal 702 and performs a frequency dividing operation (frequency division operation) on the clock signal 702 to generate the frequency-divided signal 704, wherein the duty cycle of the frequency-divided signal 704 is 50%.

In step S1003, the frequency-divided signal 704 is received and inverted by the inverter 6071 to generate an inverted frequency-divided signal. The signal input terminal of the positive-edge-triggered D-type flip-flop 605 receives the first synchronization signal 703, and the clock input terminal of the positive-edge-triggered D-type flip-flop 605 receives the inverse frequency-dividing signal. The first synchronization signal 703 is synchronized with the positive edge of the inverse frequency-divided signal based on the positive edge trigger characteristic of the positive edge trigger D-type flip-flop 605, and the output terminal of the positive edge trigger D-type flip-flop 605 generates the second synchronization signal 705. Since the inverse divided signal is an inverse of the divided signal 704, the first synchronization signal 703 is synchronized with the negative edge of the divided signal 704. That is, as shown in fig. 7, the start time 7051 of the second synchronization signal 705 is aligned with one of the negative edges of the divided signal 704 (the negative edge of the pulse 7041) closest to the start time 7031 of the first synchronization signal 703, and the end time 7052 of the second synchronization signal 705 is aligned with one of the negative edges of the divided signal 704 (the negative edge of the pulse 7042) closest to the end time 7032 of the first synchronization signal 703.

In step S1004, the sum gate 606 of the synthesis circuit 104 receives the second synchronization signal 705 and the frequency-divided signal 704. The AND gate 606 in the combining circuit 104 sums the second synchronization signal 705 and the frequency-divided signal 704 to output a full period signal 706.

Fig. 8 is a block diagram of a signal generation circuit according to some embodiments of the invention. Fig. 9 is a schematic diagram illustrating operation of a signal generation circuit according to some embodiments of the invention. Referring to fig. 1, 8, 9 and 10, in the present embodiment, the signal time length of the beacon signal 901 is 100ns, and the clock signal 902 is a periodic pulse with a frequency of 250 mhz and a period of 4ns. The circuit specification requirement is to output two full-period signals each having a period of 48ns for the signal time length of the beacon signal 901. Since the period of the frequency-divided signal is the same as the period of the full-period signal, the divisor of the frequency-divided element 102 is selected to be 12. With such a configuration, the period of the divided signal would be 48ns, and the product of the period of the divided signal and the number of full period signals would be 48×2=96, which is less than the signal time length of 100ns of the beacon signal 701. Thus, the first frequency divider 602 of the frequency divider 102 is configured to include a divide-by-6 frequency divider 6021, and the second frequency divider 608 of the frequency divider 102 includes a divide-by-two (frequency divider) consisting of a positive-edge-triggered D flip-flop 603 and a NAND gate 604.

As shown in fig. 8, the first synchronization circuit 101 includes a positive-edge-triggered D-type flip-flop 601. The second synchronization circuit 103 includes a positive-edge-triggered D-type flip-flop 605. The combining circuit 104 includes an AND gate 606.

In step S1001, the positive edge triggered D-type flip-flop 601 generates the first synchronization signal 903 based on the beacon signal 901 such that the start time 9031 of the first synchronization signal 903 is aligned with one of the positive edges of the clock signal 902 (the positive edge of the pulse 9021) that is closest to the start time of the beacon signal 901, and the end time 9032 of the first synchronization signal 903 is aligned with one of the positive edges of the clock signal 902 (the positive edge of the pulse 9022) that is closest to the end time of the beacon signal 901.

In step S1002, the frequency dividing element 102 receives the clock signal 902 and performs a frequency dividing operation (frequency division operation) on the clock signal 902 to generate a frequency-divided signal 904, wherein the duty cycle of the frequency-divided signal 904 is 50%.

In step S1003, the signal input terminal of the positive-edge-triggered D-type flip-flop 605 receives the first synchronization signal 903, and the clock input terminal of the positive-edge-triggered D-type flip-flop 605 receives the frequency-divided signal 904. The first synchronization signal 903 is synchronized with the positive edge of the frequency-divided signal 904 based on the positive edge trigger characteristic of the positive edge trigger D-type flip-flop 605, and the output terminal of the positive edge trigger D-type flip-flop 605 generates the second synchronization signal 905. That is, as shown in fig. 9, the start time 9051 of the second synchronization signal 905 is aligned with one of the positive edges of the divided signal 904 (the positive edge of the pulse 9041) closest to the start time 9031 of the first synchronization signal 903, and the end time 9052 of the second synchronization signal 905 is aligned with one of the positive edges of the divided signal 904 (the positive edge of the pulse 9042) closest to the end time 9032 of the first synchronization signal 903.

In step S1004, the sum gate 606 of the synthesis circuit 104 receives the second synchronization signal 905 and the frequency-divided signal 904. The AND gate 606 in the circuit 104 is synthesized and sums the second synchronization signal 905 and the frequency-divided signal 904 to output a full period signal 906.

In view of the foregoing, some embodiments of the present invention provide a signal generating circuit and a signal generating method, which can output the complete periodic signals in a predetermined period by using a synchronization circuit and a frequency divider circuit.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that the invention is not limited thereto, and that modifications and variations may be made by those skilled in the art without departing from the spirit of the invention.

Claims (10)

1. A signal generating circuit for outputting a plurality of complete periodic signals within a signal time period of a beacon signal, the signal generating circuit comprising:

a first synchronization circuit configured to receive the beacon signal and a clock signal and synchronize a first signal edge of the beacon signal and the clock signal to generate a first synchronization signal;

a frequency-dividing element configured to receive the clock signal and perform a frequency-dividing operation on the clock signal to generate a frequency-divided signal, wherein a duty cycle of the frequency-divided signal is 50%;

a second synchronization circuit configured to receive the first synchronization signal and the frequency-divided signal and synchronize a second signal edge of the first synchronization signal and the frequency-divided signal to generate a second synchronization signal; and

and a synthesis circuit configured to receive the second synchronization signal and the frequency-divided signal, and perform a sum operation on the second synchronization signal and the frequency-divided signal to output the complete periodic signal.

2. The signal generating circuit according to claim 1, wherein a divisor of the frequency dividing element is configured to make a product of a period of the frequency dividing signal and a number of the plurality of full period signals less than or equal to the signal time length.

3. The signal generating circuit according to claim 1, wherein the first signal edge of the clock signal is a positive edge of the clock signal, the first synchronization circuit comprises a positive edge-triggered D-type flip-flop, a signal input of the positive edge-triggered D-type flip-flop is configured to receive the beacon signal, and a clock input of the positive edge-triggered D-type flip-flop is configured to receive the clock signal, such that the positive edge-triggered D-type flip-flop synchronizes the beacon signal with the positive edge of the clock signal to generate the first synchronization signal.

4. The signal generating circuit according to claim 1, wherein the first signal edge of the clock signal is a negative edge of the clock signal, the first synchronization circuit comprises a negative edge-triggered D-type flip-flop, wherein a signal input of the negative edge-triggered D-type flip-flop is configured to receive the beacon signal, and a clock input of the negative edge-triggered D-type flip-flop is configured to receive the clock signal, such that the negative edge-triggered D-type flip-flop synchronizes the beacon signal with the negative edge of the clock signal to generate the first synchronization signal.

5. The signal generating circuit according to claim 1, wherein the second signal edge of the frequency-divided signal is a negative edge of the frequency-divided signal, the second synchronization circuit comprises:

a positive edge triggered D-type flip-flop; and

an inverting circuit;

the inverting circuit is configured to receive and invert the frequency-divided signal to generate an inverted frequency-divided signal, a signal input end of the positive edge trigger D-type flip-flop is configured to receive the first synchronization signal, and a clock input end of the positive edge trigger D-type flip-flop is configured to receive the inverted frequency-divided signal, so that the positive edge trigger D-type flip-flop synchronizes the first synchronization signal with the negative edge of the frequency-divided signal to generate the second synchronization signal.

6. The signal generating circuit according to claim 1, wherein the second signal edge of the frequency-divided signal is a negative edge of the frequency-divided signal, the second synchronization circuit comprises a negative edge-triggered D-type flip-flop, wherein a signal input terminal of the negative edge-triggered D-type flip-flop is configured to receive the first synchronization signal, and a clock input terminal of the negative edge-triggered D-type flip-flop is configured to receive the frequency-divided signal, so that the negative edge-triggered D-type flip-flop synchronizes the first synchronization signal with the negative edge of the frequency-divided signal to generate the second synchronization signal.

7. The signal generating circuit according to claim 1, wherein the second signal edge of the frequency-divided signal is a positive edge of the frequency-divided signal, the second synchronization circuit comprises a positive edge-triggered D-type flip-flop, wherein a signal input terminal of the positive edge-triggered D-type flip-flop is configured to receive the first synchronization signal, and a clock input terminal of the positive edge-triggered D-type flip-flop is configured to receive the frequency-divided signal, so that the positive edge-triggered D-type flip-flop synchronizes the first synchronization signal with the positive edge of the frequency-divided signal to generate the second synchronization signal.

8. The signal generating circuit according to claim 1, wherein the frequency dividing element comprises a first frequency dividing element and a second frequency dividing element, wherein the first frequency dividing element is a frequency divider configured to receive the clock signal and reduce a frequency of the clock signal to generate a first frequency dividing signal, wherein a frequency of the first frequency dividing signal is twice a predetermined frequency; the second frequency-dividing element is a frequency-dividing device and is configured to receive the first frequency-dividing signal and perform a frequency-dividing operation on the first frequency-dividing signal to generate the frequency-dividing signal.

9. The signal generating circuit according to claim 8, wherein the second frequency dividing element comprises a positive edge triggered D-type flip-flop and a nand gate, wherein a clock input of the positive edge triggered D-type flip-flop is configured to receive the first frequency dividing signal, two inputs of the nand gate are configured to simultaneously receive an output of the positive edge triggered D-type flip-flop, a signal input of the positive edge triggered D-type flip-flop is configured to receive an output of the nand gate, and the output of the nand gate is used as the frequency dividing signal.

10. The signal generating circuit according to claim 1, wherein the synthesizing circuit comprises a sum gate that sums the second synchronization signal and the divided signal to output the plurality of full-period signals.