JP2014062972A - Data reception circuit, data reception method and driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is difficult to make the frequency of a clock signal to be generated on the basis of an input signal follow up a change in the frequency of the input signal in a conventional technology.SOLUTION: A data reception circuit includes: a clock restoration part 13 for generating an internal clock signal iCLK from an input signal Sin; and a clock generation part 14 for outputting a restored clock signal having a frequency corresponding to the frequency of the internal clock signal iCLK. When the number of pulses of the internal clock signal iCLK is not coincident with the number of pulses of the input signal Sin, a reset signal RES is put in an enable state, and according as the reset signal RES is put in the enable state, the input signal Sin is output as the internal clock signal iCLK, and the frequency of a multi-phase clock signal SCLK is updated on the basis of the input signal Sin.

Description

  The present invention relates to a data receiving circuit, a data receiving method, and a data driver circuit. For example, the present invention relates to a data receiving circuit, a data receiving method, and a data driver circuit that receive an embedded clock type input signal.

  In a display device such as a liquid crystal display device, one display panel is driven using a plurality of drive circuits. In order to correctly display one image on the display panel, it is necessary to operate the plurality of drive circuits at the same timing. Therefore, in the display device, a plurality of drive circuits are operated based on the clock signal generated by the timing controller. In recent years, since the number of pixels of the display device has increased, data is transmitted to the drive circuit by an embedded clock method (self-synchronization method). The plurality of drive circuits receive embedded clock data, generate a recovered clock from the data, and operate based on the recovered clock.

  Patent Documents 1 to 3 disclose techniques using the data of the embedded clock method. In Patent Document 1, a technique for reducing jitter generated when a PLL (Phase Locked Loop) circuit is used by using a DLL (Delay Locked Loop) circuit when generating a recovered clock from an input signal of an embedded clock system. Is disclosed. Patent Document 2 discloses a clock extraction circuit having a wide capture range and excellent responsiveness when extracting a clock in a file device using an optical disk, a magnetic disk, or the like. In Patent Document 3, a transmission unit that is built in a timing controller and transmits transmission data in which an insertion clock is inserted between data and a clock enable signal that indicates the insertion clock, and a plurality of data connected to the timing controller are disclosed. A data interface device for a flat panel display device is disclosed, which is incorporated in each integrated circuit and includes a receiving unit that separates and detects an insertion clock and data from transmission data in response to a clock enable signal.

Special table 2011-514560 gazette JP-A-9-284269 JP 2009-163239 A

  In recent years, high-speed driving techniques such as double-speed driving that reduces the image update interval to ½ and quadruple-speed driving that reduces to ¼ have been used in order to realize high image quality of moving image characteristics and 3D display. In this high-speed driving technique, it is necessary to give data to the driving circuit at twice or four times the conventional speed. Therefore, when the drive circuit is operated at double speed or quadruple speed, it is necessary to set the frequency of the input signal to the drive circuit to an integral multiple such as double or quadruple.

  However, in the conventional technique, when the frequency of the input signal is switched so as to be an integral multiple, the edge of the input signal is missed. As a result, the frequency of the recovered clock signal cannot follow the switching of the frequency of the input signal due to the missing edge of the input signal. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a data receiving circuit, a data receiving method, and a data driver circuit include a clock recovery unit that generates an internal clock signal from an input signal, and a recovered clock signal having a frequency corresponding to the frequency of the internal clock signal. An output clock generator, and when the number of pulses of the internal clock signal and the number of pulses of the input signal do not match, the reset signal is enabled, and the reset signal is enabled. An input signal is output as an internal clock signal, and the frequency of the multiphase clock signal is updated based on the input signal.

  According to the embodiment, the data receiving circuit, the data receiving method, and the data driver circuit can accurately switch the frequency of the recovered clock signal corresponding to the switching of the frequency of the input signal.

1 is a block diagram of a display device according to a first exemplary embodiment. 1 is a block diagram of a driving device including a data receiving circuit according to a first embodiment; 1 is a block diagram of a clock restoration circuit according to a first exemplary embodiment; FIG. 2 is a circuit diagram of a clock restoration unit according to the first embodiment. FIG. 3 is a circuit diagram of a waveform shaping unit according to the first exemplary embodiment. FIG. 3 is a block diagram of a pulse number comparison unit according to the first exemplary embodiment. FIG. 3 is a circuit diagram of a lock determination unit according to the first exemplary embodiment. 3 is a timing chart showing an operation of the data receiving circuit according to the first exemplary embodiment; 3 is a timing chart illustrating a detailed operation in a clock training period of the data receiving circuit according to the first exemplary embodiment;

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. In the following description, an example will be described in which the data receiving circuit according to the first embodiment is applied to the drive circuit that constitutes the display device. However, the data receiving circuit according to the first embodiment can also be applied to other devices that receive embedded clock (self-synchronous) input data. First, FIG. 1 shows a block diagram of the display device 1 according to the first embodiment.

  As shown in FIG. 1, the display device 1 according to the first embodiment includes a display panel 2, timing controller 3, data driver modules 4a to 4c, and scan driver modules 6a and 6b.

  In the display panel 2, a large number of pixels in which the TFT transistor Tr and the pixel electrode 8 are combined are arranged in a lattice pattern. Further, the scan line SCAN is connected to the gate of the TFT transistor Tr, and the signal line SIG is connected to the source of the TFT transistor Tr.

  The data driver modules 4a to 4c have data driver circuits 5a to 5c, respectively. Each of the data driver circuits 5a to 5c is a semiconductor device in which a circuit is formed on one chip. The data driver circuits 5a to 5c include data receiving circuits 10a to 10c. The data receiving circuits 10a to 10c are the data receiving circuit 10 according to the first embodiment described later. The data driver circuits 5a to 5c drive the signal line SIG based on the data received by the data receiving circuits 10a to 10c.

  The scan driver modules 6a and 6b have scan driver circuits 7a and 7b, respectively. The scan driver circuits 7a and 7b are semiconductor devices each having a circuit formed on one chip. The scan driver circuits 7 a and 7 b drive the scan line SCAN based on the scan control signal output from the timing controller 3.

  The timing controller 3 outputs image data constituting an image to the data driver circuits 5a to 5c as embedded clock transmission data (for example, an input signal). Further, the timing controller 3 outputs, as transmission data, data specifying the scan line SCAN for rewriting pixel information to the scan driver circuits 7a and 7b. That is, one timing controller 3 is provided for a plurality of drive circuits (data driver circuit and scan driver circuit). Here, the input signal is switched by the timing controller 3 so that the frequency becomes an integral multiple of the frequency. The switching of the frequency of the input signal is performed according to the switching of the driving speed of the display panel.

  As described above, the data driver circuits 5a to 5c drive the signal line SIG based on the transmission data of the embedded clock method. At this time, the data driver circuits 5a to 5c generate a recovered clock signal from the transmission data and operate based on the recovered clock signal. Thereby, the data driver circuits 5 a to 5 c can drive the signal line SIG at the same timing specified by the timing controller 3. Since the data driver circuits 5a to 5c according to the first embodiment have one of the characteristics of the data receiving circuits 10a to 10c, the data receiving circuits 10a to 10c will be described in detail below. Since the data receiving circuits 10a to 10c have the same configuration, they are referred to as the data receiving circuit 10 in the following description.

  FIG. 2 is a block diagram of a driving device (for example, a data driver circuit) including the data receiving circuit 10 according to the first embodiment. As shown in FIG. 2, the data driver circuit includes a data receiving circuit 10 and a driver circuit 20.

  The data receiving circuit 10 generates restored data, a control signal (hereinafter referred to as a restored control signal) and a restored clock signal based on transmission data (hereinafter referred to as an input signal Sin), and the generated signal is supplied to the driver circuit 20. give. The driver circuit 20 receives the restored data based on the restored clock signal and drives the pixels of the display panel. More specifically, the driver circuit 20 includes a register, a data latch, a digital analog converter (DAC), and an amplifier. The register holds the restored data in order based on the restored clock signal. The data latch updates the data held by the restoration data held in the register at each timing designated by the restoration control signal. The digital-analog conversion circuit converts the data held in the data latch from a digital value to an analog value and supplies the converted value to the amplifier. The amplifier drives the signal line SIG based on the analog value output by the digital-analog conversion circuit.

  As shown in FIG. 2, the data receiving circuit 10 includes a serial / parallel conversion circuit 11, a clock restoration circuit 12, and a lock determination circuit 15. The serial-parallel conversion circuit 11 converts the input signal Sin from parallel data to serial data using the multiphase clock signal SCLK as a sampling clock, and a data signal (for example, restoration data) and a control signal (for example, restoration control) for the subsequent circuit. Signal). Here, it is assumed that the restoration control signal includes a data enable signal DE described later. The period in which the data enable signal DE is in the enabled state is a period in which the timing controller 3 instructs the clock training period, and the period in which the data enable signal DE is in the disabled state is a period in which the timing controller 3 instructs the data period. In the clock training period, the timing controller 3 outputs a clock signal having a frequency corresponding to the data transmission cycle as the input signal Sin. In the data period, the timing controller 3 outputs embedded clock data as the input signal Sin. In the example shown in FIG. 2, the restoration data is N (N is an integer) bit parallel data, and the restoration control signal is M (M is an integer) bit parallel data. The restoration data and the restoration control signal may have the same number of bits.

  The clock recovery circuit 12 generates a multiphase clock SCLK and a recovered clock signal based on the input signal Sin. The clock restoration circuit 12 updates the frequencies of the sampling clock SCLK and the restoration clock signal when the reset signal RES generated by the lock determination circuit 15 is in an enabled state. The clock recovery circuit 12 includes a clock recovery unit 13 and a clock generation unit 14.

  The clock restoration unit 13 generates an internal clock signal iCLK from an embedded clock type input signal Sin in which a clock component is embedded in a data signal. Then, the clock restoration unit 13 provides the clock generation unit 14 with the input signal Sin as the internal clock signal iCLK in response to the reset signal RES being enabled. The clock restoration unit 13 receives the DLL lock signal LOCK and the mask signal MASK. The clock restoration unit 13 outputs the input signal Sin that is input during a period in which the mask signal MASK is in the mask release state, as the internal clock signal iCLK. The clock restoration unit 13 outputs the internal clock signal iCLK at a constant value (for example, low level) regardless of the input signal Sin while the mask signal MASK is in the masked state. Further, the clock restoration unit 13 is a mask signal during a period in which the lock signal LOCK for notifying that the difference between the frequency of the multiphase clock signal SCLK and the frequency of the internal clock signal iCLK has converged within a certain range. Mask processing for the input signal Sin by MASK is stopped.

  The clock generator 14 generates a multiphase clock signal SCLK having a frequency corresponding to the frequency of the internal clock signal iCLK, and outputs one signal selected from the multiphase clock signal SCLK as a restored clock signal. Further, the clock generation unit 14 outputs a mask signal MASK having a logic level (for example, a high level) indicating a mask state before and after the switching timing of the generation cycle of the multiphase clock signal SCLK. The mask signal instructs the clock restoration unit 13 to perform mask processing for masking other than the input signal input before and after the switching timing of the generation cycle of the multiphase clock signal SCLK. Further, the clock generation unit 14 outputs a lock signal LOCK that notifies that the difference between the frequency of the multiphase clock signal SCLK and the frequency of the internal clock signal iCLK has converged within a certain range. The lock signal LOCK assumes a first logic level (for example, high level) in the locked state and a second logic level (for example, low level) in the non-locked state.

  The lock determination circuit 15 compares the number of pulses of the internal clock signal iCLK and the number of pulses of the input signal Sin, and enables the reset signal RES output to the clock restoration unit when the comparison result does not match. Further, the lock determination circuit 15 enables the reset signal RES regardless of the comparison result of the number of pulses during the period in which the data enable signal DE included in the restoration control signal is in the disabled state (for example, the clock training period).

  The lock determination circuit 15 includes a waveform shaping unit 16, a pulse number comparison unit 17, and a lock determination unit 18. The waveform shaping unit 16 detects the edge of the input signal Sin and generates the extracted edge signal ED. The waveform shaping unit 16 generates the extracted edge signal ED only for either the rising edge or the falling edge of the input signal Sin. The waveform shaping unit 16 according to the first embodiment generates the extracted edge signal ED with respect to the rising edge of the input signal Sin.

  The pulse number comparison unit 17 outputs a comparison signal PCOMP that is disabled in a period in which the number of pulses of the extracted edge signal ED and the number of pulses of the internal clock signal iCLK are different. The lock determination unit 18 enables the reset signal RES when the data enable signal ED is disabled and the comparison signal PCOMP is inconsistent.

  Next, detailed circuits in the clock restoration circuit 12 and the lock determination circuit 15 will be described. First, a detailed block diagram of the clock recovery circuit 12 is shown in FIG. FIG. 3 shows a detailed block diagram especially regarding the clock generation unit 14. Therefore, here, the clock generation unit 14 will be described in detail. The clock generation unit 14 includes a DLL (Delay Locked Loop) circuit 141, a mask signal generation unit 142, and a selection circuit 143.

  The DLL circuit 141 adjusts the period to the internal clock signal iCLK (Delay Lock), and internally divides the internal clock signal iCLK into N or an integer multiple of N to generate the internal multiphase clock signal iSCLK. In the example shown in FIG. 3, the DLL circuit 141 generates an internal multiphase clock signal iSCLK including clock signals twice as many as N.

  The mask signal generation unit 142 generates a mask signal MASK for extracting a clock edge of the input signal Sin based on the internal clock signal iCLK and the internal multiphase clock signal iSCLK. The mask signal generation unit 142 selects two clock edges that can set an optimum period for generating the mask signal MASK among the clock edges of the internal multiphase clock signal iSCLK, and selects the logic level of the mask signal MASK. The period between two clock edges is unmasked (for example, high level). Specifically, when the internal multiphase clock signal iSCLK is a clock having an internal dividing point twice (for example, 2N) of the multiphase clock signals CLK1 to CLKn, the internal multiphase before and after the edge of the internal clock signal iCLK. The clock signal iSCLK is set to the rising edge and the falling edge of the mask signal MASK, respectively. As a result, the clock restoration circuit 12 can follow jitter with a cycle within ± 50% of the clock signal in the input signal Sin (fluctuation of the internal clock signal iCLK).

  The selection circuit 143 selects and outputs N sampling clocks CLK1 to CLKN having an optimal timing for sampling N-bit serial data from the internal multiphase clock signal iSCLK. When the internal fraction of the DLL circuit is N, the internal multiphase clock iSCLK is output as it is as the multiphase clock SCLK. In addition, the selection circuit 143 selects a clock signal optimum for taking in the restoration data from the internal multiphase clock signal iSCLK, and outputs the selected clock signal as the restoration clock signal. Note that which clock signal the selection circuit 143 uses as the multiphase clock signal SCLK and the restoration clock signal may be set in advance, and the conversion result of the serial-parallel conversion circuit 11 is monitored. May be determined.

  Next, details of the clock restoration unit 13 will be described. FIG. 4 shows a circuit diagram of the clock restoration unit 13 according to the first exemplary embodiment. As illustrated in FIG. 4, the clock restoration unit 13 includes an AND circuit 131, a selector control unit 132, an inverter 134, and a selector 135.

  The AND circuit 131 performs an OR operation between the input signal Sin input to one input terminal and the mask signal MASK input to the other input terminal, and switches the logic level of the output signal according to the operation result. More specifically, the AND circuit 131 sets the output signal to a high level when both the input signal Sin and the mask signal MASK are at a high level, and sets the output signal to a low level under other input conditions. That is, the AND circuit 131 uses the input signal Sin as an output signal as it is when the mask signal MASK is at a high level (mask release state).

  The selector control unit 132 outputs a selection signal that specifies a signal to be selected by the selector 135 based on the lock signal LOCK and the reset signal RES. More specifically, the selector control unit 132 includes a NOR circuit 133 with an inverting input. Then, the lock signal LOCK is input to the inverting input terminal of the NOR circuit 133 with inverting input, and the reset signal RES is input to the normal rotation input terminal. Then, the NOR circuit 133 with inverting input sets the output signal to a high level when the lock signal LOCK is at a high level (lock state) while the reset signal RES is at a low level (disable state). On the other hand, the NOR circuit 133 with an inverting input sets the output signal to a low level when the reset signal RES is at a high level (enabled state) and when the lock signal LOCK is at a low level (non-locked state).

  The selector 135 is supplied with an output signal of the NOR circuit 133 with inverting input and a signal obtained by inverting the output signal of the NOR circuit 133 with inverting input by the inverter 134 as selection signals. The selector 135 has switches SW1 and SW2. The switch SW1 is controlled in its open / closed state based on the inverted signal of the output signal of the NOR circuit 133 with an inverting input. The open / close state of the switch SW2 is controlled based on the output signal of the NOR circuit 133 with an inverting input. That is, the switches SW1 and SW2 are controlled exclusively between the open state and the closed state. The switch SW1 is closed when the input signal Sin is output as the internal clock signal iCLK. The switch SW2 is closed when the output signal of the AND circuit 131 is output as the internal clock signal iSCLK.

  From the above description, the AND circuit 131 outputs an output signal that includes only the rising edge component of the input signal Sin that is input during the period in which the mask signal MASK is in the enabled state. The pulse width of this output signal is the width from the rising edge of the input signal Sin to the falling edge of the mask signal MASK. The selector control unit 132 and the selector 135 select the output signal of the AND circuit 131 as the internal clock signal iCLK when the reset signal RES is disabled and the lock signal LOCK indicates the locked state. On the other hand, the selector control unit 132 and the selector 135 select the input signal Sin as the internal clock signal iCLK when the reset signal RES is enabled or the lock signal LOCK indicates an unlocked state.

  Next, details of the waveform shaping unit 16 will be described. FIG. 5 shows a detailed circuit diagram of the waveform shaping unit 16 according to the first exemplary embodiment. As illustrated in FIG. 5, the waveform shaping unit 16 includes an inverter 161, a delay circuit 162, and an AND circuit 163. The inverter 161 inverts the input signal Sin and supplies the inverted signal to the delay circuit 162. The delay circuit 162 delays the input signal and outputs the delayed signal. The AND circuit 163 sets the extraction edge signal ED to high level when both the input signal Sin and the output signal of the delay circuit 162 are high level. That is, the waveform shaping unit 16 outputs, as the extracted edge signal ED, a pulse signal that becomes high level from the timing when the input signal Sin becomes high level to the timing when the output of the delay circuit 162 switches from high level to low level. To do. That is, the extracted edge signal ED is a pulse signal having the same edge as the rising edge of the input signal Sin.

  Next, details of the pulse number comparison unit 17 will be described. FIG. 6 is a block diagram of the pulse number comparison unit according to the first exemplary embodiment. As shown in FIG. 6, the pulse number comparison unit 17 includes a pulse number comparator 171 and a delay circuit 175. The pulse number comparator 171 includes counters 172 and 173 and a comparator 174. The counter 172 generates a first count value by using the number of pulses of the extracted edge signal ED as a coefficient. The counter 173 generates a second count value by multiplying the number of pulses of the internal clock signal iCLK. The comparator 174 compares the first count value and the second count value. When the two count values match, the comparison notice signal PRECOMP is set to a low level (match state). The warning signal PRECOMP is set to a high level (inconsistent state). The delay circuit 175 delays the comparison notice signal PRECOMP in synchronization with the internal clock signal iCLK and outputs the comparison signal PCOMP. The delay circuit 175 can change the value of the comparison signal PCOMP in accordance with the beginning of the next serial data.

  It should be noted that the number of bits of the count values of the counters 172 and 173 only needs to be secured to the extent that it can be confirmed that the frequency of the input signal Sin has changed to an integral multiple. The counters 172 and 173 are reset at the same time, but the reset processing cycle is such that the frequency of the frequency based on the input signal Sin becomes low after the DLL circuit 141 is unlocked after a mismatch between the two count values is detected. What is necessary is just to set to the length which can ensure the time until adjustment can be started.

  Next, details of the lock determination unit 18 will be described. FIG. 7 shows a circuit diagram of the lock determination unit according to the first embodiment. As shown in FIG. 7, the lock determination unit 18 includes a NOR circuit 181 with an inverting input. In the NOR circuit 181 with inverting input, the comparison signal PCOMP is input to the inverting input terminal, and the data enable signal DE is input to the normal rotation input terminal. Then, the NOR circuit 181 with an inverting input sets the reset signal high when the comparison signal PCOMP is high level (mismatch state) during the period when the data enable signal DE is low level (disenabled state or state indicating the clock training period). Level (enabled state). Further, the NOR circuit 181 with an inverting input causes the reset signal to be low level (even if the comparison signal PCOMP is high level (mismatch state) while the data enable signal DE is high level (enable state or state indicating data period). Disabled state).

  Here, the operation of the data receiving circuit 10 according to the first exemplary embodiment will be described. First, the operation of the data receiving circuit 10 during the clock training period and the operation of the data receiving circuit 10 during the data period will be described. FIG. 8 is a timing chart showing the operation of the data receiving circuit according to the first embodiment.

  In the example shown in FIG. 8, the period in which the data enable control signal DE is in the disable state (low level) is the clock training period, and the period in which the data enable control signal DE is in the enabled state (high level) is the data period. In the period before the timing t1 in the clock training period, the input signal Sin is only a signal component including the leading clock edge of the serial data Data embedded in the input signal Sin (that is, not including data). On the other hand, the input signal Sin in the data period after the timing t2 includes actual data following the leading clock edge of the serial data. Further, according to the protocol of the input signal Sin, the input signal Sin includes a code signal indicating that the data period is switched at the timing t1 before the timing t2 when the data period is reached. After receiving this code signal, the data receiving circuit 10 receives serial data as an input signal after a period determined by the protocol, and therefore before the timing t3 when the serial data is transmitted (for example, at timing t2). The data enable signal DE is enabled (high level). The data receiving circuit 10 completes preparation for receiving serial data when the data enable signal DE is enabled. The code signal includes not only the data enable signal DE but also a plurality of restoration control signals corresponding to the type of the code signal defined in the protocol in the input signal.

  In the period before the timing t0, the input signal Sin is output as the internal clock signal iCLK while the reset signal RES is in the enable state (high level). On the other hand, the reset signal RES is disabled (low level) during the period after the timing t0, and the active edge of the input signal Sin is input during the period when the mask signal MASK is unmasked (high level). A signal that becomes high level during the period when both of the mask signals MASK are high level is generated as the internal clock signal iCLK.

  As described above, when the input signal Sin is a stable signal within the standard defined by the protocol, the data receiving circuit 10 according to the first embodiment has the data enable signal DE disabled. During the clock training period, since the DLL circuit 141 is not locked at first, the lock signal LOCK is in an unlocked state (low level), and the input signal Sin is output as it is as the internal clock iCLK. Thereafter, when the DLL circuit 141 is locked and the lock signal LOCK is in a locked state (high level), the mask signal MASK is also stabilized at the same time. At that time, a signal obtained by ORing the input signal Sin and the mask signal MASK is output as the internal clock signal iCLK. As a result, even when the data enable signal DE becomes high level and serial data is input, the data receiving circuit 10 causes the DLL circuit 141 to lock the multiphase clock signal SCLK to the input signal Sin. Can be maintained. Actually, these processes need to be completed before the code signal Code for enabling the data enable signal DE (high level) is input (before timing t1 in FIG. 8). is there.

  If it is recognized that the DLL circuit 141 is unlocked for some reason during the clock training period in which the data enable signal DE is in the disabled state (low level), the mask signal MASK signal also becomes incorrect. However, in such a case, the input signal Sin is output as it is as the internal clock signal iCLK because the lock signal LOCK is in an unlocked state (low level). As a result, even in the data period, the DLL circuit 141 can be locked again.

  Here, a big problem is that, when a change in the input signal Sin that cannot be recognized that the DLL circuit 141 is unlocked occurs, the DLL circuit 141 cannot be brought into the locked state again by the conventional technique. That is, the conventional technique has a problem in that the unlocking of the DLL circuit 141 cannot be corrected when the clock embedded in the input signal Sin changes to an integral multiple of the clock frequency up to that time. However, this problem can be solved by using the data receiving circuit 10 according to the first embodiment. Therefore, the operation of the data receiving circuit 10 will be described in more detail below.

  FIG. 9 is a timing chart showing the detailed operation of the data receiving circuit according to the first embodiment during the clock training period. In the example shown in FIG. 9, the frequency of the input signal Sin changes twice in the period B. In the example shown in FIG. 9, the DLL circuit 141 generates an internal multiphase clock signal iSCLK including 2N clock signals. In FIG. 9, an odd-numbered clock among the 2N internal multiphase clock signals iSCLK is generated. The signals are shown as clock signals CLK1 to CLKn. Furthermore, in the example shown in FIG. 9, the data enable signal DE is in a disable state. That is, the example shown in FIG. 9 shows the operation of the data receiving circuit 10 during the clock training period.

  In the example shown in FIG. 9, the lock signal LOCK is in a locked state (high level) in the period A. That is, in the example shown in FIG. 9, the DLL circuit 141 is in the locked state before the period A, and the mask signal MASK is in the mask release state (high level) during the period in which the rising edge of the input signal Sin can be captured. Is generated as follows.

  In such a case, when the data receiving circuit 10 according to the first embodiment is not used, the DLL circuit 141 is not released from the locked state even if the frequency of the input signal Sin changes twice after the period A. There arises a problem that the frequency 141 cannot cope with the frequency change of the input signal Sin. More specifically, when the data receiving circuit 10 is not used, after the frequency of the input signal Sin changes twice in the period B, the clock edge of the input signal Sin input in the period C is masked by the mask signal MASK. In addition, the clock edge of the input signal Sin input in the period D is not masked. Therefore, when the data receiving circuit 10 is not used, the clock edge of the input signal Sin input in the period C is not output as the internal clock signal iCLK. Thereby, when the data receiving circuit 10 is not used, even if the frequency of the input signal Sin is switched after the DLL circuit 141 is locked, the DLL circuit 141 maintains the locked state, and the multiphase clock signal SCLK and the restoration are restored. There arises a problem that the frequency of the clock signal is not switched.

  However, as shown in FIG. 9, in the data receiving circuit 10 according to the first exemplary embodiment, the waveform shaping unit 16 generates a pulse of the extracted edge signal ED from the clock edge of the input signal Sin in the period C. Therefore, in the period C, a difference occurs between the first count value and the second count value generated by the counters 172 and 173 of the pulse number comparison unit 17, and the period in which the internal clock signal iCLK is input next. At D, the comparison notice signal PRECOMP becomes inconsistent (high level). Then, during the period E during which the internal clock signal iCLK is input, the lock determination unit 18 enables the reset signal RES (high level) in response to the pulse number comparison unit 17 setting the comparison signal PCOMP to a mismatch state (high level). Level).

  Then, in response to the reset signal RES being enabled in the period E, the clock restoration unit 13 outputs the input signal Sin as the internal clock signal iCLK. Accordingly, in the period F, the clock edge is input to the DLL circuit 141 at a timing different from that before the period E. Therefore, the DLL circuit 141 sets the lock signal LOCK to the unlocked state (low level) and continues to the internal state until the locked state is again entered. The frequency of the multiphase clock signal iSCLK is adjusted. Thereafter, the DLL circuit 141 recognizes that the frequency of the internal multiphase clock signal iSCLK is locked to the internal clock signal iCLK (this period is the same signal as the input signal Sin), and sets the lock signal LOCK to the locked state in the period H. . Thereby, after the period H, the internal clock signal iCLK having the clock edge of the input signal Sin masked by the mask signal MASK is generated.

  In the example shown in FIG. 9, in the period F, the counters 172 and 173 of the pulse number comparison unit 17 are reset, so that the comparison notice signal PRECOMP is switched to the coincidence state (low level). In the period G, which is the input timing of the internal clock signal iCLK after the period F, the pulse number comparison unit 17 switches the comparison signal PCOMP to the coincidence state (low level), so that the lock determination unit 18 also resets the reset signal RES in the period G. Is disabled. At this time, since the DLL circuit 141 has already locked the lock signal LOCK, the clock restoration unit 13 uses the input signal Sin as the internal clock signal iCLK until the period H in which the lock signal LOCK is locked even after the period G. Output.

  From the above description, the data receiving circuit 10 according to the first exemplary embodiment includes the clock restoration unit 13 and the clock generation unit 14. Then, the clock restoration unit 13 generates the internal clock signal iCLK from the embedded clock type input signal Sin in which the clock component is embedded in the data signal. The clock generator 14 generates a multiphase clock signal SCLK having a frequency corresponding to the frequency of the internal clock signal iCLK, and outputs one signal selected from the multiphase clock signal SCLK as a restored clock signal. Then, the data receiving circuit 10 compares the number of pulses of the internal clock signal iCLK and the number of pulses of the input signal Sin, and enables the reset signal RES to be output to the clock restoration circuit 13 when the comparison result does not match. . Then, in response to the reset signal RES being enabled, the clock restoration unit 13 provides the input signal Sin to the clock generation unit 14 as the internal clock signal iCLK. As a result, in the data receiving circuit 10 according to the first exemplary embodiment, even if the DLL circuit 141 cannot recognize the frequency change of the input signal Sin, such as when the frequency of the input signal Sin is switched to an integral multiple, The lock state of the circuit 141 can be released, and the DLL circuit 141 can be readjusted for the frequency of the generated clock signal.

  When the input signal Sin is directly input to the DLL circuit 141 without using the mask signal MASK, a clock edge (for example, an edge of data) other than the leading clock edge of the input signal Sin is input during the data period. There arises a problem that the circuit 141 does not operate correctly. However, in the data receiving circuit 10 according to the first embodiment, at least during the period when the data enable signal DE indicates the data period, the mask signal MASK masks other than the leading clock edge as long as the lock signal LOCK is in the locked state. Therefore, the problem described above does not occur.

  Further, in the data receiving circuit 10 according to the first embodiment, as shown in FIGS. 5 to 7, the circuit constituting the lock determination circuit 15 can be configured with a simple circuit. Therefore, an increase in circuit area due to the addition of the lock determination circuit 15 can be reduced.

  Further, the data receiving circuit 10 according to the first embodiment can be applied to a driver circuit of a display device. In the display device, the drive speed of the display panel may be changed based on the type of video or a user instruction. When such a change in the driving speed occurs, the timing controller 3 instructs the data receiving circuit 10 about the clock training period by the data enable signal DE. Then, the frequencies of the multiphase clock signal SCLK and the recovered clock signal generated by the DLL circuit 141 that is already locked must be changed. At this time, in the conventional method, when the frequency of the input signal Sin is switched by an integral multiple, it is difficult to make the frequencies of the multiphase clock signal SCLK and the restored clock signal follow the frequency of the input signal Sin after switching. However, the data receiving circuit 10 according to the first embodiment can accurately follow such a frequency change of the input signal Sin. That is, a more remarkable effect can be obtained in the driver circuit including the data receiving circuit 10 according to the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display panel 3 Timing controller 4a-4c Data driver module 5a-5c Data driver circuit 6a, 6b Scan driver module 7a, 7b Scan driver circuit 8 Pixel electrode 10, 10a-10c Data receiving circuit 11 Serial parallel conversion circuit 12 Clock recovery circuit 13 Clock recovery unit 14 Clock generation unit 15 Lock determination circuit 16 Waveform shaping unit 17 Pulse number comparison unit 18 Lock determination unit 141 DLL circuit 142 Mask signal generation unit 143 Selection circuit 131 AND circuit 132 Selector control unit 133, 181 Inversion NOR circuit with input 134, 161 Inverter 135 Selector 162, 175 Delay circuit 163 AND circuit 171 Pulse number comparator 172, 173 Counter 174 Comparator SW1, SW2 switch 20 driver circuit SIG signal line SCAN scan line Tr TFT transistor Sin input signal iSCLK internal multiphase clock signal SCLK multiphase clock signal LOCK DLL lock signal MASK mask signal iCLK internal clock signal PCOMP comparison signal PRECOMP comparison advance notice signal RES reset Signal ED Extraction edge signal DE Data enable signal

Claims (11)

A clock recovery unit that generates an internal clock signal from an embedded clock method input signal in which a clock component is embedded in a data signal;
A clock generation unit that generates a multiphase clock signal having a frequency corresponding to the frequency of the internal clock signal, and outputs one signal selected from the multiphase clock signal as a restored clock signal;
A lock determination circuit that compares the number of pulses of the internal clock signal and the number of pulses of the input signal, and enables a reset signal to be output to the clock restoration unit when the comparison result does not match,
The clock recovery unit is a data receiving circuit that applies the input signal as the internal clock signal to the clock generation unit in response to the reset signal being enabled.   The data receiving circuit according to claim 1, further comprising: a serial / parallel conversion circuit that converts the input signal from parallel data to serial data using the multiphase clock signal to generate a data signal and a control signal for a subsequent circuit.   The data receiving circuit according to claim 2, wherein the lock determination circuit disables the reset signal regardless of the comparison result during a period in which the data enable signal included in the control signal is in an enabled state. The lock determination circuit includes:
A waveform shaping unit that detects an edge of the input signal and generates an extracted edge signal;
A pulse number comparison unit that outputs a comparison signal that is a value indicating a mismatch state in a period in which the number of pulses of the extracted edge signal and the number of pulses of the internal clock signal are different from each other;
The data reception circuit according to claim 3, further comprising: a lock determination unit that enables the reset signal when the data enable signal is in an enabled state and the comparison signal indicates a mismatch state. The clock generator is
A DLL (Delay Locked Loop) circuit for generating the multiphase clock signal;
A mask signal generation unit that generates a mask signal for extracting a clock edge of the input signal based on the internal clock signal and the multiphase clock signal;
2. The data receiving circuit according to claim 1, wherein the clock restoration unit outputs the input signal input during a period in which the mask signal is in a mask release state as the internal clock signal. The DLL circuit generates a lock signal for notifying that the difference between the frequency of the multi-phase clock signal and the frequency of the internal clock signal is locked within a certain range,
The data receiving circuit according to claim 5, wherein the clock restoration unit stops mask processing on the input signal by the mask signal during a period in which the lock signal indicates an unlocked state.   The data receiving circuit according to claim 1, wherein the input signal is output from a timing controller provided one for the plurality of data receiving circuits.   The data receiving circuit according to claim 7, wherein the input signal is switched by the timing controller so that a frequency becomes an integral multiple of the frequency.   The data receiving circuit according to claim 2, further comprising a driver circuit that receives the data signal based on the restored clock signal and drives a pixel of a display panel. A clock recovery unit that generates an internal clock signal from an embedded clock method input signal in which a clock component is embedded in a data signal;
A clock generation unit that generates a multiphase clock signal having a frequency corresponding to the frequency of the internal clock signal, and outputs one signal selected from the multiphase clock signal as a restored clock signal;
A data receiving method for a data receiving circuit comprising:
Compare the number of pulses of the internal clock signal and the number of pulses of the input signal,
When the comparison result is inconsistent, the reset signal output to the clock restoration unit is enabled,
A data receiving method for applying the input signal as the internal clock signal to the clock generator in response to the reset signal being enabled. A clock recovery unit that generates an internal clock signal from an embedded clock method input signal in which a clock component is embedded in a data signal;
A clock generation unit that generates a multiphase clock signal having a frequency corresponding to the frequency of the internal clock signal, and outputs one signal selected from the multiphase clock signal as a restored clock signal;
A lock determination circuit that compares the number of pulses of the internal clock signal with the number of pulses of the input signal and enables a reset signal to be output to the clock restoration unit when the comparison result is inconsistent;
A serial-parallel conversion circuit that converts the input signal from parallel data to serial data using the multiphase clock signal to generate a data signal and a control signal for a subsequent circuit;
A driver circuit that receives the data signal based on the restored clock signal and drives the pixels of the display panel;
The clock restoration unit is a driver circuit that provides the input signal to the clock generation unit as the internal clock signal in response to the reset signal being enabled.

Images