CN104079268A - Method and device for achieving arbitrary waveform occurrence and display of pulse power supply - Google Patents
Method and device for achieving arbitrary waveform occurrence and display of pulse power supply Download PDFInfo
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- CN104079268A CN104079268A CN201410295203.8A CN201410295203A CN104079268A CN 104079268 A CN104079268 A CN 104079268A CN 201410295203 A CN201410295203 A CN 201410295203A CN 104079268 A CN104079268 A CN 104079268A
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Abstract
The invention relates to a method and device for achieving arbitrary waveform occurrence and display of a pulse power supply. The achieving method includes the following steps that a waveform data file of any given waveform is generated; waveform data of the waveform data file are read, downloaded and cached to generate waveform digital signals; digital-to-analogue conversion is conducted on the waveform digital signals to generate waveform analog signals; the pulse power supply is controlled to generate pulse current analog signals according to the waveform analog signals; the pulse current analog signals are collected and the digital-to-analogue conversion is conducted, and the converted pulse current digital signals are cached to generate pulse current data; the pulse current data are uploaded and displayed to be pulse current waveforms. According to the method and device, occurrence and display of any given waveform easy to be edited and controlled are achieved based on the DSP plus FPGA framework and internet interface technology, and real time performance, repeatability, high accuracy, high stability and easy operation of occurrence and display of the waveforms are achieved.
Description
Technical field
The present invention relates to digital processing field, relate in particular to a kind of random waveform for the pulse power and occur and the implementation method and the device that show.
Background technology
The fields such as random waveform occurs with display unit communicating by letter, observing and controlling, navigation, radar, medical treatment have a wide range of applications, its important indicator is arbitrariness, accuracy, the real-time of output waveform with respect to given waveform, is mainly determined by given waveform compilation control mode and response time.Fig. 1 is that in prior art, programmable pulse power-type waveform occurs and the theory diagram of display unit, in this figure, programmable pulse power supply is the switching mode pulse power, mainly by controller, insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor) topography module, power supply output module composition.In this wider device of application, AWG (Arbitrary Waveform Generator) provides by programming any given waveform that the pulse power needs, produce pulse width modulation (PWM by pulse power feedback controller, Pulse Width Modulation) signal, control IGBT grid trigger impulse duty ratio, make any given waveform of the pulse current waveform trace pulse power supply input of pulse power output, reach the object of the pulse current waveform of control impuls power supply output arbitrary shape, the shape of pulse current waveform and the shape of given waveform that are the pulse power are consistent, any given waveform and pulse current waveform are compared simultaneously, calculate tracking accuracy, flat-top stability etc., thereby can revise in real time the shape of given waveform with the shape of the pulse current waveform of change pulse power output, to meet best demand.
But domestic and international at present, AWG (Arbitrary Waveform Generator) mostly adopts the special any given waveform of waveform compilation Software Create, for example adopt Direct Digital (DDS, Direct Digital Synthesis) realize AWG (Arbitrary Waveform Generator), this AWG (Arbitrary Waveform Generator) is expensive and not easy to operate, the given waveform of an arbitrary shape of editor usually requires a great deal of time and energy, also cannot meet waveform shows simultaneously, conventionally need to realize record by professional digital oscilloscope again, gather and observe the pulse current waveform of output, not only response speed is poor, and precision and stability are also difficult to ensure.
Summary of the invention
The object of the present invention is to provide a kind of fast response time, easy operating, the generation of the random waveform for the pulse power that precision is high, stability is strong and the implementation method and the device that show, for solving problems of the prior art with not enough.
For achieving the above object, technical scheme proposed by the invention is:
A kind of random waveform for the pulse power of the present invention occurs to comprise the following steps with the implementation method showing: the Wave data file that generates any given waveform; Read the Wave data in described Wave data file, described Wave data is downloaded and buffer memory generation waveform digital signal; Described waveform digital signal is carried out to digital-to-analogue conversion and generate waveform modelling signal; According to pulse power production burst current analog signal described in described waveform modelling signal controlling; Gather described pulse current analog signal and carry out analog-to-digital conversion, by the pulse current digital signal buffer memory production burst current data after conversion; And by described pulse current data upload and be shown as pulse current waveform.
Further, described implementation method is further comprising the steps of: described any given waveform and described pulse current waveform are compared, according to comparative result, described Wave data file is revised in real time, to realize the real-time tracking of described pulse current waveform to described any given waveform.
Further, describedly the Wave data buffer memory that reads is generated to waveform digital signal step comprise the following steps: described described Wave data is downloaded and buffer memory generates waveform digital signal step and comprises the following steps: described Wave data is downloaded and buffer memory to the first memory block, generated first data cached; Data cachedly transfer to the second memory block from described the first memory block by described first, and buffer memory generates described waveform digital signal.
Further, described pulse current digital signal buffer memory production burst current data step after conversion is comprised the following steps: described pulse current digital signal buffer memory to described the second memory block, is generated second data cached; Data cachedly transfer to described the first memory block from described the second memory block by described second, and buffer memory production burst current data.
A kind of random waveform for the pulse power of the present invention occurs to comprise with the implement device showing the central control unit being connected successively, transmission buffer unit and signal conversion unit, wherein, described central control unit is for generating the Wave data file of any given waveform, and the Wave data reading is downloaded to described transmission buffer unit from described Wave data file, and the pulse current data of uploading are shown as to pulse current waveform, and described any given waveform and described pulse current waveform are compared, according to comparative result, described Wave data file is revised in real time, to realize the real-time tracking of described pulse current waveform to described any given waveform, described transmission buffer unit is used for described Wave data buffer memory to generate waveform digital signal, and transfers to described signal conversion unit, and pulse current digital signal buffer memory is generated to described pulse current data, and transfers to described central control unit, and described signal conversion unit is for being converted to described waveform digital signal waveform modelling signal and transferring to the described pulse power, and the pulse current analog signal of described pulse power output is converted to described pulse current digital signal, and transfer to described transmission buffer unit.
Further, described central control unit comprises waveform compilation module, waveform transport module, waveform memory area and waveform display module.
Further, described transmission buffer unit comprises DSP processing unit and FPGA processing unit.
Further, described DSP processing unit comprises a first interface and one first memory block; Described FPGA processing unit comprises one second interface, one second memory block and clock administration module.
Further, described signal conversion unit comprises D/A converter module and analog-to-digital conversion module.
Further, described implement device also comprises the described pulse power, for generating described pulse current analog signal and transfer to described signal conversion unit according to described waveform modelling signal, the described pulse power is the switching mode pulse power, and the described switching mode pulse power comprises controller, insulated gate bipolar transistor (IGBT) topography module and power supply output module.
Compared with prior art, a kind of random waveform for the pulse power of the present invention occurs and the implementation method and the device that show, there is following beneficial effect: the present invention adopts the digital processing system and the high-performance that add FPGA framework based on DSP, the technology of high bandwidth embedded system level interconnecting interface has realized generation and the demonstration of any given waveform that is easy to editor's control, not only improve the response time of implement device to any given waveform, realize the real-time that waveform shows, repeatability and easy operating, and improve the tracking accuracy of pulse current waveform for any given waveform, high accuracy and high stability that waveform shows are realized.
Brief description of the drawings
Fig. 1 is that in prior art, programmable pulse power-type waveform occurs and the theory diagram of display unit.
Fig. 2 is the structural representation of the implement device of a kind of generation of the random waveform for the pulse power of the present invention and demonstration.
Fig. 3 is the multiple line distance management method schematic diagram of DSP processing unit in one embodiment of the invention.
Fig. 4 is the flow chart of the implementation method of a kind of generation of the random waveform for the pulse power of the present invention and demonstration.
Fig. 5 is the waveform schematic diagram of given waveform in one embodiment of the invention.
Fig. 6 is the interconnected method schematic diagram of SRIO interface in one embodiment of the invention.
Fig. 7 is SRIO interface data transmission control flow chart in one embodiment of the invention.
Fig. 8 is the comparative result schematic diagram of any given waveform and pulse current waveform in one embodiment of the invention.
Embodiment
Below with reference to accompanying drawing, the present invention is given to elaboration further.
Fig. 2 is the structural representation of the implement device of a kind of generation of the random waveform for the pulse power of the present invention and demonstration, and occurring with the implement device of demonstration hereinafter to be referred as the random waveform for the pulse power is implement device.As shown in Figure 2, this implement device 1 comprises the central control unit 10, transmission buffer unit 20, signal conversion unit 30 and the pulse power 40 that connect successively.Wherein, this central control unit 10 is for generating the Wave data file of any given waveform, and the Wave data reading is downloaded to transmission buffer unit 20 from this Wave data file, and the pulse current data that transmission buffer unit 20 is uploaded are shown as pulse current waveform, and any given waveform and pulse current waveform are compared, according to comparative result, Wave data file is revised in real time, to realize the real-time tracking of pulse current waveform to any given waveform; This transmission buffer unit 20 is for generating waveform digital signal by Wave data buffer memory, and transfer to signal conversion unit 30, and pulse current digital signal buffer memory production burst current data after signal conversion unit 30 is changed, and transfer to central control unit 10; This signal conversion unit 30 is for waveform digital signal being converted to waveform modelling signal and transferring to the pulse power 40, and the pulse current analog signal that the pulse power 40 is exported is converted to pulse current digital signal, and transfers to transmission buffer unit 20; This pulse power 40 is for according to waveform modelling signal production burst current analog signal, and transfers to signal conversion unit 30.
Particularly, central control unit 10 comprises waveform compilation module 101, waveform transport module 102, waveform memory area 103 and waveform display module 104, and waveform compilation module 101 is for generating the Wave data file of any given waveform; Waveform transport module 102 is for being downloaded to transmission buffer unit 20 by the Wave data reading from this Wave data file; The pulse current data that upload for buffer memory transmission buffer unit 20 waveform memory area 103; Waveform display module 104 is for being shown as pulse current waveform by the pulse current data of waveform memory area 103.
Transmission buffer unit 20 comprises DSP processing unit 201 and FPGA processing unit 202, wherein, DSP processing unit 201 comprises a first interface A and one first memory block 2011, and FPGA processing unit 202 comprises one second interface B, one second memory block 2021 and clock administration module 2022.Particularly, this first interface A is for the transmission of Wave data and pulse current data; The first memory block 2011 is first data cached for Wave data buffer memory is generated, and the second data cached buffer memory production burst current data that the second memory block 2021 buffer memorys are generated.This second interface B is for first data cached and the second data cached transmission; The second memory block 2021 is for the first data cached buffer memory is generated to waveform digital signal, and the pulse current digital signal buffer memory that signal conversion unit 30 is changed generation generated second data cached; This Clock management module 2022 is for controlling the required clock signal of the each module of this implement device 1, in an embodiment of the present invention, this clock module 2022 comprises clock crystal oscillator source and a phase-locked loop (PLL of a 50MHz, Phase Locked Loop), frequency division and/or frequency multiplication by this clock crystal oscillator source through PLL, thus the required clock signal of each module generated.
In an embodiment of the present invention, DSP processing unit 201 is solidified and is realized by dsp chip, the model of the dsp chip adopting is TMS320C6455, it has high-performance more, more simplifies the integrated peripheral hardware of code, more on-chip memories and superelevation bandwidth than dsp chip in the past, and the physical chip that inner integrated gigabit ethernet interface only needs sheet to configure power consumption and small volume outward can be realized network data transmission.Fig. 3 is the multiple line distance management method schematic diagram of DSP processing unit 201 in the present embodiment, the Integrated Development Environment CCS3.3 of embedded real-time operating system DSP/BIOS-based on TI company, this DSP/BIOS operating system is by task management priority preemptive policy scheduler task, complete successively after the inter-related task of hardware interrupts, background thread, in user task management phase, realize the inter-related task of DSP processing unit 201.In another embodiment of the present invention, FPGA processing unit 202 is solidified and is realized by fpga chip, the fpga chip model adopting is the SPARTAN-6 of XILINX company, it is as main logic control device, the optical fiber of controlling Clock management, the pulse power source control device of the initialization of each module in implement device 1, each module trigger control and and dsp chip between high speed data transfer and control etc.Add the technology of the digital processing system of FPGA framework and high-performance, high bandwidth embedded system level interconnecting interface based on DSP by this, this implement device can response fast in 2ms, has realized the real-time that waveform shows.
Signal conversion unit 30 comprises D/A converter module 301 and analog-to-digital conversion module 302, and the waveform digital signal of reception is converted to waveform modelling signal by D/A converter module 301, and transfers to the pulse power 40; The pulse current analog signal that analog-to-digital conversion module 302 is exported the pulse power 40 is converted to pulse current digital signal, and transfers to the second memory block 2021 of FPGA processing unit 202.
In an embodiment of the present invention, the pulse power 40 is the switching mode pulse power, this switching mode pulse power 40 comprises controller 401, IGBT topography module 402 and power supply output module 403, and this controller 401 is for producing pwm signal and transfer to IGBT topography module 402 according to waveform modelling signal; This IGBT topography module 402, for according to pwm signal control IGBT grid trigger impulse duty ratio, makes power supply output module 403 export pulse current analog signal; This power supply output module 403 is also exported a pulse power timing signal for controlling this controller 401, with second memory block 2021 of triggering FPGA processing unit 202, waveform digital signal is transferred in the D/A converter module 301 of signal conversion unit.It should be noted that, the pulse power can also be single positive pulse power supply or two positive and negative pulse power.
In an embodiment of the present invention, this implement device 1 can also comprise an external memory, and this external memory can be flash memory FLASH or EPROM, for solidifying initialization process program to realize the initialization of transmission buffer unit 20.In the time that this implement device powers on, initialization process program can be loaded in the DSP processing unit 201 and FPGA processing unit 202 in transmission buffer unit 20 automatically from this external memory, to complete the initialization of dsp chip and fpga chip, for example, this initialization can be that version loads.
Fig. 4 is the flow chart of the implementation method of a kind of generation of the random waveform for the pulse power of the present invention and demonstration, and occurring with the implementation method of demonstration hereinafter to be referred as the random waveform for the pulse power is implementation method.Now, in conjunction with Fig. 2, this implementation method in one embodiment of the invention is explained.
Step 201, the waveform compilation module 101 of central control unit 10 generates the Wave data file of any given waveform.
Wherein, central control unit 10 can be the central processing unit in computer, waveform compilation module 101 can be the MATLAB software operating environment in computer, in this MATLAB software operating environment, the given waveform of arbitrary shape is easy to programming Control, can be the regular figures such as square wave, triangular wave, square wave, also can be the irregular figure of arbitrary shape, in this MATLAB software operating environment, Wave data can be stored as text or the autoexec of arbitrary carry system.
Fig. 5 is the waveform schematic diagram of given waveform in one embodiment of the invention.This given waveform equation is:
This given waveform equation is programmed by MATLAB, carry out the collection of Wave data by stepping more than 0.05us, certainly, also can select a suitable step value to gather by actual demand, in the present embodiment, preferably, MATLAB is stored as gathered Wave data according to stepping 0.05us the text of 16 systems, calls for waveform transport module 102.
Step 202, the waveform transport module 102 of central control unit 10 reads the Wave data in Wave data file, and this Wave data is downloaded to transmission buffer unit 20, and in transmission buffer unit 20, buffer memory generates waveform digital signal.
Wherein, between waveform transport module 102 and transmission buffer unit 20, complete reading and downloading of local Wave data by the udp protocol in gigabit Ethernet communication, comprise there is time tag data packet group bag, unpack, a series of processing such as restructuring, retaking of a year or grade, verification.
In transmission buffer unit 20, this Wave data receiving is transferred to the first memory block 2011 by the first interface A of DSP processing unit 201, by this first memory block 2011 by this Wave data buffer memory and generate first data cached, first data cachedly transfers to the second memory block 2021 by the second interface B of FPGA processing unit 202 again,, called for signal conversion unit 30 by this first data cached buffer memory and generate waveform digital signal by this second memory block 2021.In another embodiment of the present invention, the digital-to-analogue conversion RAM that this waveform digital signal also can be carried by fpga chip buffer memory one-level again, calls for signal conversion unit 30.
Except udp protocol, first interface A also can meet other communication standards, the second interface B can select CPRI interface, OBSAI interface or SRIO interface, and DDR, FIFO, RAM or ROM can be selected in the first memory block 2011 and the second memory block 2021 identical or differently, in the present embodiment, preferably, the second interface B is SRIO interface, and the first memory block 2011 is DDR, and this DDR is the memory space in dsp chip, the second memory block 2021 is RAM, and this RAM is the IP kernel in fpga chip.
Step 203, the D/A converter module 301 of signal conversion unit 30 is carried out digital-to-analogue conversion to waveform digital signal and is generated waveform modelling signal.
Wherein, in the present embodiment, the chip that D/A converter module 301 adopts is 14 DAC2904,20M sampling.
Step 204, D/A converter module 301 is according to the waveform modelling signal controlling pulse power 40 production burst current analog signals.
Wherein, in the present embodiment, the pulse power 40 is a switching mode pulse power, the power supply output module 403 of this switching mode pulse power 40 is controlled inner controller 401 and is exported a pulse power timing signal, and transmit with the optical fiber that FPGA processing unit 202 is connected by it, waveform digital signal is transferred in the D/A converter module 301 of signal conversion unit 30 with second memory block 2021 of triggering FPGA processing unit 202, D/A converter module 301 transfers to controller 401 after waveform digital signal is converted to waveform modelling signal, this controller 401 produces pwm signal and transfers to IGBT topography module 402 according to this waveform modelling signal, IGBT topography module 402 is according to pwm signal control IGBT grid trigger impulse duty ratio, make power supply output module 403 export pulse current analog signal.
Step 205, the analog-to-digital conversion module 302 of signal conversion unit 30 gathers described pulse current analog signal and carries out analog-to-digital conversion, and transmission buffer unit 20 is by the pulse current digital signal buffer memory production burst current data after conversion.
Wherein, in the present embodiment, the chip that analog-to-digital conversion module 302 adopts is 16 AD9248,20M sampling, dual port bus multiplex technique, ceiling voltage ± 5V.
In transmission buffer unit 20, FPGA processing unit 202 is by this pulse current digital data transmission to the second memory block 2021 receiving, by this second memory block 2021 by this pulse current digital signal buffer memory and generate second data cached, the second data cached the first memory block 2011 that transfers to again DSP processing unit 201 by the second interface B of FPGA processing unit 202,, called for central control unit 10 this second data cached buffer memory production burst current data by this first memory block 2011.In another embodiment of the present invention, the analog-to-digital conversion RAM that this pulse current digital signal also can be carried by fpga chip buffer memory one-level again, calls for DSP processing unit 201.
The second interface B can select CPRI interface, OBSAI interface or SRIO interface, DDR, FIFO, RAM or ROM can be selected in the first memory block 2011 and the second memory block 2021 identical or differently, in the present embodiment, preferably, the second interface B is SRIO interface, and the first memory block 2011 is DDR, and this DDR is the memory space in dsp chip, the second memory block 2021 is RAM, and this RAM is the IP kernel in fpga chip.
Refer to Fig. 6, Fig. 7, Fig. 6 is that in one embodiment of the invention, the second interface is the interconnected method schematic diagram of SRIO interface, the Data Transmission Controlling flow chart that Fig. 7 is this interface.The transfer of data of the SRIO agreement that this SRIO interface meets is based on request and response mechanism, and dsp chip carries out communication as initiator by the packet and the fpga chip that comprise source and destination device ID in the present embodiment.On waveform generation link, in the time that the given waveform in the first memory block 2011 has renewal, dsp chip sends operation requests and transmits data to fpga chip, fpga chip is without replying directly in the time receiving a bag packet, after going here and there and changing, data cachedly write the second memory block 2021 by this SRIO interface by first, buffer memory generates waveform digital signal, and after convert waveform modelling signal to through D/A converter module 301 and call for the pulse power 40, export pulse current analog signal by the real-time control impuls power supply 40 of this waveform modelling signal; Show on link at waveform, analog-to-digital conversion module 302 generates the pulse current analog signal storage of collection to the second memory block 2,021 second data cached, call for dsp chip, fpga chip request sends the second data cached packing, reply and allow, after reception, this second buffered data is transferred to the first memory block 2011 by this SRIO interface at dsp chip, then buffer memory production burst current data.
Step 206, transmission buffer unit 20 is the waveform memory area 103 to central control unit 10 by pulse current data upload, by the waveform display module 104 of central control unit 10, these pulse current data is shown as to pulse current waveform.
Wherein, between waveform memory area 103 and transmission buffer unit 20, complete uploading of local pulse current data by the udp protocol in gigabit Ethernet communication, comprise there is time tag data packet group bag, unpack, a series of processing such as restructuring, retaking of a year or grade, verification.Except udp protocol, also can adopt other communication standards.
Waveform display module 104 can be the graphic user interface (GUI in computer, Graphical User Interface), in the present embodiment, under Labview environment, can receive and show the Pulse of Arbitrary current waveform collecting by this gui interface, ruuning situation simultaneously that can also observe relevant device, the for example ruuning situation of the switching mode pulse power in the present embodiment, this ruuning situation mainly comprises that pulse current waveform and any given waveform to receiving compares, calculate the tracking accuracy of the two, the flat-top stability of certain point of observation and running time etc., according to comparative result, the Wave data file in step 201 is revised in real time simultaneously, to realize the real-time tracking of this pulse current waveform to any given waveform, thereby the further stability of test pulse electric power outputting current.
Fig. 8 is the comparative result schematic diagram of any given waveform and pulse current waveform in one embodiment of the invention, what Fig. 8 top showed is given waveform, what Fig. 8 below showed is pulse current waveform, and Fig. 8 right side is to calculate in real time the operation interface of pulse current waveform with respect to the tracking accuracy of given waveform and the flat-top stability of point of observation.As can be seen from Figure 8, the pulse current waveform obtaining by this implementation method and device all has preferably effect with respect to tracking accuracy and the flat-top stability of given waveform.
In sum, a kind of random waveform for the pulse power of the present invention occurs to utilize digital function that MATLAB is powerful to realize the simple and easy able to programme and controllability of the given waveform of arbitrary shape with the implementation method showing and device, and gigabit Ethernet communication based on udp protocol adds data-signal treatment system that DSP adds FPGA architecture and realizes generation and the demonstration of random waveform, utilize FPGA simultaneously, Programmable Technology on the sheets such as DSP, adopt the good high speed serialization SRIO of application prospect technology in digitlization strategy and system level interconnect equipment, not only improve the response time of implement device to any given waveform, realize the real-time that waveform shows, repeatability and easy operating, and improve the tracking accuracy of pulse current waveform for any given waveform, high accuracy and high stability that waveform shows are realized.
Foregoing; it is only preferred embodiment of the present invention; not for limiting embodiment of the present invention; those of ordinary skill in the art are according to main design of the present invention and spirit; can carry out very easily corresponding flexible or amendment, therefore protection scope of the present invention should be as the criterion with the desired protection range of claims.
Claims (10)
1. occur and the implementation method showing for the random waveform of the pulse power, it is characterized in that, comprise the following steps:
Generate the Wave data file of any given waveform;
Read the Wave data in described Wave data file, described Wave data is downloaded and buffer memory generation waveform digital signal;
Described waveform digital signal is carried out to digital-to-analogue conversion and generate waveform modelling signal;
According to pulse power production burst current analog signal described in described waveform modelling signal controlling;
Gather described pulse current analog signal and carry out analog-to-digital conversion, by the pulse current digital signal buffer memory production burst current data after conversion; And
By described pulse current data upload and be shown as pulse current waveform.
2. random waveform according to claim 1 occurs and the implementation method showing, it is characterized in that, described implementation method is further comprising the steps of: described any given waveform and described pulse current waveform are compared, according to comparative result, described Wave data file is revised in real time, to realize the real-time tracking of described pulse current waveform to described any given waveform.
3. random waveform according to claim 1 and 2 occurs and the implementation method showing, it is characterized in that, described described Wave data is downloaded and buffer memory generates waveform digital signal step and comprises the following steps:
Described Wave data is downloaded and buffer memory to the first memory block, and generation first is data cached;
Data cachedly transfer to the second memory block from described the first memory block by described first, and buffer memory generates described waveform digital signal.
4. random waveform according to claim 3 occurs and the implementation method showing, it is characterized in that, described pulse current digital signal buffer memory production burst current data step after conversion is comprised the following steps:
By described pulse current digital signal buffer memory, to described the second memory block, generation second is data cached;
Data cachedly transfer to described the first memory block from described the second memory block by described second, and buffer memory production burst current data.
5. occur and the implement device showing for the random waveform of the pulse power, it is characterized in that, comprise the central control unit, transmission buffer unit and the signal conversion unit that connect successively, wherein,
Described central control unit is for generating the Wave data file of any given waveform, and the Wave data reading is downloaded to described transmission buffer unit from described Wave data file, and the pulse current data of uploading are shown as to pulse current waveform, and described any given waveform and described pulse current waveform are compared, according to comparative result, described Wave data file is revised in real time, to realize the real-time tracking of described pulse current waveform to described any given waveform;
Described transmission buffer unit is used for described Wave data buffer memory to generate waveform digital signal, and transfers to described signal conversion unit, and pulse current digital signal buffer memory is generated to described pulse current data, and transfers to described central control unit; And
Described signal conversion unit is for being converted to described waveform digital signal waveform modelling signal and transferring to the described pulse power, and the pulse current analog signal of described pulse power output is converted to described pulse current digital signal, and transfer to described transmission buffer unit.
6. random waveform according to claim 5 occurs and the implement device showing, it is characterized in that, described central control unit comprises waveform compilation module, waveform transport module, waveform memory area and waveform display module.
7. random waveform according to claim 5 occurs and the implement device showing, it is characterized in that, described transmission buffer unit comprises DSP processing unit and FPGA processing unit.
8. random waveform according to claim 7 occurs and the implement device showing, it is characterized in that, described DSP processing unit comprises a first interface and one first memory block; Described FPGA processing unit comprises one second interface, one second memory block and clock administration module.
9. random waveform according to claim 5 occurs and the implement device showing, it is characterized in that, described signal conversion unit comprises D/A converter module and analog-to-digital conversion module.
10. random waveform according to claim 5 occurs and the implement device showing, it is characterized in that, described implement device also comprises the described pulse power, for generating described pulse current analog signal and transfer to described signal conversion unit according to described waveform modelling signal, the described pulse power is the switching mode pulse power, and the described switching mode pulse power comprises controller, insulated gate bipolar transistor topography module and power supply output module.
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| CN105137401A (en) * | 2015-08-24 | 2015-12-09 | 哈尔滨工程大学 | Fast small-stepping agile frequency conversion radar signal generation device |
| CN105913809A (en) * | 2016-05-30 | 2016-08-31 | 武汉精测电子技术股份有限公司 | Device and method for adjusting backlight brightness of liquid crystal display module |
| CN105913809B (en) * | 2016-05-30 | 2018-08-28 | 武汉精测电子集团股份有限公司 | A kind of device and method of adjustment liquid crystal module group backlight brightness |
| CN109188967A (en) * | 2018-08-31 | 2019-01-11 | 桂林电子科技大学 | A kind of random waveform generating system and Waveform generation method based on network-on-chip |
| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN112731191A (en) * | 2020-12-08 | 2021-04-30 | 北京无线电测量研究所 | Automatic test table for pulse power supply |
| CN114384288A (en) * | 2022-03-22 | 2022-04-22 | 中星联华科技（北京）有限公司 | Signal generating device |
| CN114384288B (en) * | 2022-03-22 | 2022-07-01 | 中星联华科技（北京）有限公司 | Signal generating device |
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