CN104580005A - Method for sending random length message according to flow model accurately - Google Patents
Method for sending random length message according to flow model accurately Download PDFInfo
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Abstract
A method for sending messages with random lengths accurately according to a flow model. The method utilizes a universal PRBS generating circuit and DSP (digital signal processor) hardcore resources in an FPGA (field programmable gate array) to generate a random number in a designated range, uses the random number as the length of a message to be sent, then utilizes two accumulators to calculate in real time with a reciprocal value of a message rate pre-stored in a message rate control FIFO to obtain a message interval corresponding to each message to be sent, and finally outputs a message encapsulation control enabling signal by a message sending controller according to the length of the message to be sent and the requirement of the message interval to realize accurate control of the message sending rate in accordance with the random length under a given flow model. The message sending rate can be accurately controlled to the level of one clock period by applying the method, the realization is simple, the time sequence is easy to converge, and the resource utilization rate is low.
Description
Technical field
The present invention relates to network communication field, particularly relate to a kind of accurately according to given discharge model transmission message, and the message length sent is the method and apparatus of random value.
Background technology
In many data communication systems, as in the systems such as IP exchange, EPON, Ethernet, data throughout, message delay etc. are very important test indexs, and the test of these indexs needs the data model of simulating practical business.Along with the development of the integration of three networks, the business that single network carries gets more and more, and concrete message shows as message length variable at random, message flow meets certain statistical model.Therefore in network test, often use and can generate length of random message, and can test according to the device of particular flow rate model transmission message.
In order to accurately control the transmission rate of message, needing transmission rate as requested and message length, calculating the time interval often sending a message.When message length change at random, the transmission rate of message is also when changing simultaneously, and according to the method being calculated each message interval by software, because software computation rate is lower, and real-time is bad, and the high speed that cannot realize message sends; According to the method for token bucket, the linear speed that can realize message sends, but cannot realize controlling enough accurately message transmitting spped rate.
Summary of the invention
The object of the invention is to solve when sending message length change at random, and message transmitting spped rate is when also changing according to given flow model, be difficult to the problem accurately controlling to send message rate, propose that a kind of FPGA of utilization realizes meeting given flow model and the Ethernet file transmitting method of message length change at random.
Technical scheme of the present invention is:
Accurately send a method for random-length message according to discharge model, the method includes the steps of:
1st, in FPGA, design a random number generator circuit be made up of PRBS maker and DSP stone, be created on the random number in specified scope, by this random number as message length d to be sent; Concrete operation step is as follows:
The PRBS maker of a 16bit is set, generates the pseudo noise code s of 16bit; Suppose that the lower limit of the random number that need produce is a, higher limit is the value that a adds b, be can be calculated the value of message length d to be sent by formula (1);
(1)
Division arithmetic in formula (1) realizes by the method for 16 bits that move to right in FPGA, and multiplying adopts DSP stone resource to realize in FPGA, and the value of the d calculated needs the principle according to rounding up to leave and take its integer part;
2nd, in FPGA, design message rate a controls FIFO, being used for the inverse of the quantity m and packet sending speed v that gives out a contract for a project of each ladder in storage given flow model subtracts the value of 1 again; Concrete operation step is as follows:
The width of described message rate control FIFO is 72 bits, wherein the value of bit 19 to 0 is the fractional part of the inverse of described packet sending speed v, the value of bit 39 to 20 is the value that the integer part of the inverse of described packet sending speed v deducts 1 again, and bit 71 to 40 represents the quantity m that gives out a contract for a project under each flow ladder; The degree of depth of described message rate control FIFO is n, represents the ladder quantity of given flow model;
Value in described message rate control FIFO is calculated before startup message sends by software, and is written in FIFO;
3rd, in FPGA, a message Band Computer be made up of message quantity forwarded counter, message interval decimal place accumulator and message spaced at integer bit accumulator is designed, the value of 1 is subtracted again according to the inverse of described packet sending speed v, and described message length d to be sent, in message process of transmitting, calculate the message interval ifg that this message is corresponding in real time; Concrete operation step is as follows:
The message interval ifg that described message Band Computer exports is calculated by formula (2), the value that wherein inverse of packet sending speed v subtracts 1 again reads and obtains from described message rate control FIFO, and message length d to be sent is the output of described random number generator circuit;
（2）
In order to realize the computing in formula (2) in FPGA, the message interval decimal place accumulator that a bit wide is 20 bits is set, its initial value is 0, when a certain start of heading, sends, described message interval decimal place accumulator adds in 20 clock cycle at ensuing d, Continuous accumulation exports the value of the bit 19 to 0 of data from described message rate control FIFO; The message spaced at integer bit accumulator that a bit wide is 32 bits is set, when a certain start of heading, sends, the initial value arranging this message spaced at integer bit accumulator is 12, add that in 20 clock cycle, on Continuous accumulation, described message rate control FIFO exports the value of the bit 39 to 20 of data at ensuing d, and the value of the overflow position of described message interval decimal place accumulator; Finally the value assignment of described message spaced at integer bit accumulator is given the value of described message interval ifg;
The message quantity forwarded counter that a bit wide is 32bit is set; its initial value is 0; often send this message transmitting counter of message cumulative 1; until when the value of this message quantity forwarded counter is equal with the quantity m that gives out a contract for a project that described message rate control FIFO exports; reset this message quantity forwarded counter, provide once to the read operation of described message rate control FIFO simultaneously;
4th, in FPGA, a message transmit control device is designed, when enable message sends, according to described message length d to be sent and described message interval ifg, often add that ifg adds 8 clock cycle through d, outgoing message encapsulates enable control signal, is used for starting encapsulation and the transmission of Ethernet message data.
Advantage of the present invention and beneficial effect:
The present invention meets the random number in certain limit by the DSP stone resource in FPGA and PRBS circuit evolving, by this random number as message length to be sent, and the message interval of each message is calculated in real time according to given flow model, under efficiently solving length of random message, message transmitting spped rate is difficult to the problem accurately meeting given flow model, the grade of message transmitting spped rate is accurate to clock cycle.
It is simple that method of the present invention has implementation structure, resource utilization is low, the advantage that sequential easily restrains, the xc7k160tfbg676-2 device of xilinx is applied, carry out engineering design with vivado instrument, actual use LUT number is the number of 145, FF is 444, DSP48 resource is 1, BRAM resource is 1.
accompanying drawing illustrates:
Fig. 1 is the structural representation of the length of random message dispensing device of the application embodiment of the present invention;
Fig. 2 is the random number generator circuit diagram of the embodiment of the present invention;
Fig. 3 is the structure chart of the message Band Computer of the embodiment of the present invention;
Fig. 4 is the simulation waveform of the embodiment of the present invention.
Embodiment
below in conjunction with accompanying drawing, and specific embodiment is described further the present invention again.
In conjunction with an example, the performing step sending random-length Ethernet message according to given flow model is described, be illustrated in figure 1 application apparatus structure schematic diagram of the present invention: this device comprises: random number generator, message rate control FIFO, message Band Computer and message transmit control device, described random number generator is connected with message transmit control device and message Band Computer respectively, and message rate control FIFO is connected with message transmit control device by message Band Computer.
First, the inverse of the message quantity forwarded m and message transmitting spped rate v that store each flow ladder in message rate control FIFO 103 deducts the value of 1, and this value is calculated before startup message sends by upper layer software (applications), from the message length d to be sent that random number generator 101 exports, deliver in message Band Computer 104 and message transmit control device 102 simultaneously, often send a message, notify that message Band Computer 104 calculates corresponding message interval ifg by message transmit control device 102 by latch_en signal, preferably, in the present embodiment, latch_en is designed to the pulse signal of a clock cycle, message transmit control device 102 is again according to the value of message length d to be sent and message interval ifg, produce and be used for starting the control signal fram_en of message encapsulation and the length fram_length of message to be packaged, preferably, in the present embodiment, fram_en is designed to the pulse signal of a clock cycle, fram_length is designed to 16 bit bit wides.
Method of the present invention comprises:
step1, Figure 2 shows that the random number generator circuit diagram (device 200) of the embodiment of the present invention, the exportable message length d to be sent of this device 200, specific implementation step is as follows:
Device 201 is 16 pseudo random number generative circuits, exports 16 the pseudo noise code s generated; The device 202 DSP stone resource called in FPGA realizes multiplication and the add operation of formula (1), numerical value a and b is arranged by upper layer software (applications) or user, be used for limiting the scope of described message length d to be sent, in the present embodiment, suppose that the value of a is 64, the value of b is 20, then the scope of message length d to be sent is less than or equal to 84 for being more than or equal to 64; Division arithmetic in formula (1) is realized by 16 bits that moved to right by operation result; Device 203 exports the highest order of the decimal place of data according to device 202, the selector controlling an alternative realizes the carry algorithm rounded up;
step 2, the message rate control FIFO 103 that describes in Fig. 1, be used for the inverse of give out a contract for a project quantity and the packet sending speed v that store each ladder deduct again 1 value; Concrete operation step is as follows:
The width of described message rate control FIFO is 72 bits, wherein the value of bit 19 to 0 is the fractional part of the inverse of message transmitting spped rate v, the value of bit 39 to 20 is the value that the integer part of the inverse of message transmitting spped rate v deducts 1, and bit 71 to 40 represents the message number needing to send under certain message transmitting spped rate; Such as in the present embodiment, message sends 5 messages with the speed of 80%, then sends 3 messages with the speed of 40%, then two numbers stored in device 103 i.e. message rate control FIFO are respectively 0x50000040000 and 0x30000180000.
Preferably, the numerical value in described message rate control FIFO is calculated before startup message sends by upper layer software (applications), and is written in FIFO;
step 3, a message Band Computer is set, deduct the value of 1 again according to the inverse of described message transmitting spped rate v, and described message length d to be sent, utilize two accumulators in message process of transmitting, calculate message interval ifg corresponding to each message; Concrete operation step is as follows:
Be illustrated in figure 3 the structure chart (device 300) of the message Band Computer of the embodiment of the present invention, the wherein decimal place accumulator of 301 to be a bit wide be 20 bits, initial value is 0, its input vl is the value of the bit 19 to 0 from described message rate control FIFO output, its output is the Overflow flag cin of 1 bit, after the latch_en signal exported by message transmit control device 102 is effective, decimal place accumulator 301 can carry out continuous d to vl signal and add the cumulative of 20 clock cycle;
302 is a bit wide is the integer-bit accumulator of 32 bits, its input vh is the value of the bit 39 to 20 from described message rate control FIFO output, it exports the message interval to be sent that ifg is 32 bit bit wides, when the latch_en signal exported by message transmit control device 102 is effective, integer-bit accumulator 302 initialize is 12, add in 20 clock cycle at ensuing d, integer-bit accumulator 302 pairs of vh and cin signals add up, and the value after this is cumulative is exactly the value needing the ifg exported;
303 is the Read Controller of described message rate control FIFO, its input m is the value of the bit 71 to 40 that described message rate control FIFO exports, when latch_en signal is effective, the number of frames counter of sending out of FIFO Read Controller 303 inside increases by 1, when the value of described number of frames counter is equal with m, produced once to the read operation of described message rate control FIFO by rd_en signal, a described number of frames counter assignment is 0 simultaneously;
Step 4, a message transmit control device is set, when enable message sends, according to described message length d to be sent and described message interval ifg, often add that ifg adds 8 clock cycle through d, outgoing message encapsulates enable control signal latch_en and corresponding message length fram_length, is used for starting encapsulation and the transmission of Ethernet message data.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
In order to further illustrate the availability of the embodiment of the present invention, be illustrated in figure 4 the simulation waveform of the embodiment of the present invention, the value wherein arranging a is 64, the value of b is 20, prbs_out signal is pseudo noise code s, the random number that then circuit for generating random number generates is less than or equal in the scope of 84 being more than or equal to 64, after the control signal tx_en starting message transmission becomes high level, first send 5 messages with the message transmitting spped rate of 80%, 3 messages are sent again with the message transmitting spped rate of 40%, the value of these 7 message length d is respectively 79, 81, 70, 68, 73, 82, 74, 73, 74, the value of message interval ifg is corresponding thereto respectively 36, 38, 34, 34, 35, 165, 153, 152, 153, from this simulation result, when achieving message length d change at random, to the accurate control of message transmitting spped rate.
Claims (4)
1. accurately send a method for random-length message according to discharge model, it is characterized in that, the method includes the steps of:
1st, in FPGA, design a random number generator circuit be made up of PRBS maker and DSP stone, be created on the random number in specified scope, by this random number as message length d to be sent;
2nd, in FPGA, design message rate a controls FIFO, being used for the inverse of the quantity m and packet sending speed v that gives out a contract for a project of each ladder in storage given flow model subtracts the value of 1 again;
3rd, in FPGA, a message Band Computer be made up of message quantity forwarded counter, message interval decimal place accumulator and message spaced at integer bit accumulator is designed, the value of 1 is subtracted again according to the inverse of described packet sending speed v, and described message length d to be sent, in message process of transmitting, calculate the message interval ifg that this message is corresponding in real time;
4th, in FPGA, a message transmit control device is designed, when enable message sends, according to described message length d to be sent and described message interval ifg, often add that ifg adds 8 clock cycle through d, outgoing message encapsulates enable control signal, is used for starting encapsulation and the transmission of Ethernet message data.
2. method according to claim 1, is characterized in that, the concrete steps designing a random number generator described in the 1st step are as follows:
First design the PRBS maker of a 16bit, generate the pseudo noise code s of 16bit; Suppose that the lower limit of the random number that need produce is a, higher limit is the value that a adds b, then be can be calculated the value of message length d to be sent by formula (1);
(1)
Division arithmetic in formula (1) adopts the method for the 16bit that moves to right to realize in FPGA, and multiplying adopts DSP stone resource to realize in FPGA, and the value calculating d needs the principle according to rounding up to leave and take its integer part.
3. method according to claim 1, is characterized in that, the concrete steps designing a message rate control FIFO described in the 2nd step are as follows:
The width of described message rate control FIFO is 72 bits, wherein the value of bit 19 to 0 is the fractional part of the inverse of described packet sending speed v, the value of bit 39 to 20 is the value that the integer part of the inverse of described packet sending speed v deducts 1 again, and bit 71 to 40 represents the quantity m that gives out a contract for a project under each flow ladder; The degree of depth of described message rate control FIFO is n, represents the ladder quantity of given flow model;
Value in described message rate control FIFO is calculated before startup message sends by software, and is written in this FIFO.
4. method according to claim 1, is characterized in that, the concrete steps designing a message Band Computer described in the 3rd step are as follows:
The message interval ifg that described message Band Computer exports is calculated by formula (2), the value that wherein inverse of packet sending speed v subtracts 1 again reads and obtains from described message rate control FIFO, and message length d to be sent is the output of described random number generator circuit;
（2）
In order to realize the computing in formula (2) in FPGA, the message interval decimal place accumulator that a bit wide is 20 bits is set, its initial value is 0, when a certain start of heading, sends, described message interval decimal place accumulator adds in 20 clock cycle at ensuing d, Continuous accumulation exports the value of the bit 19 to 0 of data from described message rate control FIFO; The message spaced at integer bit accumulator that a bit wide is 32 bits is set, when a certain start of heading, sends, the initial value arranging this message spaced at integer bit accumulator is 12, add that in 20 clock cycle, on Continuous accumulation, described message rate control FIFO exports the value of the bit 39 to 20 of data at ensuing d, and the value of the overflow position of described message interval decimal place accumulator; Finally the value assignment of described message spaced at integer bit accumulator is given the value of described message interval ifg;
The message quantity forwarded counter that a bit wide is 32bit is set, its initial value is 0, often send this message transmitting counter of message cumulative 1, until when the value of this message quantity forwarded counter is equal with the quantity m that gives out a contract for a project that described message rate control FIFO exports, reset this message quantity forwarded counter, provide once to the read operation of described message rate control FIFO simultaneously.
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| CN110290020A (en) * | 2019-06-17 | 2019-09-27 | 北京挚友科技有限公司 | A kind of ethernet test instrument high-precision flow percentage production method and device |
| CN111654886A (en) * | 2020-05-27 | 2020-09-11 | 杭州迪普科技股份有限公司 | Method and device for limiting user bandwidth |
| CN111865498A (en) * | 2020-07-29 | 2020-10-30 | 北京中科网维科技有限公司 | 100G OTN payload flow rate generation method and device |
| WO2022062758A1 (en) * | 2020-09-25 | 2022-03-31 | 中兴通讯股份有限公司 | Incentive message sending method and apparatus, electronic device, and storage medium |
| CN114679411A (en) * | 2022-03-24 | 2022-06-28 | 芯河半导体科技(无锡)有限公司 | Method for implementing rate-controllable Ethernet message packet sender |
| CN115309676A (en) * | 2022-10-12 | 2022-11-08 | 浪潮电子信息产业股份有限公司 | Asynchronous FIFO read-write control method, system and electronic equipment |
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Application publication date: 20150429 |