CN102999311A - 48*30 bit multiplier based on Booth algorithm - Google Patents
48*30 bit multiplier based on Booth algorithm Download PDFInfo
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- CN102999311A CN102999311A CN2012105276574A CN201210527657A CN102999311A CN 102999311 A CN102999311 A CN 102999311A CN 2012105276574 A CN2012105276574 A CN 2012105276574A CN 201210527657 A CN201210527657 A CN 201210527657A CN 102999311 A CN102999311 A CN 102999311A
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Abstract
The invention discloses a 48*30 bit multiplier based on a Booth algorithm. The multiplier comprises a Bit displacement control mode, a partial product generator, a linear accumulation controller and a partial product linear accumulator. According to the invention, partial products are firstly generated by the multiplier and then accumulated and summed to realize the multiplying operation of 48*30 bits, wherein the partial products are generated by using a Radix-4Booth algorithm and are processed in a linear summing manner, so that the number of the partial products to be summed is reduced greatly. Therefore, a clock period required for realization of the multiplying operation is shortened, and the algorithms of multiplication with symbolic numbers and without symbolic numbers are unified. As a result, the traditional serial multiplier and the traditional parallel multiplier for processing the consumption of bandwidth and hardware resources are compromised. Consequently, the hardware resource consumption in design is lowered greatly and the cost is saved obviously on the basis that the multiplier with a high bit width satisfies the requirement of the bandwidth speed of system design.
Description
Technical field
The present invention relates to the multiplier the pipeline design in a kind of high speed, the high capacity communication technical field, relate in particular to a kind of 48x30 position multiplier based on the Booth algorithm.
Background technology
Along with the fast development of the 3G communication technology, TD-SCDMA technology (being called for short the TD technology) also is used widely.At present, each communication base station of TD technical requirement and application network element thereof are realized high precision clock, time synchronized.NTP technology in the past can't satisfy the demand of precise synchronization, adopts high precision clock, time synchronization protocol thereby turn to, and such as the IEEE1588 agreement, realizes the time accurate synchronization of each network node in the TD system.
In the IEEE1588 agreement, its standard time form is the time counter of 80bits.High 48bits is part second that is expressed as the time, and low 32bits is expressed as the nanosecond part of time.But in the hardware handles circuit, when the time of this IEEE1588 consensus standard is processed, often need to process the time carry second, the problem such as overflow.This will use multiplier, and mainly use two kinds of implementations at present: serial multiplier and parallel multiplier.
Serial multiplier, the i.e. algorithm of technical employing shifter-adder.The remarkable shortcoming of this implementation is to do once displacement and additive operation each clock period, as depicted in figs. 1 and 2, a 48x30 bit serial multiplier will be finished the multiplying of 48x30 position needs 30 just can finish one time computation period more than the clock period at least, although the hardware that it consumes is less, it is lower that it processes bandwidth.
Parallel multiplier, i.e. the computing method that technical employing is directly multiplied each other.This implementation is to finish all displacements and additive operation by the iteration of combinational circuit is disposable, from Fig. 3 and Fig. 4, can find out, the multiplying of finishing like this a 48x30 position only needs 1 clock period just can finish computation period one time, and it is the highest to process bandwidth.But its shortcoming is that the hardware that consumes is more, cost is high.
Therefore, how computing bandwidth and hardware resource consumption being done one and take into account balance optimizing to realize processing a balance of bandwidth and hardware consumption, is the technical matters that needs to be resolved hurrily at present.
Summary of the invention
The object of the present invention is to provide a kind of 48x30 position multiplier based on the Booth algorithm, take into account to realize the balance of processing bandwidth and hardware consumption.
For achieving the above object, the invention provides a kind of 48x30 position multiplier based on the Booth algorithm, comprising:
Bit bit shift control module is used for carrying out multiplication control indicator when effective when detecting to start, and receives the input of 30bit position multiplier B, and control 30bit position multiplier B is shifted by bit from low to high at each computation period;
The partial product maker be used for to receive the state value of one group of 3 bit position of the described multiplier B that the input of 48bit position multiplicand A and described bit bit shift control module send here at each described computation period; Generate a partial product according to the Radix-4Booth algorithm and in conjunction with the state value of one group of 3 bit position of the current multiplicand A that receives and described multiplier B;
The flowing water controller that adds up is used under the driving of described bit bit shift control module, and the long-pending streamline totalizer of control section is done an additive operation to partial product in each computation period;
Partial product streamline totalizer is used under the control of the cumulative controller of described flowing water every group of partial product that described partial product maker is brought being done accumulating operation; After finishing all partial product calculating processes, export operation result, and finish Warning Mark by the cumulative controller output of described flowing water computing.
48x30 position multiplier based on the Booth algorithm of the present invention is that first generating portion is long-pending, again partial product is added up to sue for peace and realize the computing of 48x30 position multiplication, carry out the partial product number that the flowing water additive operation can significantly reduce needs summation owing to utilize Radix-4Booth algorithm generating portion to amass, thereby shortened the needed clock period of realization multiplying, the algorithm that also signed number and unsigned number is multiplied each other has simultaneously been realized unification.This shows, it is a kind of the trading off on processing bandwidth and hardware resource consumption to conventional serial multiplier and parallel multiplier, thereby can make the multiplier of high-bit width on the basis of satisfying our system bandwidth speed demand, greatly reduce the hardware resource consumption in the design, significantly save cost.
Description of drawings
Fig. 1 is the resource consumption situation synoptic diagram based on Altera Quartus analysis tool of existing serial multiplier;
Fig. 2 is the temporal characteristics synoptic diagram based on software emulation of existing serial multiplier;
Fig. 3 is the resource consumption situation synoptic diagram based on Altera Quartus analysis tool of existing parallel multiplier;
Fig. 4 is the temporal characteristics synoptic diagram based on software emulation of existing parallel multiplier;
Fig. 5 is the configuration diagram of the 48x30 position multiplier based on the Booth algorithm of the present invention;
Fig. 6 is the resource consumption situation synoptic diagram based on Altera Quartus analysis tool of the 48x30 position multiplier based on the Booth algorithm of the present invention;
Fig. 7 is the temporal characteristics synoptic diagram based on software emulation of the 48x30 position multiplier based on the Booth algorithm of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail:
The main design idea based on the 48x30 position multiplier of Booth algorithm of present embodiment is to utilize Radix-4Booth algorithm generating portion long-pending and partial product carried out the flowing water additive operation, the generation of partial product is only determined by multiplier, can obtain an arbitrarily partial product according to the Booth algorithm, reasonably select the number of partial product generative circuit, to improve the performance of multiplier, its cost is exactly partial product generative circuit and the adder circuits of increasing more.
With reference to shown in Figure 5, the 48x30 position multiplier based on the Booth algorithm of present embodiment comprises Bit bit shift control module, partial product maker, the cumulative controller of flowing water and partial product streamline totalizer.Wherein:
Bit bit shift control module is used for carrying out multiplication control indicator when effective when detecting to start, and receives the input of 30bit position multiplier B, and control 30bit position multiplier B is shifted by bit from low to high at each computation period.Such as first computation period that is beginning to calculate, the-the 1bit(that gets multiplier B is for the first time more special, but in fact do not have-1bit, according to algorithm here-the 1bit value just is designated as 0), 0bit, 1bit, tell the partial product maker with the state value of these 3 bit.When second computation period arrives, get 1bit, 2bit, the 3bit of multiplier B, and also tell the partial product maker with the state value of these 3 bit.The rest may be inferred, until the 15 computation period when arriving, got 27bit, 28bit, the 29bit of multiplier B, and also told the partial product maker with the state value of these 3 bit.
The partial product maker be used for to receive the state value of one group of 3 bit position of the multiplier B that the input of 48bit position multiplicand A and bit bit shift control module send here at each computation period; Generate a partial product according to the Radix-4Booth algorithm and in conjunction with the state value of one group of 3 bit position of the current multiplicand A that receives and multiplier B.
The cumulative controller of flowing water is used under the driving of bit bit shift control module, and the long-pending streamline totalizer of control section is done an additive operation to partial product in each computation period;
Partial product streamline totalizer is used under the control of the cumulative controller of flowing water every group of partial product that the partial product maker is brought being done accumulating operation; After finishing all partial product calculating processes, export operation result, and finish Warning Mark by the cumulative controller output of flowing water computing.Wherein the one-accumulate calculating process of partial product streamline totalizer is: the initial value that at first will be kept in the accumulation result buffer of partial product streamline totalizer takes out, then initial value and this current partial product of being sent here by the partial product maker add up, at last current accumulation result is transmitted back to the accumulation result buffer and preserves, use in order to next computation period.
In conjunction with shown in Figure 6, can find out, the relatively existing serial adder in hardware logic unit based on the 48x30 position multiplier consumption of Booth algorithm of present embodiment increases to some extent, but in contrast to parallel multiplier, the hardware logic resource quantity of its consumption greatly reduces, thereby has significantly reduced design cost.And in conjunction with shown in Figure 7, the simulation result from figure can find out that finishing a 48x30 position multiplication calculates, and only needs 15 clock period, and its time-delay will reduce half with respect to existing serial multiplier.Therefore, the 48x30 position multiplier based on the Booth algorithm of present embodiment can have been finished symbol or without symbol 48x30 position multiplying, after multiplicand process sign extended, use the Booth algorithm coding of Radix-4 can significantly reduce the partial product number that needs summation, thereby shortened the needed computation period of realization multiplying, the algorithm that also signed number and unsigned number is multiplied each other has simultaneously been realized unification.
Above embodiment is described preferred implementation of the present invention; be not that scope of the present invention is limited; design under the prerequisite of spirit not breaking away from the present invention; various distortion and improvement that the common engineering technical personnel in this area make technical scheme of the present invention; such as the Radix-4Booth algorithm being replaced with Radix-8Booth algorithm or Radix-16Booth algorithm etc., all should fall in the definite protection domain of claims of the present invention.
Claims (3)
1. the 48x30 position multiplier based on the Booth algorithm is characterized in that, comprising:
Bit bit shift control module is used for carrying out multiplication control indicator when effective when detecting to start, and receives the input of 30bit position multiplier B, and control 30bit position multiplier B is shifted by bit from low to high at each computation period;
The partial product maker be used for to receive the state value of one group of 3 bit position of the described multiplier B that the input of 48bit position multiplicand A and described bit bit shift control module send here at each described computation period; Generate a partial product according to the Radix-4Booth algorithm and in conjunction with the state value of one group of 3 bit position of the current multiplicand A that receives and described multiplier B;
The flowing water controller that adds up is used under the driving of described bit bit shift control module, and the long-pending streamline totalizer of control section is done an additive operation to partial product in each computation period;
Partial product streamline totalizer is used under the control of the cumulative controller of described flowing water every group of partial product that described partial product maker is brought being done accumulating operation; After finishing all partial product calculating processes, export operation result, and finish Warning Mark by the cumulative controller output of described flowing water computing.
2. the 48x30 position multiplier based on the Booth algorithm according to claim 1 is characterized in that the one-accumulate calculating process of described partial product streamline totalizer is as follows:
The initial value that at first will be kept in the accumulation result buffer of described partial product streamline totalizer takes out, then described initial value and this current partial product of being sent here by described partial product maker add up, at last current accumulation result is transmitted back to described accumulation result buffer and preserves, use in order to next computation period.
3. the 48x30 position multiplier based on the Booth algorithm according to claim 2 is characterized in that described Radix-4Booth algorithm replaces with Radix-8Booth algorithm or Radix-16Booth algorithm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104572012A (en) * | 2015-01-29 | 2015-04-29 | 东南大学 | Polynomial-based GF [2(227)] high-speed modular multiplier based on AOP (all one polynomial) |
| CN109753268A (en) * | 2017-11-08 | 2019-05-14 | 北京思朗科技有限责任公司 | More granularity concurrent operation multipliers |
| CN110046404A (en) * | 2019-03-28 | 2019-07-23 | 宝鸡文理学院 | A kind of IP core design method based on pid algorithm |
| CN110597486A (en) * | 2019-08-27 | 2019-12-20 | 中山大学 | Method and system for realizing scalable multiplication by utilizing function callback |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6434587B1 (en) * | 1999-06-14 | 2002-08-13 | Intel Corporation | Fast 16-B early termination implementation for 32-B multiply-accumulate unit |
| US6463453B1 (en) * | 1998-01-12 | 2002-10-08 | Motorola, Inc. | Low power pipelined multiply/accumulator with modified booth's recoder |
| CN101122850A (en) * | 2007-09-21 | 2008-02-13 | 清华大学 | Large number multiplier based on secondary Booth coding |
| CN102662624A (en) * | 2012-04-13 | 2012-09-12 | 钜泉光电科技(上海)股份有限公司 | Multiplying unit |
| CN102722352A (en) * | 2012-05-21 | 2012-10-10 | 华南理工大学 | Booth multiplier |
-
2012
- 2012-12-10 CN CN2012105276574A patent/CN102999311A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6463453B1 (en) * | 1998-01-12 | 2002-10-08 | Motorola, Inc. | Low power pipelined multiply/accumulator with modified booth's recoder |
| US6434587B1 (en) * | 1999-06-14 | 2002-08-13 | Intel Corporation | Fast 16-B early termination implementation for 32-B multiply-accumulate unit |
| CN101122850A (en) * | 2007-09-21 | 2008-02-13 | 清华大学 | Large number multiplier based on secondary Booth coding |
| CN102662624A (en) * | 2012-04-13 | 2012-09-12 | 钜泉光电科技(上海)股份有限公司 | Multiplying unit |
| CN102722352A (en) * | 2012-05-21 | 2012-10-10 | 华南理工大学 | Booth multiplier |
Non-Patent Citations (1)
| Title |
|---|
| 李娜: "FT_C55LPDSP中位处理单元与双乘累加单元的设计与实现", 《中国优秀硕士学位论文全文数据库（信息科技辑）》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104572012A (en) * | 2015-01-29 | 2015-04-29 | 东南大学 | Polynomial-based GF [2(227)] high-speed modular multiplier based on AOP (all one polynomial) |
| CN109753268A (en) * | 2017-11-08 | 2019-05-14 | 北京思朗科技有限责任公司 | More granularity concurrent operation multipliers |
| CN109753268B (en) * | 2017-11-08 | 2021-02-02 | 北京思朗科技有限责任公司 | Multi-granularity parallel operation multiplier |
| CN110046404A (en) * | 2019-03-28 | 2019-07-23 | 宝鸡文理学院 | A kind of IP core design method based on pid algorithm |
| CN110597486A (en) * | 2019-08-27 | 2019-12-20 | 中山大学 | Method and system for realizing scalable multiplication by utilizing function callback |
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Application publication date: 20130327 |