CN203457135U

CN203457135U - Gray code counter device

Info

Publication number: CN203457135U
Application number: CN201320442627.3U
Authority: CN
Inventors: 李林; 仲亚东
Original assignee: HWA CREATE SHANGHAI CO Ltd
Current assignee: Beijing HWA Create Co Ltd
Priority date: 2013-07-24
Filing date: 2013-07-24
Publication date: 2014-02-26
Anticipated expiration: 2023-07-24

Abstract

The utility model discloses a Gray code counter device. The device at least comprises an accumulator and a counter. The accumulator is achieved by use of a combined circuit and the type of coding is the Gray coding; the counter is achieved by use of a register sequential circuits the accumulator is connected with the counter; the counter will output feedback to input of the accumulator; and the accumulator performs accumulating processing for present values of the counter and then outputs the processed results to the counter for preservation. Therefore, there is no need of interchanging between a binary system and the Gray code, and problems of long time delay and complex structures in the prior art are resolved.

Description

Gray count apparatus

[technical field]

The utility model relates to a kind of gray count apparatus, particularly refers to use combinational circuit Gray code accumulator and sequence circuit register to realize the device of synchronised clock counter.

[background technology]

Existing counter is the adder based on binary field, and one of them addend is fixed as 1, doing cumulative realization, and normally used implementation method is ripple adder by turn, or carry lookahead adder.They have some restrictions in realization, or sequential restriction and bit wide be directly proportional, or hardware resource and bit wide linear.

Many times, the output valve of counter also needs to do cross clock domain transmission.This just need to first be converted to Gray code binary system, could remove metastable state by two groups of registers realize cross clock domain with register after latching.This has increased again hardware resource and time delay response greatly.

Refer to shown in Fig. 1, for traditional solution application drawing, wherein because Gray code is better in the data transmission stability of cross clock domain, when so in Fig. 1, leftmost accumulator uses conventional binary coding, need first by binary system, to gray code converter, to be converted to Gray code, then deliver to gray code registers, prepare to be delivered to second clock territory from the first clock cross clock domain; In second clock territory, after synchronously obtaining stationary value by two-stage and be stored in the second register, at this time still Gray code, must to binary system (cary_to_binaray) transducer, be converted to conventional binary coding and be stored in binary register by Gray code, just can send into the threshold values (threshold) of setting in comparator (comparor) and threshold registers and compare, obtain flag bit (flag) and be stored in flag register.The weak point of this kind of mode has: it needs the mutual conversion between Gray code and binary system, complex structure, and hardware configuration is difficult for realizing, and is unfavorable for reducing hardware resource and time delay response.

[utility model content]

The purpose of this utility model is to provide a kind of gray count apparatus, in order to solve the binary counter of prior art, needs the exchange of binary system and Gray code to introduce larger time delay and baroque problem.

For achieving the above object, implement gray count apparatus of the present utility model and at least comprise accumulator sum counter, wherein accumulator is to use combinational circuit to realize, its type of coding is Gray code, and counter is to use register sequence circuit to realize, accumulator is connected in counter, and counter can feed back the input that outputs to accumulator, accumulator exports the value of current counter to counter and preserves after accumulation process is made in Gray code territory by result, and gray count apparatus also comprises first and second register of serial connection, the first register is connected with counter, this first and second register work clock is second clock, this secondary register is all to adopt register sequence circuit to realize.

According to above-mentioned principal character, the bit wide of accumulator is Parametric Definition.

According to above-mentioned principal character, counter works clock is the first clock.

Compared with prior art, implement gray count apparatus of the present utility model and only use generic logic hardware can realize the accumulated counts in Gray code territory, do not need Gray code and binary mutual conversion; And accumulator is to realize by pure combinational circuit, hardware configuration is easy to realize; Hard-wired sequential restriction and hardware resource are to be all logarithmic relationship with bit wide, increase slower; And need not do the exchange of binary system and Gray code, reduced hardware resource and time delay response; Meanwhile, bit wide can parameter-definition, has increased flexibility, and therefore output is the binary number that Gray code represents, and in strict accordance with the output of synchronous working clock, can meet the needs of embedded system complicated applications.

[accompanying drawing explanation]

Fig. 1 is for implementing the application schematic diagram of conventional counter device.

Fig. 2 is for implementing the hardware principle schematic diagram of the utility model gray count apparatus.

Fig. 3 is for implementing the application schematic diagram of the specific embodiment of the utility model gray count apparatus.

[embodiment]

Refer to shown in Fig. 2, for implementing the hardware principle schematic diagram of the utility model gray count apparatus, wherein this gray count apparatus comprises an accumulator and counter, wherein accumulator is to use combinational circuit to realize, its type of coding is Gray code, and its data width is parametrization, can be self-defining.And counter is to use register sequence circuit to realize, its work clock is the first clock, is 32KHz in the present embodiment.Wherein accumulator is connected in counter, and counter can feed back the input that outputs to accumulator, and accumulator exports the value of current counter to counter and preserves after accumulation process is made in Gray code territory by result.

In addition, implement first and second register that gray count apparatus of the present utility model also comprises serial connection, the first register is connected with counter, this first and second register work clock is second clock, be 48MHz in the present embodiment, because the first clock is different from second clock, so in cross clock domain synchronous, need to use first and second two-stage register to carry out synchronously, and this secondary register is all to adopt register sequence circuit to realize.

The transmittance process from the first clock to second clock, between counter and first, second register, it must be direct electrical connection, can not add combinational circuit, the value in the second register finally obtaining is the stable register in second clock territory again, and its type of coding is Gray code.

Refer to shown in Fig. 3, for implementing the application schematic diagram of the specific embodiment of the utility model gray count apparatus, compare with the conventional binary coding shown in Fig. 1, this scheme has not only been removed binary system to gray code converter (binary_to_gray) and Gray code to binary translator (cary_to_binary) combined circuit module, and having reduced Gray code to the binary register between binary translator and comparator, performance can be better.

From above-mentioned narration, implement the functional modules such as the included Gray code accumulator of the utility model gray count apparatus and register, not only save hardware resource, sequential restriction is also looser, and after having reduced one group of sequential register (being the binary register shown in Fig. 1), performance also promotes to some extent.Particularly, after hardware structure has designed, can also by parameter, reconfigure accumulator bit wide for different application scenarios, obtain different products, thereby more can meet the elastic demand of design.

Be understandable that; for those of ordinary skills; can be equal to replacement or change according to the technical solution of the utility model and utility model design thereof, and all these changes or replacement all should belong to the protection range of the appended claim of the utility model.

Claims

1. a gray count apparatus, at least comprise accumulator sum counter, it is characterized in that: accumulator is to use combinational circuit to realize, its type of coding is Gray code, and counter is to use register sequence circuit to realize, accumulator is connected in counter, and counter can feed back the input that outputs to accumulator, accumulator exports the value of current counter to counter and preserves after accumulation process is made in Gray code territory by result, and this gray count apparatus also comprises first and second register of serial connection, the first register is connected with counter, this first and second register work clock is second clock, this secondary register is all to adopt register sequence circuit to realize.

2. gray count apparatus as claimed in claim 1, is characterized in that: the bit wide of accumulator is Parametric Definition.

3. gray count apparatus as claimed in claim 1, is characterized in that: counter works clock is the first clock.