CN103699729A - Modulus multiplier - Google Patents

Abstract

The invention discloses a modulus multiplier, in particular a modulus (2<n>+2<p>-1) multiplier. The modulus (2<n>+2<p>-1) multiplier comprises an (n+1)-digit binary adder, a CSA (carry save adder) tree compressor array, an (n+2)-digit binary adder and a modulus (2<n>+2<p>-1) adder. According to the modulus (2<n>+2<p>-1) multiplier, a binary multiplication result serves as an operation number P for reprocessing, so that repeated correction of the conventional modulus (2<n>+2<p>-1) multiplier is changed into primary correction, the resource consumption of the modulus (2<n>+2<p>-1) multiplier is reduced, required operation can be completed in a clock period, and the modulus (2<n>+2<p>-1) multiplier is simple, high in speed and high in efficiency.

Description

Mode multiplier

Technical field

The invention belongs to computing machine and integrated circuit fields, be specifically related to a kind of design of high-speed multiplier.

Background technology

Before introducing multiplier, first residue number system (RNS, Residue Number Systems) is done to an explanation.Residue number system RNS be a kind of by one group between two the remainder of relatively prime remainder base digital numerical representation method system is described, by { m ₁, m ₂..., m _ll remainder base forming, integer X, 0≤X<M, wherein M=m ₁* m ₂* ... * m _l, in RNS system, having unique expression mode is X={x ₁, x ₂..., x _l,

wherein,

represent that X is for mould m _iremainder.In residue number system, two operands operate, and operational character is Θ, can be defined as:

{ z ₁, z ₂..., z _l}={ x ₁, x ₂..., x _lΘ { y ₁, y ₂..., y _l, wherein

here, Θ can be modulo addition, mould subtraction or mould multiplication.In residue number system, these arithmetical operations are all executed in parallel, and processing is all very little remainder rather than a very large number.Mould (2 ⁿ+ 2 ^p-1) for the dynamic range of expansion residue number system, and the balance between each arithmetic channel has very important meaning, and multiplier is as the main arithmetic element of arithmetic channel, therefore for mould (2 ⁿ+ 2 ^p-1) research of multiplier is very significant.

Existing mould (2 ⁿ+ 2 ^p-1) multiplier, generally still adopts traditional Booth coding+Wallace(to comprise correction circuit) structure of+mould adder (comprising correction circuit), this mould (2 ⁿ+ 2 ^p-1) multiplier is revised owing to having used repeatedly, especially correction repeatedly in Wallace.Be specially: existing mould (2 ⁿ+ 2 ^p-1) multiplier adopts Booth coding structure, can produce

individual partial product, and

individual partial product need to be carried out delivery (2 ⁿ+ 2 ^p-1) correcting process, thus the quantity of the partial product making further increases, at Wallace and mould (2 ⁿ+ 2 ^p-1) in totalizer same exist repeatedly to mould (2 ⁿ+ 2 ^p-1) processing.Thereby existing mould (2 ⁿ+ 2 ^p-1) multiplier consumes resources is very many, has also caused accordingly arithmetic speed very low.

Summary of the invention

The object of the invention is in order to solve existing towards mould (2 ⁿ+ 2 ^p-1) multiplier consumes resources, the problem that speed is lower, has proposed a kind of mould (2 ⁿ+ 2 ^p-1) multiplier.

Technical scheme of the present invention is: a kind of mould (2 ⁿ+ 2 ^p-1) multiplier, comprising: (n+1) position binary multiplier, CSA(Carry Save Adder) tree compressor reducer array, (n+2) position binary adder, mould (2 ⁿ+ 2 ^p-1) totalizer.

If A and B are described mould (2 ⁿ+ 2 ^p-1) input of multiplier, total (n+1) position, is respectively [n:0], and Y is described mould (2 ⁿ+ 2 ^p-1) output of multiplier, total (n+1) position, be [n:0], wherein, A[u:v], B[u:v] and Y[u:v] representing that respectively the v position of A, B and Y is to the number of u position correspondence, concrete annexation is as follows:

Two input ends of described (n+1) position binary multiplier are respectively used to input described mould (2 ⁿ+ 2 ^p-1) input A and B for two of multiplier, described n position binary multiplier is output as P, and wherein, P is 2n+2 position, is specially [2n+1:0];

Six input ends of described CSA tree compressor reducer array are respectively used to the combination P[n-1:0 of corresponding bit data of the output P of input described (n+1) position binary multiplier], P[2n-1:n],

(2 ⁿ-2 ^p+2-2 ^p+1-1), wherein, # is junction symbol,

represent the anti-of P, two output terminals of described CSA tree compressor reducer array are respectively: present bit output L[n+1:0], carry output H[n+1:0];

Two addend input ends of described (n+2) position binary adder are respectively used to input L[n+1:0] and H[n+1:0], described (n+2) position binary adder with carry input is output as T[n+2:0];

Described mould (2 ⁿ+ 2 ^p-1) two of totalizer input ports are respectively used to the output T[n+2:0 of input described (n+2) position binary adder] corresponding position T[n-1:0] and the combination of corresponding

described mould (2 ⁿ+ 2 ^p-1) the output of totalizer be described mould (2 ⁿ+ 2 ^p-1) the output Y of multiplier.

Beneficial effect of the present invention: mould (2 of the present invention ⁿ+ 2 ^p-1) multiplier adopts the result of binary multiplication to process as operand P again, thereby traditional mould (2 ⁿ+ 2 ^p-1) the repeatedly correction of multiplier changes into once and revising, and can within a clock period, complete required computing, has reduced mould (2 ⁿ+ 2 ^p-1) consumes resources of multiplier, has improved its arithmetic speed.

Accompanying drawing explanation

Fig. 1 is mould (2 of the present invention ⁿ+ 2 ^p-1) multiplier architecture schematic diagram.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment, the invention will be further elaborated.

Mould (2 of the present invention ⁿ+ 2 ^p-1) as shown in Figure 1, wherein, 1 is (n+1) position binary multiplier to multiplier architecture, and 2 is CSA tree compressor reducer array, and 3 is (n+2) position binary adder, and 4 is mould (2 ⁿ+ 2 ^p-1) totalizer.

Concrete annexation can be with reference to summary of the invention part.It should be noted that:

represent the anti-of P, # is junction symbol, for example,

in,

this position is lowest order, at P[2n-1:n] in, P[2n-1] this is most significant digit.

Here, mould (2 ⁿ+ 2 ^p-1) multiplier adopts the result of binary multiplication to process as operand P again, thereby traditional mould (2 ⁿ+ 2 ^p-1) the repeatedly correction of multiplier changes into once and revising.

In enforcement of the present invention, can adopt hardware description language (VHDL or Verilog) according to mould proposed by the invention (2 ⁿ+ 2 ^p-1) structural design of multiplier goes out required mould (2 ⁿ+ 2 ^p-1) multiplier, just can carry out emulation and comprehensive.This multiplier can complete required computing within a clock period, simple high-speed and high-efficiency, and Computer Simulation shows that this multiplier is with respect to existing mould (2 ⁿ+ 2 ^p-1) multiplier all improves a lot aspect Area and Speed.

Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that the protection domain of invention is not limited to such special statement and embodiment.Everyly according to foregoing description, make various possible being equal to and replace or change, be all considered to belong to the protection domain of claim of the present invention.

Claims (1)

1. a mould (2 ⁿ+ 2 ^p-1) multiplier, comprising: (n+1) position binary multiplier, CSA(Carry Save Adder) tree compressor reducer array, (n+2) position binary adder, mould (2 ⁿ+ 2 ^p-1) totalizer;

If A and B are described mould (2 ⁿ+ 2 ^p-1) input of multiplier, total (n+1) position, is respectively [n:0], and Y is described mould (2 ⁿ+ 2 ^p-1) output of multiplier, total (n+1) position, be [n:0], wherein, A[u:v], B[u:v] and Y[u:v] representing that respectively the v position of A, B and Y is to the number of u position correspondence, concrete annexation is as follows:

Two input ends of described (n+1) position binary multiplier are respectively used to input described mould (2 ⁿ+ 2 ^p-1) input A and B for two of multiplier, described n position binary multiplier is output as P, and wherein, P is 2n+2 position, is specially [2n+1:0];

Six input ends of described CSA tree compressor reducer array are respectively used to the combination P[n-1:0 of corresponding bit data of the output P of input described (n+1) position binary multiplier], P[2n-1:n],

(2 ⁿ-2 ^p+2-2 ^p+1-1), wherein, # is junction symbol, and two output terminals of described CSA tree compressor reducer array are respectively: present bit output L[n+1:0], carry output H[n+1:0];

Two addend input ends of described (n+2) position binary adder are respectively used to input L[n+1:0] and H[n+1:0], described (n+2) position binary adder with carry input is output as T[n+2:0];

Described mould (2 ⁿ+ 2 ^p-1) two of totalizer input ports are respectively used to the output T[n+2:0 of input described (n+2) position binary adder] corresponding position T[n-1:0] and the combination of corresponding

described mould (2 ⁿ+ 2 ^p-1) the output of totalizer be described mould (2 ⁿ+ 2 ^p-1) the output Y of multiplier.

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