CN203720258U - Voltage and current transient signal high-speed synchronous data sampling device - Google Patents
Voltage and current transient signal high-speed synchronous data sampling device Download PDFInfo
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Abstract
The utility model provides a voltage and current transient signal high-speed synchronous data sampling device, which comprises a voltage and current input transmission circuit, a signal conditioning circuit, an analog-to-digital conversion circuit and a main control field programmable gate array unit, wherein the voltage and current input transmission circuit is used for linearly transmitting a voltage and current transient signal of the power system into an analog voltage-current signal comprising multiple frequency bands; the signal conditioning circuit is used for carrying out filtering and operational amplifying processing on the analog voltage-current signal with multiple frequency bands; the analog-to-digital conversion circuit is used for converting the analog voltage-current signal into a digital voltage-current signal; and the main control field programmable gate array unit is used for realizing the synchronous high-speed sampling of the voltage and current transient signal. The voltage and current transient signal high-speed synchronous data sampling device can realize the synchronous high-speed data sampling of multiple channels, and the plurality of sampling devices can realize the synchronous sampling of multiple sampling modules under the control of the same clock signal, so that the extension of the sampling channel is not restricted.
Description
Technical field
The utility model relates to power technology field, relates in particular to a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus.
Background technology
At present; the collection of conventional electric system Microcomputer Protection to electric simulation amount signal, is substantially all based on periodic stable state power frequency component, realizes multichannel synchronal data sampling by technology of frequency tracking; sampling rate is not high, yet comparative maturity of correlation technique.Aspect sampling rate; no matter be the sampling system using in the extensive Microcomputer Protection sampling system using or digital transformer substation; the sampling rate of each power frequency period is less than 200 points/cycle substantially, installs discernmible higher harmonics number of times and can not exceed 20 subharmonic.
In recent years; people recognize contains abundant high fdrequency component in electric power system fault transient signal; can therefrom obtain some very valuable fault characteristic informations by Digital Signal Processing, therefore, the protection theory based on fault-signal transient signal obtains development and application gradually.But with respect to steady-state signal, there is a following difficult problem in the sampling of transient signal:
1, signal presents aperiodicity, cannot realize synchronized sampling by frequency of utilization tracking.
2, signal duration very short, generally only have several millisecond, even only have tens microseconds.
3, generally need to carry out synchronized sampling to the analog quantity such as voltage, electric current of many circuits, single-piece molded number converter (hereinafter to be referred as ADC) cannot complete the collection of all passages sometimes.
Traditional data acquisition modes, to use microcontroller (hereinafter to be referred as MCU) to control ADC work, which circuit is simple, few at some sampling channels, in the less demanding system of sampling rate, be used widely, still, in High Speed Sampling System, if still adopted in this way, will bring a lot of problems, mainly contain:
1, sample rate is subject to the impact of MCU processing speed.
Because ADC is sampling, the transmission of carrying out data under the control of MCU, so data sampling speed can not be higher than the frequency of operation of MCU.Meanwhile, other tasks such as communication, man-machine, data processing also can take a large amount of time of MCU, therefore, utilize MCU to control the mode efficiency of ADC work lower, have limited the raising of sampling rate.
2, ADC and MCU timing synchronization existing problems
In electric system, generally need multi-channel synchronous sampling.In the time that sample frequency is too high, very high to the timing synchronization requirement between MCU and ADC, if cannot be synchronous, will cause that ADC cannot normally work, cause whole data acquisition system (DAS) collapse.
3, affect the work efficiency of MCU
In the time that sample frequency is too high, MCU will be used for a large amount of processor time to control ADC and read the data after conversion, thereby causes distributing to the time decreased of other tasks, affects the overall performance of system.Past, in the time solving High Speed Sampling System, due to the method not had, have to additionally adopt a slice to control specially ADC from MCU, then by communication interface, sampled data is passed to main MCU, this will increase hardware cost, reduce hardware reliability, affect the operational efficiency of main MCU.
4, high-speed sampling number of active lanes is limited
In the time that MCU is used for controlling ADC and carries out high-speed sampling, be limited by the performance of MCU itself, if increase too much sampling channel, certainly will increase the data processing time of MCU, affect system performance.And at relay protection device; particularly, in single-phase earth fault line selection device, the synchronism of sampling channel number and sampled data is had to higher requirement, if cannot realize multichannel sampling; the use field that is seriously restricting device, can not meet actual motion demand.
Utility model content
For solving the problems of the technologies described above, the utility model provides a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus, comprising: voltage and current input progress of disease circuit, signal conditioning circuit, analog to digital conversion circuit, master control field programmable gate array unit;
Described voltage and current input progress of disease circuit, for by the electric current and voltage transient signal of electric system linearly the progress of disease be the analog voltage current signal that includes multiple frequency bands;
Described signal conditioning circuit, comprises filtering circuit and discharge circuit, carries out filtering and amplifier processing for the analog voltage current signal to described multiple frequency bands;
Analog-digital conversion circuit as described, for being converted to digital voltage current signal by the analog voltage current signal through described signal conditioning circuit processing;
Master control field programmable gate array unit, for generating control signal to control described voltage and current input progress of disease circuit, signal conditioning circuit, analog to digital conversion circuit work to realize the synchronous high-speed sampling to described electric current and voltage transient signal.
Wherein, described device also comprises: outer clock circuit;
Generate the required external timing signal of control signal for generation of described master control field programmable gate array unit.
Wherein, described voltage and current input progress of disease circuit comprises:
For the Hall element of progress of disease voltage transient signal;
For the Luo-coil of progress of disease current temporary state signal.
Wherein, described master control field programmable gate array unit comprises:
Benchmark timing sampling control module, the benchmark timing sampling control signal of sending for detection of micro-control unit or global positioning system apparatus;
Analog to digital conversion control module, its switching signal line is connected with the I/O pin of described master control field programmable gate array unit with reading data signal line, when described benchmark timing sampling control module detects after benchmark timing sampling control signal, output analog to digital conversion control signal, carry out synchronous high-speed sampling with all passages of controlling analog-digital conversion circuit as described, after sampling completes, sampled data is stored in dual port random access storer;
Dual port random access storer, it comprises the data cache function of two dual port random access memory areas to realize.
Wherein, described master control field programmable gate array unit stores the digital signal of described analog to digital converter output into first dual port random access memory areas place, when first dual port random access memory areas is filled with after data, described master control field programmable gate array unit just sends interrupt request singal to microprocessor, stores the digital signal of analog to digital converter output into second dual port random access memory areas place immediately simultaneously; Before second dual port random access memory areas is filled with data, microprocessor responds interrupt request, reads the data in first dual port random access memory areas;
Described second dual port random access memory areas is filled with after data, described master control field programmable gate array unit stores data into first dual port random access memory areas again, and then microprocessor read second data in dual port random access memory areas before first dual port random access memory areas is filled with data.
Wherein, the time of described microprocessor read data from first dual port random access memory areas or second dual port random access memory areas was less than to the time of writing data in first dual port random access memory areas or second dual port random access memory areas.
Wherein, described master control field programmable gate array unit also comprises:
Interrupt producing control module, after it is controlled dual port random access storer store data completes in predetermined address space, produce a look-at-me, this look-at-me is connected with exterior interrupt.
Wherein, described device also comprises:
Central processing unit, produces for detection of described interruption the look-at-me that control module produces, and after it detects that this look-at-me effectively, release data bus, address bus, control bus read the sampled data of buffer memory in dual port random access storer.
Wherein, when described central processing unit has read the data in an address of described dual port random access storer, described interruption produces control module and regains look-at-me, makes this dual port random access storer be ready for data buffer storage next time.
Implement the utility model, there is following beneficial effect:
The utility model utilizes field programmable gate array unit (hereinafter to be referred as FPGA) to control the high-speed synchronous data sampling of voltage, current temporary state signal in the electric system of analog to digital converter (ADC) realization, carries out a series of shortcomings of data sampling to overcome traditional use MCU control ADC.
A kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus of the utility model design can be realized the synchronous high-speed data sampling of multiple passages, and multiple electric current and voltage transient signal high-speed synchronous data sampling apparatuses can be realized the synchronized sampling of many sampling modules under the control of same clock signal, make the expansion of sampling channel unrestricted.
Brief description of the drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus embodiment mono-of providing of the utility model;
Fig. 2 is the structural representation of a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus embodiment bis-of providing of the utility model;
Fig. 3 is the structural representation of a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus embodiment tri-of providing of the utility model;
Fig. 4 is the structural representation of a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus embodiment tetra-of providing of the utility model.
Embodiment
Referring to Fig. 1, a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus that the utility model provides, comprising:
Voltage and current input progress of disease circuit 1, signal conditioning circuit 2, analog to digital conversion circuit 3, master control field programmable gate array unit (FPGA, Field-Programmable Gate Array) 4;
Described voltage and current input progress of disease circuit 1, for being the analog voltage current signal that includes multiple frequency bands by the electric current and voltage transient signal progress of disease of linear electric system;
Described signal conditioning circuit 2, comprises filtering circuit and discharge circuit, carries out filtering and amplifier processing for the analog voltage current signal to described multiple frequency bands;
Analog-digital conversion circuit as described 3, for being converted to digital voltage current signal by the analog voltage current signal of processing through described signal conditioning circuit 2;
Master control field programmable gate array unit 4, works to realize the synchronous high-speed sampling to described electric current and voltage transient signal for generating control signal to control described voltage and current input progress of disease circuit 1, signal conditioning circuit 2, analog to digital conversion circuit 3.
Described device also comprises: outer clock circuit 5;
Generate the required external timing signal of control signal for generation of described master control field programmable gate array unit 4.
The voltage of electric system, current temporary state signal, before carrying out signal condition, need first carry out the progress of disease to signal, by its linearly the progress of disease be the simulating signal that is applicable to analog to digital converter input and processes.
Referring to Fig. 2, the structural representation of a kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus embodiment bis-that the utility model provides.
In the present embodiment, described voltage and current input progress of disease circuit 1 comprises:
For the Hall element 10 of progress of disease voltage transient signal;
For the Luo-coil 11 of progress of disease current temporary state signal.
It should be noted that, be to utilize electromagnetic potential transformer to carry out progress of disease voltage signal in prior art, carrys out progress of disease current signal with electromagnetic type electric current current transformer.But electromagnetic transformer has the shortcomings such as magnetic saturation, phase angle error is large, energy loss is large in the time of progress of disease electric simulation amount, the electric parameters that cannot be applicable to transient fault detects, the also detection of inapplicable high speed signal.The utility model adopts Hall element 10 progress of disease voltage signals, and the feature that Hall element 10 linearities are good, bandwidth range is large, measurement range is large, overload capacity is strong solves the progress of disease problem of voltage transient signal well.In addition, adopt Luo-coil 11 to carry out progress of disease current signal in the utility model, the feature that the linearity is good, bandwidth range is large, measurement range is large, conveyance capacity is strong, function is low, anti-interference is good of Luo-coil, can solve the progress of disease problem of current temporary state signal.
In specific implementation, power system voltage, current signal after the progress of disease of Hall mutual inductor 10 and Luo-coil 11, obtain including the simulating signal of multiple frequency bands respectively.This simulating signal needs further conditioning, as shown in Figure 2, described signal conditioning circuit 2 comprises filtering circuit 20 parts and discharge circuit 21 parts, the signal of main frequency of utilization in 5kHz in actual applications, so, filtering circuit 20 in signal conditioning circuit 2 is designed to broadband, high input impedance, low output impedance, circuit that phase-frequency characteristic is good, and cutoff frequency is limited in 5kHz.
It should be noted that, each electric current and voltage transient signal high-speed synchronous data sampling apparatus can be realized the data acquisition of 12 passages, in order to ensure the independence of each passage, each passage is designed to independently active filter circuit and discharge circuit and carry out signal condition.
Shown in Fig. 2; the selected analog to digital converter chip of analog to digital conversion circuit (ADC) is 16, quick, low-power consumption successive approximation type a/d C; maximum throughput can reach 250ksps; and built-in low noise, wide bandwidth sample/hold amplifier; can process the incoming frequency up to 12MHz; possess high-speed parallel data-interface, be mainly used in power system relay protection device and Instrumentation and Control system.
A kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus of the present utility model configures two analog to digital converter chips, realizes altogether the analog to digital conversion of 12 passages.Two analog to digital converter chips share same set of control signal and data-signal, so both can ensure the synchro control of two chip blocks, can simplify again circuit design.Can design consideration in conjunction with electric system actual needs and system EMC, two analog to digital converter chips, under the control of sampling clock and gating signal, are realized the sampling rate of 51.2Ksample/s.
Master control field programmable gate array unit 4 as shown in Figure 2, be that master control FPGA4 is the core of whole electric current and voltage transient signal high-speed synchronous data sampling apparatus, the required full control signal of its generation system, the various piece that ensures electric current and voltage transient signal high-speed synchronous data sampling apparatus can be worked harmoniously, in addition, it also realizes the caching function of data.Master control FPGA utilizes external timing signal in inner frequency multiplication or frequency division processing, realizes and controls the clock signal needing.Realize the EP1C3 chip that the design of ALTERA company of the master control fpga chip selection U.S. is produced, the major function of realization has the control of benchmark timing sampling, ADC conversion and control, dual port RAM control, interrupts producing control etc.
Concrete, as shown in Figure 3, described master control field programmable gate array unit 4 specifically comprises:
Benchmark timing sampling control module 40, the benchmark timing sampling control signal of sending for detection of micro-control unit or global positioning system apparatus;
Analog to digital conversion control module 41, its switching signal line is connected with the I/O pin of described master control field programmable gate array unit 4 with reading data signal line, when described benchmark timing sampling control module 40 detects after benchmark timing sampling control signal, output analog to digital conversion control signal, carry out synchronous high-speed sampling with all passages of controlling analog-digital conversion circuit as described ADC3, after sampling completes, sampled data is stored in dual port random access storer 42;
Concrete, in the time that the benchmark timing sampling control module 40 of FPGA4 detects the benchmark timing sampling control signal that MCU or GPS device send, FPGA4 just starts ADC conversion and control.Like this, electric current and voltage transient signal high-speed synchronous data sampling apparatus can carry out analog to digital conversion at synchronization, realizes synchronized sampling.Because electric current and voltage transient signal high-speed synchronous data sampling apparatus adopts unified benchmark timing sampling control signal, so its sampling clock error is minimum, and can there is not the sampling clock cumulative errors between multimode, can ensure well the sample-synchronous of many sampling modules.
Dual port random access storer 42, it comprises the data cache function of two dual port random access memory areas to realize.
Wherein, the digital signal that described analog to digital converter 3 is exported in described master control field programmable gate array unit 4 stores first dual port random access memory areas place into, when first dual port random access memory areas is filled with after data, described master control field programmable gate array unit just sends interrupt request singal to microprocessor, stores the digital signal of analog to digital converter output into second dual port random access memory areas place immediately simultaneously; Before second dual port random access memory areas is filled with data, microprocessor responds interrupt request, reads the data in first dual port random access memory areas;
Described second dual port random access memory areas is filled with after data, described master control field programmable gate array unit stores data into first dual port random access memory areas again, and then microprocessor read second data in dual port random access memory areas before first dual port random access memory areas is filled with data.
Wherein, the time of described microprocessor read data from first dual port random access memory areas or second dual port random access memory areas was less than to the time of writing data in first dual port random access memory areas or second dual port random access memory areas.
Wherein, described master control field programmable gate array unit 4 also comprises:
Interrupt producing control module 43, after it is controlled dual port random access storer store data completes in predetermined address space, produce a look-at-me, this look-at-me is connected with exterior interrupt.
As shown in Figure 4, described electric current and voltage transient signal high-speed synchronous data sampling apparatus also comprises:
Central processing unit 6, be called for short CPU, it produces for detection of described interruption the look-at-me that control module 43 produces, and after it detects that this look-at-me effectively, release data bus, address bus, control bus read the sampled data of buffer memory in dual port random access storer.
Wherein, when described central processing unit 6 has read the data in an address of described dual port random access storer 42, described interruption produces control module 43 and regains look-at-me, makes this dual port random access storer 42 be ready for data buffer storage next time.
Describing electric current and voltage transient signal high-speed synchronous data sampling apparatus in detail below with reference to Fig. 1 ~ Fig. 4 is realized high-speed cache and is produced by interruption the process that control is interrupted in control module 43 realizations by dual port random access storer 42.
In specific implementation, in FPGA4, open up the data cache function that Liang Ge dual port RAM district realizes.Liang Ge dual port RAM district is called after RAM1 and RAM2 respectively, adopts the mode of pingpang handoff to store data between them.First, FPGA4 stores the digital signal of ADC3 output into RAM1 address place, and when RAM1 is filled with after data, FPGA just sends interrupt request singal to MCU, stores the digital signal of ADC3 output into RAM2 address place immediately simultaneously.Before RAM2 is filled with data, MCU responds interrupt request, reads the data in RAM1.Equally, wait RAM2 to be filled with after data, FPGA4 stores data into RAM1 district again, and then MCU read the data in RAM2 before RAM1 is filled with data.Constantly repeat this process, just can realize ADC sampling and MCU read data and carry out simultaneously, can significantly improve sampling rate.Because the time of read data from RAM1 or RAM2 was significantly less than to the time of writing data in RAM1 or RAM2, therefore, when FPGA controls ADC sampling, MCU has time enough to read the data of last sampling, and reading and writing data mistake can not occur.
FPGA controls dual port RAM after store data completes in certain address space, the interruption of FPGA4 produces control module 43 will produce a look-at-me, this look-at-me is connected with the exterior interrupt of CPU6, after CPU6 detects that this look-at-me effectively, CPU6 reads release data bus, address bus, control bus the sampled data of buffer memory in dual port RAM.In the time that CPU6 reads the data in first address of dual port RAM, FPGA4 will regain look-at-me, makes this sheet dual port RAM be ready for data buffer storage next time.
Take after above measure, can realize multichannel synchronous high-speed sampling.Taking the sampling rate of 1024 points/cycle as example, under classic method, CPU directly controls ADC sampling and reads adc data, and every cycle CPU need to interrupt 1024 times, and interrupt interval is 20/1024=0.0195ms, if CPU frequency is 50M, be that clock is 0.02us, the CPU execution time only has 19.5/0.02=975 clock so, calculates by 3 clock period of average every instruction, can only carry out at most 325 instructions, obviously cannot meet system requirements.And this programme sampling interrupt interval is 2.5ms, be 128 times of classic method, carry out at most the instruction of 325*128=41600 bar, realize the real-time property processing under high-speed sampling.
Implement the utility model, there is following beneficial effect:
The utility model utilizes field programmable gate array unit (hereinafter to be referred as FPGA) to control the high-speed synchronous data sampling of voltage, current temporary state signal in the electric system of analog to digital converter (ADC) realization, carries out a series of shortcomings of data sampling to overcome traditional use MCU control ADC.
A kind of electric current and voltage transient signal high-speed synchronous data sampling apparatus of the utility model design can be realized the synchronous high-speed data sampling of multiple passages, and multiple electric current and voltage transient signal high-speed synchronous data sampling apparatuses can be realized the synchronized sampling of many sampling modules under the control of same clock signal, make the expansion of sampling channel unrestricted.
It should be noted that; what the utility model was described is a kind of a kind of product form of electric current and voltage transient signal high-speed synchronous data sampling apparatus; other meets the product of structure described in the utility model; even if material, device name, outward appearance, device are put order etc., not affect the factor of product performance not identical, still belongs to the scope of the utility model protection.
Above content is in conjunction with concrete preferred implementation further detailed description of the utility model, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, without departing from the concept of the premise utility, can also make some simple deduction or replace, all should be considered as belonging to protection domain of the present utility model.
Claims (9)
1. an electric current and voltage transient signal high-speed synchronous data sampling apparatus, is characterized in that, comprising: voltage and current input progress of disease circuit, signal conditioning circuit, analog to digital conversion circuit, master control field programmable gate array unit;
Described voltage and current input progress of disease circuit, for by the electric current and voltage transient signal of electric system linearly the progress of disease be the analog voltage current signal that includes multiple frequency bands;
Described signal conditioning circuit, comprises filtering circuit and discharge circuit, carries out filtering and amplifier processing for the analog voltage current signal to described multiple frequency bands;
Analog-digital conversion circuit as described, for being converted to digital voltage current signal by the analog voltage current signal through described signal conditioning circuit processing;
Master control field programmable gate array unit, for generating control signal to control described voltage and current input progress of disease circuit, signal conditioning circuit, analog to digital conversion circuit work to realize the synchronous high-speed sampling to described electric current and voltage transient signal.
2. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 1, is characterized in that, described device also comprises: outer clock circuit;
Generate the required external timing signal of control signal for generation of described master control field programmable gate array unit.
3. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 2, is characterized in that, described voltage and current input progress of disease circuit comprises:
For the Hall element of progress of disease voltage transient signal;
For the Luo-coil of progress of disease current temporary state signal.
4. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 3, is characterized in that, described master control field programmable gate array unit comprises:
Benchmark timing sampling control module, the benchmark timing sampling control signal of sending for detection of micro-control unit or global positioning system apparatus;
Analog to digital conversion control module, its switching signal line is connected with the I/O pin of described master control field programmable gate array unit with reading data signal line, when described benchmark timing sampling control module detects after benchmark timing sampling control signal, output analog to digital conversion control signal, carry out synchronous high-speed sampling with all passages of controlling analog-digital conversion circuit as described, after sampling completes, sampled data is stored in dual port random access storer;
Dual port random access storer, it comprises the data cache function of two dual port random access memory areas to realize.
5. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 4, it is characterized in that, described master control field programmable gate array unit stores the digital signal of described analog to digital converter output into first dual port random access memory areas place, when first dual port random access memory areas is filled with after data, described master control field programmable gate array unit just sends interrupt request singal to microprocessor, stores the digital signal of analog to digital converter output into second dual port random access memory areas place immediately simultaneously; Before second dual port random access memory areas is filled with data, microprocessor responds interrupt request, reads the data in first dual port random access memory areas;
Described second dual port random access memory areas is filled with after data, described master control field programmable gate array unit stores data into first dual port random access memory areas again, and then microprocessor read second data in dual port random access memory areas before first dual port random access memory areas is filled with data.
6. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 5, it is characterized in that, the time of described microprocessor read data from first dual port random access memory areas or second dual port random access memory areas was less than to the time of writing data in first dual port random access memory areas or second dual port random access memory areas.
7. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 6, is characterized in that, described master control field programmable gate array unit also comprises:
Interrupt producing control module, after it is controlled dual port random access storer store data completes in predetermined address space, produce a look-at-me, this look-at-me is connected with exterior interrupt.
8. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 7, is characterized in that, described device also comprises:
Central processing unit, produces for detection of described interruption the look-at-me that control module produces, and after it detects that this look-at-me effectively, release data bus, address bus, control bus read the sampled data of buffer memory in dual port random access storer.
9. electric current and voltage transient signal high-speed synchronous data sampling apparatus as claimed in claim 8, it is characterized in that, when described central processing unit has read the data in an address of described dual port random access storer, described interruption produces control module and regains look-at-me, makes this dual port random access storer be ready for data buffer storage next time.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155545A (en) * | 2014-07-28 | 2014-11-19 | 广西电网公司电力科学研究院 | Multichannel analog quantity acquisition module based on GPS signals |
| CN106443541A (en) * | 2016-09-06 | 2017-02-22 | 南京大全自动化科技有限公司 | Voltage and current sampling and sampling value angle calibration method for power distribution device |
| CN110824977A (en) * | 2019-09-24 | 2020-02-21 | 广东科瑞德电气科技有限公司 | Signal sampling method, MCU core processing module and power distribution automation terminal |
-
2014
- 2014-01-24 CN CN201420045983.6U patent/CN203720258U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155545A (en) * | 2014-07-28 | 2014-11-19 | 广西电网公司电力科学研究院 | Multichannel analog quantity acquisition module based on GPS signals |
| CN106443541A (en) * | 2016-09-06 | 2017-02-22 | 南京大全自动化科技有限公司 | Voltage and current sampling and sampling value angle calibration method for power distribution device |
| CN110824977A (en) * | 2019-09-24 | 2020-02-21 | 广东科瑞德电气科技有限公司 | Signal sampling method, MCU core processing module and power distribution automation terminal |
| CN110824977B (en) * | 2019-09-24 | 2023-06-27 | 广东科瑞德电气科技有限公司 | Signal sampling method, MCU core processing module and power distribution automation terminal |
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