CN103763064A - CRC code generating method and circuit applicable to ultra-high-speed communication system - Google Patents
CRC code generating method and circuit applicable to ultra-high-speed communication system Download PDFInfo
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- CN103763064A CN103763064A CN201410038714.1A CN201410038714A CN103763064A CN 103763064 A CN103763064 A CN 103763064A CN 201410038714 A CN201410038714 A CN 201410038714A CN 103763064 A CN103763064 A CN 103763064A
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Abstract
The invention relates to a CRC code generating method and circuit applicable to an ultra-high-speed communication system, and belongs to the technical field of ultra-high-speed communication systems. According to the technical scheme, the CRC code generating method applicable to the ultra-high-speed communication system comprises the following steps of a, receiving n bit data M within one cycle, and partitioning the data M into blocks freely, wherein the width of each partitioned block is the same as n, and the effective data position of each partitioned block is the same as the data position in the data M; b, conducting CRC calculation on the partitioned blocks in parallel, adding CRC codes obtained by the CRC calculation of all the partitioned blocks, and conducting total negation on the calculation value obtained after addition so as to output the required CRC code value. According to the CRC code generating method and circuit applicable to the ultra-high-speed communication system, the structure is simple, production efficiency is high, the cost is low, and the requirement of the ultra-high-speed system for conducting the CRC on high-parallel data is met.
Description
Technical field
The present invention relates to a kind of method and circuit, especially a kind of cyclic redundancy check (CRC) code generation method and circuit that is applicable to ultrahigh speed communication system, belongs to the technical field of ultrahigh speed communication system.
Background technology
Cyclic redundancy check (CRC) technology is usually a kind of calibration technology of use of right and wrong in network communication, can check conveniently and fast that whether transmission data are correct.But along with the speed of network communication is more and more higher, the cyclic redundancy check (CRC) that complete high degree of parallelism within the shorter and shorter time is calculated more and more difficult.
Existing about improving CRC(Cyclic Redundancy Check) method of computational efficiency has: directly long numeric data carried out to concurrent operation, then according to last bat, has under multiple possible situation, select correct data output; Or for last bat, have under multiple possible situation, carry out the inverse operation take byte as unit.
Take 40Gbps ethernet standard as example, inner parallel bus is 64, and parallel bus clock frequency is 625MHz.No matter will in a clock cycle 1.6ns, complete the CRC-32 verification of 64 bit data is calculated, be directly 64 bit data to be carried out to CRC computing, or the byte number of last bat is carried out to the method for repeatedly inverse operation, has all been difficult to.Its circuit design difficulty is very big, is difficult to meet the real-time sequential requirement of circuit.Although so above-mentioned existing method has solved the equilibrium problem of circuit area and sequential to a certain extent, there is no to solve the problem of the high degree of parallelism CRC calculating that how to complete many bits within a clock cycle.Therefore need to provide a kind of new, efficiently, can with lower cost, apply to cyclic redundancy check (CRC) computational methods and the circuit of ultrahigh speed communication system, thereby meet ultrahigh speed system, high degree of parallelism data are carried out to the requirement of cyclic redundancy check (CRC).
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of cyclic redundancy check (CRC) code generation method and circuit that is applicable to ultrahigh speed communication system is provided, and it is simple in structure, and formation efficiency is high, cost is low, can meet ultrahigh speed system and high parallel data be carried out to the requirement of cyclic redundancy check (CRC).
According to technical scheme provided by the invention, a kind of cyclic redundancy check (CRC) code generation method that is applicable to ultrahigh speed communication system, described cyclic redundancy check (CRC) code generation method comprises the steps:
N Bit data M in a, reception one-period, and described data M is carried out to any piecemeal, the data width of each piecemeal is similarly n, and the valid data position of each piecemeal is identical with the Data Position in data M;
B, each block parallel is carried out to CRC calculating, and the cyclic redundancy check (CRC) code that the CRC of all piecemeals is calculated carries out addition calculation, and by the whole negates of calculated value after being added, to export required cyclic redundancy check (CRC) code value.
In described step a, the piecemeal of n Bit data M is comprised to even piecemeal or non-homogeneous piecemeal; The whole zero setting of Data Position in each piecemeal outside valid data.
When n Bit data M is evenly divided into K piece, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
N Bit data M is carried out non-homogeneous while being divided into i piece, in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
The described cyclic redundancy check (CRC) code generative circuit that is applicable to ultrahigh speed communication system, the CRC counting circuit that comprises deblocking circuit and be connected with described deblocking circuit, the output of described CRC counting circuit is connected with adder, and the output of adder is connected with inverter;
Deblocking circuit receives the n Bit data M in one-period, and described data M is carried out to any piecemeal, and the data width of each piecemeal is similarly n, and the valid data position of each piecemeal is identical with the Data Position in data M;
CRC counting circuit carries out CRC calculating to each block parallel, and the cyclic redundancy check (CRC) code that the CRC of all piecemeals is calculated is carried out addition calculation by adder, and the calculated value after being added is passed through to the whole negates of inverter, to export required cyclic redundancy check (CRC) code value by inverter.
Described deblocking circuit comprises even piecemeal or non-homogeneous piecemeal to the piecemeal of the n Bit data M receiving; The whole zero setting of Data Position in each piecemeal outside valid data.
When described deblocking circuit is evenly divided into K piece by n Bit data M, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
Described deblocking circuit carries out n Bit data M non-homogeneous while being divided into i piece, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
Advantage of the present invention: by data are carried out to piecemeal, and multiple block parallels are carried out to CRC calculating simultaneously, the cyclic redundancy check (CRC) code obtaining add up again and accumulated value negate after obtain required cyclic redundancy check (CRC) code value, simple in structure, formation efficiency is high, cost is low, can meet ultrahigh speed system and high parallel data be carried out to the requirement of cyclic redundancy check (CRC).
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present invention.
Fig. 2 is the schematic diagram of the even piecemeal of the present invention.
Fig. 3 is the schematic diagram of the non-homogeneous piecemeal of the present invention.
Description of reference numerals: 100-deblocking circuit, 110-CRC counting circuit and 120-adder.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
For can be efficient, carry out at low cost the cyclic redundancy check (CRC) code generation of ultrahigh speed communication system, cyclic redundancy check (CRC) code generation method of the present invention comprises the steps:
N Bit data M in a, reception one-period, and described data M is carried out to any piecemeal, the data width of each piecemeal is similarly n, and the valid data position of each piecemeal is identical with the Data Position in data M;
Wherein, the piecemeal of n Bit data M is comprised to even piecemeal or non-homogeneous piecemeal; The whole zero setting of Data Position in each piecemeal outside valid data.In the embodiment of the present invention, when described valid data refer to n Bit data M piecemeal, the data of correspondence in n Bit data M.In order to make the data width in each piecemeal be similarly n, and keep in each piecemeal valid data position identical with the Data Position of n Bit data M, in the specific implementation, in each piecemeal, by whole the Data Position outside valid data zero setting, by data 0, fill the Data Position of valid data both sides.
When n Bit data M is evenly divided into K piece, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.In the embodiment of the present invention, be divided into after K piecemeal, K piecemeal is respectively piecemeal 1, piecemeal 2 ..., piecemeal K; Usually, the highest order of the position of valid data in n Bit data M in piecemeal K.
When n Bit data M is evenly divided, according to CRC generator polynomial G(x) carry out cyclic redundancy check, the valid data width of each piecemeal is n/K position, by the Data Position to outside valid data in each piecemeal, carries out zero padding, makes the data width of each piecemeal all reach n bit.In the embodiment of the present invention, the highest order of the valid data that in K piecemeal, valid data refer to piecemeal in the piecemeal of highest order in n Bit data M, as the n data M that is 64, valid data refer to the piecemeal that comprises the 63rd (described the 63rd is the highest order of whole data M, and the lowest order of data bit is 0) in the piecemeal of highest order.
N Bit data M is carried out non-homogeneous while being divided into i piece, in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.In the embodiment of the present invention, be divided into after i piecemeal, i piecemeal is respectively piecemeal 1, piecemeal 2 ..., piecemeal i; Usually, the highest order of the position of valid data in n Bit data M in piecemeal i.
Particularly, for the n Bit data M receiving in one-period, be divided into arbitrarily i piece, the quantity of each piecemeal valid data is any bit number r (i), r (i-1) ... r (1), r (i) represents the quantity of valid data in piecemeal i, r (i-1) represents the quantity of valid data in piecemeal (i-1), r (1) represents the quantity of valid data in piecemeal 1, and the n Bit data M of input can be expressed as: M=m
ix
n-r (i)+ m
i-1x
n-r (i)-r (i-1) +m
3x
r (2)+r (1)+ m
2x
r (1)+ m
1; m
ifor the valid data in piecemeal i, m
i-1for the valid data in piecemeal (i-1), m
3for the valid data in piecemeal 3, m
2for the valid data in piecemeal 2, m
1for the valid data in piecemeal 1, CRC proper polynomial G (x) is t rank, and the high order power of G (x) is x
t, with multinomial G (x), to n Bit data M delivery, obtain Mx
tmod G (x), Mx
trepresent that M is to t the bit that move to left, when doing mod computing, data M need to be according to the Mx that carries out of high order power in G (x)
toperation.After n Bit data M is divided into i blocks of data piece, use G (x) delivery, obtain
(m
i?x
n-r(i)+m
i-1x?
n-r(i)-r(i-1) +…m
3x
r(2)+r(1)+m
2x
r(1)+m
1)x
t?mod?G(x)
=(m
ix
n-r(i))x
t?mod?G(x)+(m
i-1x
n-r(i)-r(i-1))x
t?mod?G(x)+…+m
3x
r(2)+r(1)x
tmod?G(x)+m
2x
r(1)x
t?mod?G(x)+m
1x
t?mod?G(x)，
Therefore, there is pair verification of the cyclic redundancy of data M to equal the verification of the cyclic redundancy of each new data block after piecemeal.In the embodiment of the present invention, for the situation of even piecemeal, also there is similar conclusion, repeat no more herein.For non-homogeneous piecemeal and even piecemeal, difference is only the width of valid data in each piecemeal.Evenly the number K of piecemeal and the number i of non-homogeneous piecemeal can select as required.
B, each block parallel is carried out to CRC calculating, and the cyclic redundancy check (CRC) code that the CRC of all piecemeals is calculated carries out addition calculation, and by the whole negates of calculated value after being added, to export required cyclic redundancy check (CRC) code value.
In the embodiment of the present invention, the block parallel of each n bit is carried out to CRC calculating simultaneously, thereby obtain the cyclic redundancy check (CRC) code of each piecemeal, to the cyclic redundancy check (CRC) code addition calculation of all piecemeals, and by the calculated value negate after being added, thereby can obtain the cyclic redundancy check (CRC) code value of whole n Bit data M.In this step, identical with the situation operation of non-homogeneous piecemeal for even piecemeal.In addition, multiple block parallels are carried out to CRC calculating simultaneously and can adopt existing computational methods, can be specifically the disclosed technical scheme of generation method and apparatus > > of the disclosed < < of a CN103269255A Parallel CRC circuit with reference to publication number, repeat no more herein.
As shown in Figure 1, Figure 2 and Figure 3: above-mentioned cyclic redundancy check (CRC) code generation method, can implement by following circuit, particularly, the CRC counting circuit 110 that generative circuit comprises deblocking circuit 100 and is connected with described deblocking circuit 100, the output of described CRC counting circuit 110 is connected with adder 120, and the output of adder 120 is connected with inverter;
Described deblocking circuit 100 comprises even piecemeal or non-homogeneous piecemeal to the piecemeal of the n Bit data M receiving; The whole zero setting of Data Position in each piecemeal outside valid data.
When described deblocking circuit 100 is evenly divided into K piece by n Bit data M, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
Described deblocking circuit 100 carries out n Bit data M non-homogeneous while being divided into i piece, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
During concrete enforcement, deblocking circuit 100 receives data, and data are carried out to piecemeal, and the initial value of generation cycle redundancy check code; CRC counting circuit 110 can carry out required CRC according to existing CRC account form and calculate, adder 120 is for carrying out binary addition to multiple cyclic redundancy check (CRC) code, inverter is for carrying out negate to the output valve of adder 120, the concrete structure of foregoing circuit, it not emphasis of the present invention, as long as can complete corresponding function, repeat no more herein.
Embodiment 1:
Take 40Gbps ethernet standard as example, the Method and Process that produces CRC-32 cyclic redundancy check (CRC) code within a clock cycle is described.
In the present embodiment, inner parallel bus is 64 bits, parallel bus clock frequency is 625MHz, that is to say a clock cycle to be in 1.6ns, to complete the CRC-32 verification of 64 bit data to calculate, in the present embodiment, the generator polynomial of CRC-32 is G (x)=x
32+ x
26+ x
23+ x
22+ x
16+ x
12+ x
11+ x
10+ x
8+ x
7+ x
5+ x
4+ x
2+ x+1, with hexadecimal representation be 16 ' h04c11db7.
Circular and step are as follows:
Within a clock cycle, receive 64 parallel Bit datas; By 64 Bit datas that receive within a clock cycle, by high-low-position, be divided into equably 4, every valid data are 16 bits, after piecemeal, new data block is also 64 bits, wherein the position of valid data is identical with before piecemeal, the whole zero paddings of Data Position of all the other 48 bits in each piecemeal; Within the same clock cycle, each 64 new Bit data piecemeal is carried out separately to the calculating of cyclic redundancy check (CRC) code;
The same clock cycle in, the cyclic redundancy check (CRC) code of by adder 120,32 bit data of 4 data blocks are calculated 32 is added, then by the whole negates of value after being added, obtains the cyclic redundancy check (CRC) code of whole 64 Bit datas; And output with the same clock cycle in 32 cyclic redundancy check (CRC) code of data.
The present invention is by carrying out piecemeal to data, and multiple block parallels are carried out to CRC calculating simultaneously, the cyclic redundancy check (CRC) code obtaining add up again and accumulated value negate after obtain required cyclic redundancy check (CRC) code value, simple in structure, formation efficiency is high, cost is low, can meet ultrahigh speed system and high parallel data be carried out to the requirement of cyclic redundancy check (CRC).
In the present invention, should, according to the multinomial of the bit number of the clock cycle in specific embodiment, pending parallel data and calculating cyclic redundancy verification, reasonably to parallel data piecemeal, arrive the optimization of sequential and resource.
It should be noted; although described illustrative embodiments of the present invention above, the variation of carrying out within the scope of technical solution of the present invention, revises and replaces; and use being different from applied environment of the present invention, all should be contained in protection scope of the present invention.
Claims (8)
1. one kind is applicable to the cyclic redundancy check (CRC) code generation method of ultrahigh speed communication system, it is characterized in that, described cyclic redundancy check (CRC) code generation method comprises the steps:
(a), receive the n Bit data M in one-period, and described data M is carried out to any piecemeal, the data width of each piecemeal is similarly n, and the valid data position of each piecemeal is identical with the Data Position in data M;
(b), each block parallel is carried out to CRC calculating, and the cyclic redundancy check (CRC) code that the CRC of all piecemeals is calculated carries out addition calculation, and by the whole negates of calculated value after being added, to export required cyclic redundancy check (CRC) code value.
2. the cyclic redundancy check (CRC) code generation method that is applicable to ultrahigh speed communication system according to claim 1, is characterized in that: in described step (a), the piecemeal of n Bit data M is comprised to even piecemeal or non-homogeneous piecemeal; The whole zero setting of Data Position in each piecemeal outside valid data.
3. the cyclic redundancy check (CRC) code generation method that is applicable to ultrahigh speed communication system according to claim 2, it is characterized in that: when n Bit data M is evenly divided into K piece, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
4. the cyclic redundancy check (CRC) code generation method that is applicable to ultrahigh speed communication system according to claim 2, it is characterized in that: when n Bit data M is carried out to the non-homogeneous i of being divided into piece, in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
5. one kind is applicable to the cyclic redundancy check (CRC) code generative circuit of ultrahigh speed communication system, it is characterized in that, the CRC counting circuit (110) that comprises deblocking circuit (100) and be connected with described deblocking circuit (100), the output of described CRC counting circuit (110) is connected with adder (120), and the output of adder (120) is connected with inverter;
Deblocking circuit (100) receives the n Bit data M in one-period, and described data M is carried out to any piecemeal, and the data width of each piecemeal is similarly n, and the valid data position of each piecemeal is identical with the Data Position in data M;
CRC counting circuit (110) carries out CRC calculating to each block parallel, and the cyclic redundancy check (CRC) code that the CRC of all piecemeals is calculated is carried out addition calculation by adder (120), and the calculated value after being added is passed through to the whole negates of inverter, to export required cyclic redundancy check (CRC) code value by inverter.
6. the cyclic redundancy check (CRC) code generative circuit that is applicable to according to claim 5 ultrahigh speed communication system, is characterized in that: described deblocking circuit (100) comprises even piecemeal or non-homogeneous piecemeal to the piecemeal of the n Bit data M receiving; The whole zero setting of Data Position in each piecemeal outside valid data.
7. be applicable to according to claim 6 the cyclic redundancy check (CRC) code generative circuit of ultrahigh speed communication system, it is characterized in that: when described deblocking circuit (100) is evenly divided into K piece by n Bit data M, the valid data width of each piecemeal is n/K position, and the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0 in K piecemeal, in K piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
8. be applicable to according to claim 6 the cyclic redundancy check (CRC) code generative circuit of ultrahigh speed communication system, it is characterized in that: when described deblocking circuit (100) carries out the non-homogeneous i of being divided into piece by n Bit data M, in i piecemeal, the cyclic redundancy check (CRC) code initial value of the piecemeal of valid data in highest order is full 0, and in i piecemeal, the cyclic redundancy check (CRC) code initial value of all the other piecemeals is complete 1.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105389229A (en) * | 2015-10-29 | 2016-03-09 | 中国科学院微电子研究所 | CRC (Cyclic Redundancy Check) checking circuit applicable to 64-bit bus bit width and checking method |
| CN105721107A (en) * | 2016-02-03 | 2016-06-29 | 华信塞姆（成都）科技有限公司 | Device and method for improving clock frequency by block calculation of CRC (Cyclic Redundancy Check) |
| CN106650835A (en) * | 2015-07-22 | 2017-05-10 | 深圳市远望谷信息技术股份有限公司 | Method for improving data transmission reliability in train number identification system |
| WO2022057872A1 (en) * | 2020-09-21 | 2022-03-24 | 华为技术有限公司 | Data processing method and related apparatus |
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2014
- 2014-01-26 CN CN201410038714.1A patent/CN103763064A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106650835A (en) * | 2015-07-22 | 2017-05-10 | 深圳市远望谷信息技术股份有限公司 | Method for improving data transmission reliability in train number identification system |
| CN106650835B (en) * | 2015-07-22 | 2020-04-10 | 深圳市远望谷信息技术股份有限公司 | Method for improving data transmission reliability in railway train number identification system |
| CN105389229A (en) * | 2015-10-29 | 2016-03-09 | 中国科学院微电子研究所 | CRC (Cyclic Redundancy Check) checking circuit applicable to 64-bit bus bit width and checking method |
| CN105389229B (en) * | 2015-10-29 | 2018-09-25 | 中国科学院微电子研究所 | CRC check circuit and method of calibration suitable for 64 BITBUS network bit wides |
| CN105721107A (en) * | 2016-02-03 | 2016-06-29 | 华信塞姆（成都）科技有限公司 | Device and method for improving clock frequency by block calculation of CRC (Cyclic Redundancy Check) |
| CN105721107B (en) * | 2016-02-03 | 2019-03-22 | 华信塞姆（成都）科技有限公司 | A kind of piecemeal calculates device and method of the CRC to improve clock frequency |
| WO2022057872A1 (en) * | 2020-09-21 | 2022-03-24 | 华为技术有限公司 | Data processing method and related apparatus |
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Address after: Room 5 No. 58 digital circuit of Hui Road Binhu District 214037 Jiangsu city of Wuxi Province Applicant after: China Electronics Technology Group Corporation No.58 Research Institute Address before: Hui Road Binhu District 214035 Jiangsu city of Wuxi province No. 5 58 Simulation Laboratory Applicant before: China Electronics Technology Group Corporation No.58 Research Institute |
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