CN102594370B - High-efficient low-delay parallel Chien search method and device - Google Patents
High-efficient low-delay parallel Chien search method and device Download PDFInfo
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- CN102594370B CN102594370B CN2012100461297A CN201210046129A CN102594370B CN 102594370 B CN102594370 B CN 102594370B CN 2012100461297 A CN2012100461297 A CN 2012100461297A CN 201210046129 A CN201210046129 A CN 201210046129A CN 102594370 B CN102594370 B CN 102594370B
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Abstract
The invention discloses a high-efficient low-delay parallel Chien search method and device. The method comprises the following steps: sending the coefficient of an error polynomial, which is registered in a coefficient register set, to an initial constant multiplier set in a clock cycle, and further outputting the output result of the initial constant multiplier set and the output intermediate result of a public parallel constant multiplier set into the public parallel constant multiplier set through an initial value selector set to perform parallel Galois field multiplication operation on n positions of a code block; then respectively performing Galois field summing operation on the Galois field multiplication operation results in the corresponding positions in the n positions of the code block in a multi-input adder set; further comparing the Galois field summing operation result with the coefficient sigma 0 of the error polynomial in a comparator set and judging the positions of effective errors in the n positions of the code block; and in the process, simultaneously storing the corresponding result of the public parallel constant multiplier set for being output to the public parallel constant multiplier set through the initial value selector set from the beginning of the second-round Chien search. According to the method disclosed by the invention, the search period can be shortened, the method is compatible with a variety of error correction capabilities, and the construction cost of a circuit is saved.
Description
Technical field
The present invention relates to digital communicating field, relate in particular to a kind of high-efficient low-delay parallel Chien search method and device, can be widely used in the error correction decode technology.
Background technology
Error-correcting code technique is widely used at aspects such as data communication, data storages, and common error correcting code has now: RS (Reed-Solomon, Read-Solomon) code, BCH code, Hamming code, and wherein: Hamming code is less due to code distance, can only correct a bit-errors; RS code, BCH code can be carried out the error correction of many bits, thereby application is very extensive.In the decode procedure of the error correcting codes such as RS code, BCH code, need to be according to error location polynomial (hereinafter to be referred as error polynomial), the position that utilizes the money search to find error code to occur.
The money searching algorithm is by all positions in the traversal code block, the final position of determining wrong generation.The money searching algorithm, namely for accepting code polynomial r (x)=r
0+ r
1X ... + r
N-1x
N-1Pursue bit decoding, wherein, at galois field GF (2
m) middle n=2
m-1.In order to translate r
N-1, decoder check α
N-1Whether is the errors present number, the α reciprocal that namely checks it is the root of error location polynomial σ (x).If α is the root of σ (x), σ is arranged
0+ σ
1α+σ
2α
2+ ... + σ
tα
t=0, wherein t is the rank of error location polynomial.Thus, decoder will be constructed σ
1α, σ
2α
2..., σ
tα
tWhether, and then judge theirs and equal σ
0.Usually, as needs, to translate r
n-i, will check α
iWhether meet σ
0+ σ
1α
i+ σ
2(α
i)
2+ ... + σ
t(α
i)
t=0; According to the additional calculation rule of galois field, whether namely check meets σ
1σ+σ
2σ
2+ ... + σ
2σ
2=σ
0.
Traditional money search method need to be searched for check by turn, specifically adopts the mode of serial process, is also the data that a clock cycle can only process a bit, this method of the many employings of application system that regular software decode system etc. are not high to rate request.But for the high data communication system of data transmission rate request, this has seriously restricted transmission speed.
In order to improve the transmission rate of data, document " 10-and 40-Gb/s Forward Error Correction Devices for Optical Communications-By Leiei Song, Meng-Lin Yu and Michael S.Shaffer " has been mentioned a kind of parallel money search method.The method adopts tree multiplier to realize parallel money search, for GF (2
m) binary BCH codes (n, the k) (n=2 in territory
m-1), it is from highest order r
N-1(n=2
m-1) start to walk abreast money search.Although the method has been accomplished parallel money search, than traditional serial money search circuit, improved efficiency, but because it adopts the mode of tree multiplier, degree of parallelism is larger, the multiplier of cascade is darker, thereby the critical path time delay of circuit is just larger, be not suitable for thus the money searching requirement of high degree of parallelism.
For head it off, paper " Small Area Parallel Chien Search Architectures for Long BCH Codes-By Yanni Chen and Keshab K.Parhi " has been announced a kind of new parallel money search method.The multiplier that the method increases is relatively independent, not cascade, thus the time delay of circuit critical path is fixed, be not subjected to the impact of degree of parallelism.Simultaneously, this circuit compatibility is good, is applicable to any shortening code under same territory.But this money search method is the same with money search method before, remains from high-order r
N-1(n=2
m-1) start to carry out decoding, its search cycle is long.For example,, if for 1K information, carry out the coding and decoding of binary BCH codes, for the code word size 2 that meets BCH code
m-1, adopt GF (2
14) territory while adopting 32 parallel-by-bit account form, if complete the money search of a code word, just need 2
14/ 32=512 clock cycle, therefore can not meet equally the requirement of real-time decoding error correction.
In addition, Zhang Jun mentions a kind of for BCH code (4095 in paper " cascaded code technology and the Study of the Realization thereof in optical fiber communication ", 3591) shortening BCH code (2184,2040) parallel money search circuit, the multiplier of this circuit is also independently, and its critical path delay is little, is not subjected to the impact of degree of parallelism, and search for from the highest order that shortens code, solved thus long problem of search cycle.But there is larger deficiency in this circuit when compatible various error correcting, when compatible other error correcting capabilities of need, the necessary whole circuit of Perfect Reconstruction, cause resource cost larger thus.
Because codec need to adapt to various application scenarios, and but these occasions not only require difference to the error correction figure place, and the proportion that redundant digit accounts for block of information is also had to different restrictions (the Flash chip specification gone out such as current various manufacturers is all different), so high error correction figure place is compatible low error correction figure place directly, thereby for different error correcting capabilities, design the codec chip high cost of different sizes.Thus, be necessary to design a kind of general money search method, to realize the compatibility to various error correcting.
Summary of the invention
In view of this, the invention provides a kind of high-efficient low-delay parallel Chien search method and device, be intended to solve existing long problem of money search method search cycle; And realize that further short-period error correction can join, solve the problem of poor compatibility.
For solving above technical problem, technical scheme provided by the invention is: a kind of parallel money search method of efficient low delay comprises the following steps:
Within a clock cycle, the factor sigma of the error polynomial in the coefficient register group will be deposited with
1, σ
2..., σ
tSend into initial constant multiplier group A
i(in 1≤i≤t), then the intermediate object program of the Output rusults of initial constant multiplier group and public parallel constant multiplier group output is outputed to relatively independent public parallel constant multiplier group B by Initial value choice device group
Ij(in 1≤i≤t, 1≤j≤w), n the position of the realizing code-aiming block galois field multiplying that walks abreast, code length n>=2 wherein, t is specific error correction requirement, w is degree of parallelism;
Respectively the galois field multiplication result of the correspondence position in the n of a code block position is carried out to the galois field summation operation in many input summers group;
Factor sigma by galois field summation operation result and error polynomial
0In comparator bank, compare the effective errors present in n position of judgement code block;
In said process, simultaneously by the storage of the accordingly result of public parallel constant multiplier group, by Initial value choice device group, output to public parallel constant multiplier group for since second, taking turns the money search.
More preferably, the galois field multiplication result of correspondence position in the n of a code block position is stored in the scratch-pad register group.
More preferably, take turns money search since second, the storing value in the scratch-pad register group is delivered in public parallel constant multiplier group by Initial value choice device group, with next n the position of the realizing code-aiming block galois field multiplying that walks abreast;
By many input summers group, respectively the galois field multiplication result of correspondence position is carried out to the galois field summation operation again;
And by the factor sigma of comparator bank by galois field summation operation result and error polynomial
0Make comparisons, the effective errors present in n position of judgement epicycle money search.
More preferably, choose n=2
m-1 long BCH code (n, k, t), choose front 2 on this yard collection
m-1-a-l position is zero code word entirely, removes wherein front 2
m-1-a-l position zero as after code word, form and shorten code (a+l, a, t) code, wherein m is positive integer, m>=3, k is the information bit length of non-shortening binary BCH codes, a is effective information bit length, redundant digit is l=mt.
On this basis, the corresponding parallel money searcher that a kind of efficient low delay is provided of the present invention, comprise coefficient register group, initial constant multiplier group, Initial value choice device group, relatively independent public parallel constant multiplier group, many input summers group and comparator bank, wherein:
The coefficient register group, for the polynomial factor sigma of storage errors
1, σ
2..., σ
t
Initial constant multiplier group A
i(1≤i≤t), within a clock cycle, receive and be deposited with the coefficient of the error polynomial in the coefficient register group and carry out corresponding computing;
Initial value choice device group, optionally output to public parallel constant multiplier group for the intermediate object program of the Output rusults by initial constant multiplier group and the output of public parallel constant multiplier group;
Public parallel constant multiplier group B
Ij(1≤i≤t, 1≤j≤w), be used to n the position of the realizing code-aiming block galois field multiplying that walks abreast, wherein, and code length n>=2, t is specific error correction requirement, w is degree of parallelism; Simultaneously, the accordingly result of this public parallel constant multiplier group is stored, and by Initial value choice device group, outputs to public parallel constant multiplier group for since second, taking turns the money search;
Many input summers group, for carrying out the galois field summation operation by the galois field multiplication result of the correspondence position of the n of a code block position respectively;
Comparator bank, for the factor sigma by galois field summation operation result and error polynomial
0Relatively, the effective errors present in n position of judgement code block.
More preferably, comprise the scratch-pad register group, for the galois field multiplication result of n position correspondence position storing code block.
More preferably, Initial value choice device group, can be used for taking turns the money search, the storing value output in selection scratch-pad register group, the galois field multiplying so that next n position of public parallel constant multiplier group code-aiming block walks abreast since second; By many input summers group, respectively the galois field multiplication result of correspondence position is carried out to the galois field summation operation afterwards; And by the factor sigma of comparator bank by galois field summation operation result and error polynomial
0Make comparisons, the effective errors present in n position of judgement epicycle money search.
More preferably, be the parallel money searcher of the compatible short error correcting capability of long error correcting capability, it arranges a plurality of initial constant multiplier groups, wherein the corresponding a kind of error correction demand of each initial constant multiplier group.
More preferably, comprise error correction requirement selector group, output among Initial value choice device group be used to the result of calculation of the initial constant multiplier group of selecting corresponding error correction demand.
More preferably, be the parallel money searcher of the compatible long error correcting capability of short error correcting capability, the multiplier number in its public parallel constant multiplier group is t
max* w is individual, wherein t
maxFor maximum error correcting capability.
Compared with prior art, high-efficient low-delay parallel Chien search method and device that the present invention adopts a kind of parallel processing and compatible technique to combine, it establishes initial constant multiplier group and relatively independent public parallel constant multiplier group by structure, and for the public parallel constant multiplier group of corresponding round money search, carry out corresponding multiplying by the different initial value inputs of Initial value choice device group selection, can for the code length that shortens code, carry out the money search easily, save thus the search of high l position, greatly shortened the search cycle; On the other hand, when the compatible various error correcting of needs, after for long error correcting capability, having constructed circuit, only needing to increase a small amount of multiplier and some selectors just can implement, and do not need the whole circuit of reconstruct, so just can accomplish the compatibility to short error correcting capability, and also can realize the purpose of the compatible long error correcting capability of short error correcting capability by the multiplier number increased in public parallel constant multiplier group, thereby save widely production cost.
The accompanying drawing explanation
Fig. 1 is the flow chart of the efficient low delay parallel processing of the present invention money search method embodiment;
Fig. 2 is the circuit theory diagrams of the efficient low delay parallel processing of the present invention money searcher embodiment mono-;
Fig. 3 is the circuit theory diagrams of the efficient low delay parallel processing of the present invention money searcher embodiment bis-.
Embodiment
Core concept of the present invention is, structure is established initial constant multiplier group and relatively independent public parallel constant multiplier group in advance, and for the public parallel constant multiplier group of corresponding round money search, carry out corresponding multiplying by the different initial value inputs of Initial value choice device group selection, can for the code length that shortens code, carry out the money search easily, greatly shorten the search cycle thus; In addition, money search method of the present invention and device are compatible good, when multiple error correction requires for compatibility, can pass through resource multiplex, reduce widely device area, to reach the purpose reduced costs, thereby increase on holistic cost and autgmentability.
, clearly explanation full and accurate for ease of the embodiment of the present invention is carried out, at first to the present invention relates to concept and operation principle describes.
1, shorten the code concept
For galois field GF (2
m) binary BCH codes (n, k, the t) (n=2 in territory
m-1), n is code length; K is the information bit length of non-shortening binary BCH codes; T is the error correction requirement, i.e. maximum number of errors, and m is positive integer, m>=3.In actual encoding and decoding, because adding the length (being effective code word size n ') of redundant digit, information bit length often do not meet the code word size n=2 of binary system BCH
m-1, the method usually adopted is to add zero of l position in the high position of information bit, and the code word size after making to encode meets n '+l=n=2
m-1 relation.Thus, binary BCH codes (n ', k ', t) (n '=n-l, k '=k-l) just the be called BCH code of shortening.
2, the parallel money search principle of efficient low delay
The parallel money search of efficient low delay in the present invention, carry out the money search according to the length that shortens code exactly, so just saved the search of high l position, make the iteration cycle of money search shorten to n '/w, wherein w is degree of parallelism, has greatly shortened the money search cycle thus, makes a concrete analysis of as follows:
Under different error correction conditions, shorten the highest order difference of code, the cycle of money search iteration and initial value are also different, therefore should need to require one group of initial constant multiplier A of t structure according to specific error correction by parallel money search method
i(1≤i≤t), and constructed one group of public parallel constant multiplier B
Ij(1≤i≤t, 1≤j≤w).Each public parallel constant multiplier B
IjRelatively independent, namely between each public parallel constant multiplier, there is no cascade, make the time delay of total combinational logic not be subjected to the impact of degree of parallelism.Public parallel constant multiplier group B
Ij(1≤i≤w, after the relevant multiplication result addition of 1≤j≤t) with the factor sigma of error polynomial
0Make comparisons and just can judge whether relevant bits makes mistakes, if comparative result means that for equating this is wrong; Otherwise, error-free.
The parallel money search method of the efficient low delay the present invention relates to and device can be for the binary BCH codes error correction, can correct in the information of a position any t or t with interior random error.For information bit length k, add the redundant digit length l, code length is n=k+l, makes this code length usually not meet the code word size 2 of BCH code (n, k, t)
m-1.Like this, the present invention can choose n=2
m-1 long BCH code, choose a subset (front 2 on this yard collection
m-1-a-l position is zero code word entirely) and remove some part (front 2 of front
m-1-a-l position zero) as code word, form thus and shorten code (a+l, an a, t) code, wherein m is more than or equal to any positive integer of 3, and k is the information bit length of non-shortening binary BCH codes, a is effective information bit length (namely shortening the information digit of code), and redundant digit is l=mt.
Existing from r
N-1(n=2
m-1) start the money search method of parallel search, need 2 while adopting the search of w parallel-by-bit
m/ w clock cycle; And high-efficient low-delay parallel Chien search method of the present invention and device only need (a+l)/w clock cycle.For GF (2
14) shortening code (8528,8192,24) under territory, existing from r
N-1(n=2
m-1) start the money search method of parallel search, need 512 clock cycle while adopting 32 parallel-by-bits to calculate; And high-efficient low-delay parallel Chien search method of the present invention and device only need 267 clock cycle.
The parallel money search method of the efficient low delay after the present invention improves and device can meet the requirement of compatible multiple error correction.Under the error correction condition different, the initial constant multiplier A of structure
i(difference of 1≤i≤t), and public parallel constant multiplier B
Ij(1≤i≤t, the number of 1≤j≤w) only with degree of parallelism and error correction require relevant, the obvious constant multiplier B that needs of the identical duration error correcting capability of degree of parallelism
IjNumber than short error correcting capability need many.Therefore, during the compatible short error correcting capability of long error correcting capability, only need add initial value counting circuit and certain control circuit, namely only need to be for the different initial constant multiplier of error correction increase in demand A
i, then increase by a group selector and get final product.If, during the compatible long error correcting capability of short error correcting capability, by rule, increase public parallel constant multiplier B
IjNumber, make its number meet t
max* w gets final product.
In order to make those skilled in the art understand better technical scheme of the present invention, the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Referring to Fig. 1, mean a preferred embodiment of high-efficient low-delay parallel Chien search method of the present invention.This high-efficient low-delay parallel Chien search method mainly comprises the following steps:
(1) within a clock cycle, by the factor sigma of error polynomial
1, σ
2..., σ
tDeliver to initial constant multiplier group, again the intermediate object program of the Output rusults of initial constant multiplier group and the output of public parallel constant multiplier group is outputed to relatively independent public parallel constant multiplier group by Initial value choice device group and multiply each other, the individual position of n (wherein n>=2) of the realizing code-aiming block galois field multiplying that walks abreast; Simultaneously, deposit for the correlated results of the galois field multiplying of correspondence position in n position of code block, by Initial value choice device group, output to public parallel constant multiplier group for use in since second, taking turns the money search.
(2) the galois field multiplication result of the correspondence position in the n of a code-aiming block position carries out summation operation respectively.
(3) by described summation operation result and error polynomial factor sigma
0Make comparisons, the effective errors present in n position of the described code block of judgement, be errors present while namely equating.
(4) wherein: take turns money search since second, the value of preserving in register is delivered to public parallel constant multiplier group as initial value and multiply each other, next n the position of the realizing code-aiming block galois field multiplying that walks abreast; Again the galois field multiplication result of correspondence position is carried out to summation operation, according to described summation operation result and error polynomial factor sigma
0Make comparisons, the effective errors present in n position of judgement epicycle money search.
The present invention takes turns money search from second, the value of preserving in the scratch-pad register group is delivered to public parallel constant multiplier group as initial value and multiply each other, and can make technical solution of the present invention more perfect.Its reason is: because code word size n is very large, can not search for once taking turns; The general parallel figure place w=32 selected, namely one take turns and only searched 32, and when search first round is that the result of initial constant multiplier is sent into to the galois field computing that walks abreast of public parallel constant multiplier group, second takes turns that to start be that the intermediate object program of storage is sent into to public parallel constant multiplier group.So on this kind meaning, no matter only have a kind of error correction demand or compatible multiple error correction demand, this is all a basic step, indispensable.
Fig. 1 demonstrates a complete flow process of the parallel money search method of the efficient low delay of the present invention, specifically comprises the steps:
S101, the coefficient of error polynomial is delivered in initial constant multiplier group and carried out the galois field multiplying, in order to obtain the multiplication result of initial constant.
S102, by Initial value choice device group: when first round money search, select the result of initial constant multiplier to output to public parallel constant multiplier group as initial value; Second, take turns the intermediate object program that money search preserves in starting to select the scratch-pad register group and output to public parallel constant multiplier group as initial value.
The galois field multiplying that walks abreast of S103, n the position of realizing code-aiming block in public parallel constant multiplier group.
The corresponding intermediate object program of S104, the constant multiplier group that will walk abreast computing is preserved, and starts by Initial value choice device group, to output to public parallel constant multiplier group as initial value in order to take turns the money search second; This mode, for parallel preserving type, can certainly consider serial mode, but its efficiency is lower.Usually, the corresponding intermediate object program of parallel constant multiplier group computing is kept in the scratch-pad register group; Also can consider this intermediate object program is kept in readable and writable memory (RAM), but, because the product circuit area that adopts the method is large, cost is higher, not advise using.
S105, the galois field multiplication result of the n of a code block position is carried out to the galois field summation operation.
S106, by the factor sigma of galois field summation operation result and error polynomial
0Make comparisons, the effective errors present in n position of judgement code block.
S107, judge whether to carry out the search of next round money, if return to step S102; Otherwise, after completing search, exit.
In the present embodiment, can choose n=2
m-1 long BCH code (n, k, t), choose front 2 on this yard collection
m-1-a-l position is zero code word entirely, removes wherein front 2
m-1-a-l position zero as after code word, form and shorten code (a+l, a, t) code, wherein m is positive integer, m>=3, k is the information bit length of non-shortening binary BCH codes, a is effective information bit length, redundant digit is l=mt.Like this, after by structure, establishing initial constant multiplier group and relatively independent public parallel constant multiplier group, just can start to carry out the money search from the highest order of this shortening code, save thus the search of high l position, thereby shortened the search cycle widely.
On this basis, the present invention provides a kind of parallel money searcher of efficient low delay simultaneously, below further is specifically described.
Embodiment mono-
Referring to Fig. 2, mean the circuit theory diagrams of parallel money searcher first embodiment of the efficient low delay of the present invention.The described device of this embodiment is basic model of the present invention, is adapted to only have a kind of situation of error correction requirement.This device comprises the first register group (coefficient register group) the 11, first constant multiplier group (initial constant multiplier group) 12, one selector group (Initial value choice device group) the 13, second register group (scratch-pad register group) the 14, second constant multiplier group (public parallel constant multiplier group) 15, the group of input summer more than one 16 and a comparator bank 17, and wherein: function and the course of work of each device are as follows:
The first register group 11, be used to depositing the factor sigma of error polynomial
1, σ
2..., σ
t
The first constant multiplier group 12, i.e. initial constant multiplier A
i, the coefficient calculations result of error polynomial is cascaded to an input of selector group 13;
The second register group 14, be used to depositing intermediate object program, in order to, for the second constant multiplier group 15 computings, can save computing time;
The second constant multiplier group 15, i.e. public parallel constant multiplier group B
Ij(1≤i≤t, 1≤j≤w), it is input as the output r of selector group 13;
Many input summers group 16, to constant multiplier B
Ij(1≤i≤t, the correlated results of 1≤j≤w) is sued for peace;
The parallel money searcher of the efficient low delay that the present embodiment one relates to can be for the binary BCH codes error correction, can correct in the information of a position any t or t with interior random error.
As shown in Figure 2 realize circuit, the concrete search procedure of this device is: at first by the factor sigma of error polynomial
1, σ
2..., σ
72Be stored in the first register group 11, then by σ
kSend into the first constant multiplier group 12 and carry out multiplying, by selector group 13, the intermediate object program of the Output rusults of the first constant multiplier group 12 and the second constant multiplier group 15 outputs optionally is input to the second constant multiplier group 15 again, in order to realize calculating σ
k(α
i)
k, the most relevant multiplication result of calculation of the second constant multiplier group 15 is sent into each adder and is sued for peace to realize
Result and the error polynomial factor sigma of summation
0Compare and can judge whether this position makes mistakes, mean it is the root of error polynomial if equate, make mistakes in this position, otherwise error-free.In this process, simultaneously the relevant intermediate object program of the second constant multiplier group 15 outputs is stored in the second register group 14, for next round money, search for.When selector group 13 is searched at first round money, select the result of output the first constant multiplier 12, since second, take turns the money search and all export the intermediate object program value of preserving in the second register group 14.
Embodiment bis-
Referring to Fig. 3, mean the circuit theory diagrams of parallel money searcher second embodiment of the efficient low delay of the present invention.The parallel money searcher that the present embodiment two can be joined for a kind of short-period error correction, can meet compatible multiple error correction requirement.The parallel money searcher that described short-period error correction can be joined comprises the first register group 11, the first constant multiplier group 121,122,123......, first selector group (Initial value choice device) 13, second selector group (error correction requires the selector group) the 18, second register group 14, the second constant multiplier group 15, the group of input summer more than one 16 and a comparator bank 17.The present embodiment two has increased second selector group 18 and a plurality of the first constant multiplier group, and other parts are identical with embodiment mono-, below concise and to the point the description implement the device increased in two.
When the compatible short error correcting capability of long error correcting capability, need add initial value counting circuit and certain control circuit: (1) is at first for different error correction increase in demand constant multiplier A
i, the error correction increase in demand constant multiplier group 122 that namely basis increases newly on the basis of original constant multiplier group 121, constant multiplier group 123......; (2) increase one group of second selector group 18 again, output to first selector group 13 for the result of selecting to input constant multiplier group 121 or constant multiplier group 122 or other constant multiplier group, detailed circuit is shown in Fig. 3.
If during the compatible long error correcting capability of short error correcting capability, needing more increases public parallel constant multiplier B by rule
Ij, make the multiplier number in its parallel constant multiplier group meet t
max* w, t wherein
maxFor maximum error correcting capability.
That is to say, when the multiple error correction of compatibility required, money searcher of the present invention only needed to construct a small amount of multiplier and some selectors after according to long error correcting capability, having constructed circuit, just can accomplish the compatibility to short error correcting capability; And increase constant multiplier B by rule
IjAfter, also can realize the compatible long error correcting capability of short error correcting capability.
As can be seen here, the present invention, when realizing that error correcting capability is compatible, does not need the whole circuit of reconstruct, thereby has saved widely production cost.
Be below only the preferred embodiment of the present invention, it should be pointed out that above-mentioned preferred implementation should not be considered as limitation of the present invention, protection scope of the present invention should be as the criterion with the claim limited range.For those skilled in the art, without departing from the spirit and scope of the present invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. the parallel money search method of an efficient low delay, is characterized in that, comprises the following steps:
Within a clock cycle, the factor sigma of the error polynomial in the coefficient register group will be deposited with
1, σ
2..., σ
tSend into initial constant multiplier group A
i(in 1≤i≤t), then the intermediate object program of the Output rusults of initial constant multiplier group and public parallel constant multiplier group output is outputed to relatively independent public parallel constant multiplier group B by Initial value choice device group
Ij(in 1≤i≤t, 1≤j≤w), n the position of the realizing code-aiming block galois field multiplying that walks abreast, code length n>=2 wherein, t is specific error correction requirement, w is degree of parallelism;
Respectively the galois field multiplication result of the correspondence position in the n of a code block position is carried out to the galois field summation operation in many input summers group;
Factor sigma by galois field summation operation result and error polynomial
0In comparator bank, compare the effective errors present in n position of judgement code block;
In said process, simultaneously by the storage of the accordingly result of public parallel constant multiplier group, by Initial value choice device group, output to public parallel constant multiplier group for since second, taking turns the money search.
2. the parallel money search method of efficient low delay as claimed in claim 1, is characterized in that, the galois field multiplication result of correspondence position in the n of a code block position is stored in the scratch-pad register group.
3. the parallel money search method of efficient low delay as claimed in claim 2, is characterized in that,
Take turns money search since second, the storing value in the scratch-pad register group is delivered in public parallel constant multiplier group by Initial value choice device group, with next n the position of the realizing code-aiming block galois field multiplying that walks abreast;
By many input summers group, respectively the galois field multiplication result of correspondence position is carried out to the galois field summation operation again;
And by the factor sigma of comparator bank by galois field summation operation result and error polynomial
0Make comparisons, the effective errors present in n position of judgement epicycle money search.
4. as the parallel money search method of claim 1,2 or 3 described efficient low delays, it is characterized in that, choose n=2
m-1 long BCH code (n, k, t), choose front 2 on this yard collection
m-1-a-l position is zero code word entirely, removes wherein front 2
m-1-a-l position zero as after code word, form and shorten code (a+l, a, t) code, wherein m is positive integer, m>=3, k is the information bit length of non-shortening binary BCH codes, a is effective information bit length, redundant digit is l=mt.
5. the parallel money searcher of an efficient low delay, is characterized in that, comprises coefficient register group, initial constant multiplier group, Initial value choice device group, relatively independent public parallel constant multiplier group, many input summers group and comparator bank, wherein:
The coefficient register group, for the polynomial factor sigma of storage errors
1, σ
2..., σ
t
Initial constant multiplier group A
i(1≤i≤t), within a clock cycle, receive and be deposited with the coefficient of the error polynomial in the coefficient register group and carry out corresponding computing;
Initial value choice device group, optionally output to public parallel constant multiplier group for the intermediate object program of the Output rusults by initial constant multiplier group and the output of public parallel constant multiplier group;
Public parallel constant multiplier group B
Ij(1≤i≤t, 1≤j≤w), be used to n the position of the realizing code-aiming block galois field multiplying that walks abreast, wherein, code length n>=2,
tFor specific error correction requirement, w is degree of parallelism; Simultaneously, the accordingly result of this public parallel constant multiplier group is stored, and by Initial value choice device group, outputs to public parallel constant multiplier group for since second, taking turns the money search;
Many input summers group, for carrying out the galois field summation operation by the galois field multiplication result of the correspondence position of the n of a code block position respectively;
Comparator bank, for the factor sigma by galois field summation operation result and error polynomial
0Relatively, the effective errors present in n position of judgement code block.
6. the parallel money searcher of efficient low delay as claimed in claim 5, is characterized in that, comprises the scratch-pad register group, for the galois field multiplication result of n position correspondence position storing code block.
7. the parallel money searcher of efficient low delay as claimed in claim 6, it is characterized in that, Initial value choice device group, can be used for taking turns the money search since second, select the storing value output in the scratch-pad register group, the galois field multiplying so that next n position of public parallel constant multiplier group code-aiming block walks abreast; By many input summers group, respectively the galois field multiplication result of correspondence position is carried out to the galois field summation operation afterwards; And by the factor sigma of comparator bank by galois field summation operation result and error polynomial
0Make comparisons, the effective errors present in n position of judgement epicycle money search.
8. as the parallel money searcher of efficient low delay as described in claim 5～7 any one, it is characterized in that, for the parallel money searcher of the compatible short error correcting capability of long error correcting capability, it arranges a plurality of initial constant multiplier groups, wherein the corresponding a kind of error correction demand of each initial constant multiplier group.
9. the parallel money searcher of efficient low delay as claimed in claim 8, is characterized in that, comprises error correction requirement selector group, outputs among Initial value choice device group be used to the result of calculation of the initial constant multiplier group of selecting corresponding error correction demand.
10. as the parallel money searcher of efficient low delay as described in claim 5～7 any one, it is characterized in that, is the parallel money searcher of the compatible long error correcting capability of short error correcting capability, and the multiplier number in its public parallel constant multiplier group is t
max* w is individual, wherein t
maxFor maximum error correcting capability.
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| CN111694692B (en) * | 2020-06-24 | 2022-04-22 | 山东云海国创云计算装备产业创新中心有限公司 | Data storage erasure method, device and equipment and readable storage medium |
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