CN102546089A - Method and device for implementing cycle redundancy check (CRC) code - Google Patents

Method and device for implementing cycle redundancy check (CRC) code Download PDF

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CN102546089A
CN102546089A CN2011100004827A CN201110000482A CN102546089A CN 102546089 A CN102546089 A CN 102546089A CN 2011100004827 A CN2011100004827 A CN 2011100004827A CN 201110000482 A CN201110000482 A CN 201110000482A CN 102546089 A CN102546089 A CN 102546089A
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crc
parallel
code
bit
data
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CN102546089B (en
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杨锋
陈思思
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中兴通讯股份有限公司
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Abstract

The invention relates to a method and a device for implementing a cycle redundancy check (CRC) code. The implementing method comprises the following steps of: preprocessing information codes input in parallel and acquiring an effective data bit; selecting a current effective CRC register bit from a CRC code obtained from precious CRC parallel computation; and performing at least one exclusive-or operation on the effective data bit and the current effective CRC register bit to obtain a new CRC code. Through data bit preprocessing and CRC register bit feedback processing, a parallel CRC processing effect on an information bit of any bit width can be achieved, the operation performance of a CRC generating and verifying system is enhanced, logic resources are saved greatly under the condition of meeting a high-speed CRC data processing requirement, the implementation cost is reduced, and flexibility and compatibility are enhanced.

Description

循环冗余校验CRC码的实现方法及装置 Implementation of CRC code is a cyclic redundancy check and means

技术领域 FIELD

[0001] 本发明涉及通信领域,尤其涉及一种循环冗余校验CRC码的实现方法及装置。 [0001] The present invention relates to communication field, and particularly relates to a method and apparatus to realize a cyclical redundancy check CRC code. 背景技术 Background technique

[0002] 为了通信系统中可靠性传输,人们采用差错控制技术,其中最常用的是循环冗余校验(Cyclic Redundancy Check, CRC)。 [0002] The transmission reliability for a communication system, error control techniques employed people, is the most commonly used cyclic redundancy check (Cyclic Redundancy Check, CRC).

[0003] CRC原理基于线性编码理论。 [0003] CRC principles based on linear coding theory. 发送端将要传送的k位信息码序列,以一定规则产生r位校验码(CRC码),附在信息码后构成(k+r)位发送序列。 transmitting the k-bit information end code sequence to be transmitted, to generate a certain rule r check code (CRC code), the transmission bit sequence constituting the information code attached to the (k + r). 接收端根据CRC码生成规则进行校验,判断传送过程是否出错。 Receiving end according to the CRC check code generation rules is determined whether an error occurred during transmission.

[0004] 例如,待传送的k位二进制信息码序列为D = {d[kl]d[k-2]......d[l]d[0]}, [0004] For example, k-bit binary information code sequence to be transmitted is D = {d [kl] d [k-2] ...... d [l] d [0]},

将序列D左移r位,除以一个(r+Ι)位的生成多项式,得到r位的余式R= {r[rl] D left sequence of r bits, divided by a (r + Ι) bit generator polynomial to obtain a remainder of r bits R = {r [rl]

r[r-2]......r[l]r[0]},将余式R作为序列D的CRC码,生成发送序列M = {d[kl] r [r-2] ...... r [l] r [0]}, the formula I R D as a CRC code sequence, generating a transmission sequence M = {d [kl]

d[k-2]......d[l]d[0]r[rl]r[r-2]......r[l]r[0]}。 d [k-2] ...... d [l] d [0] r [rl] r [r-2] ...... r [l] r [0]}.

[0005] 实际应用中,CRC的实现方法有串行计算和并行计算。 [0005] In practical applications, CRC calculation-implemented method with a serial and parallel computing. 串行计算电路由线性反馈移位寄存器和异或运算逻辑组成。 A serial circuit by the calculated linear feedback shift register and an exclusive OR logic operation composition. 特点为:逐位计算,每个时钟周期输入1比特信息码。 Characterized by: computing a bitwise, 1 bit per clock period of the input information code. 经过k个时钟周期,得到CRC码。 After k clock cycles, to obtain a CRC code. 以CRC-32为例说明,串行计算电路如图1所示。 To CRC-32 as an example, a serial calculation circuit shown in Fig.

[0006] 典型并行计算电路由异或运算逻辑和CRC寄存器反馈电路组成。 [0006] A typical parallel computing circuit by the exclusive logical sum computing CRC register feedback circuit. 特点为将信息码划分为长为H(KnSk)比特的若干数据块,每个时钟周期输入η比特信息码。 It characterized the information code length divided into several data blocks H (KnSk) bits per clock period of the input code bit information η. 根据串行计算方法中各线性反馈移位寄存器与输入信息码的变化关系推导出的逻辑关系式,每次 Derived according to the calculation method for each serial linear feedback shift register that changes with the input information code logic relation, each

计算η比特信息码的CRC码,通过(+ 1 )个时钟周期计算得到整个待发送信息码的最终 Η calculated CRC code bit information code, by (+ 1) clock cycles is calculated to obtain a final code information to be transmitted throughout the

CRC码。 CRC code. 缺点为CRC计算电路的计算宽度固定。 Disadvantage of the CRC calculation circuit is fixed width. 当要支特任意长信息码的CRC计算时,需要η路CRC并行计算逻辑。 When the CRC for a branched Laid arbitrarily long code information, the needs η path parallel CRC calculation logic. 如图2为典型CRC并行计算电路结构。 FIG 2 is a typical circuit configuration of the parallel computing CRC.

[0007] 但是现有技术中,CRC串行计算为每次只能计算1比特信息码,效率低,无法满足高速率数据传送的CRC生成、校验处理。 [0007] However, the prior art, is calculated for each serial CRC calculation only 1-bit information code, inefficient, can not satisfy the high rate data transmission of CRC generation, verification process. 虽然CRC并行计算速度快,但现有技术的并行计算中对应不同的逻辑关系式而位宽η也不同,则一路CRC并行计算逻辑的固定计算位宽,无法应用于其它位宽的CRC并行计算。 Although the parallel CRC calculation speed, but parallel computing the prior art correspond to different bit width of the logical relationship η is different, all the way to the CRC calculation logic in parallel fixed bit width calculation can not be applied to other bit wide parallel CRC calculation . 例如,η位并行电路计算k位信息码的CRC码,必须满足条件:k能整除n,即(k% η = 0)。 For example, [eta] bit parallel CRC code calculation circuit code information of k bits, must satisfy the condition: k divisible by n, i.e. (k% η = 0). 若不满足整除条件,则最后一次计算输入的信息码位宽为(k%n),范围为(1〜η-1),η位并行计算的逻辑电路无法计算最终CRC码。 Divisible conditions not satisfied, the last calculated information code input bit width of (k% n), the range (1~η-1), η-bit parallel logic circuit can not calculate a final calculation of the CRC code. 因此,计算任意长信息码的CRC码,则需要η套并行位宽分别为(1〜η)的逻辑电路。 Thus, the CRC code calculating arbitrary code length information, the bit width of the parallel sets need η (1~η) logic circuits, respectively. 但是,随着数据传送速率的不断提高,CRC并行计算位宽也不断增加。 However, with the increasing data transfer rate, CRC bit width parallel computing is increasing. 当计算位宽η较大时资源消耗非常大,并且不同计算位宽的逻辑电路间的切换控制电路也越来越复杂。 When calculating the bit width η large resource consumption is very large, and switching between different computing bit width logic control circuit is also more complex.

发明内容 SUMMARY

[0008] 本发明的主要目的是提供一种循环冗余校验CRC码的实现方法及装置,旨在使得校验CRC码实现过程中,既占用更少的资源,又提高了其性能。 [0008] The main object of the present invention is to provide a cyclic redundancy check CRC code implemented method and apparatus, intended to make the CRC check the implementation process, not only takes up less resources, but also improves its performance.

[0009] 本发明提供了一种循环冗余校验CRC码的实现方法,包括以下步骤:[0010] 对并行输入的信息码进行预处理,并获得其有效数据位; [0009] The present invention provides a method for implementing a cyclic redundancy check (CRC) code, comprising the steps of: [0010] code information input in parallel preprocessing, and obtain the data bits;

[0011] 从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位; [0011] calculated from the time obtained by parallel CRC code CRC and CRC register bit selects the currently active;

[0012] 将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 [0012] and the data bits of the current valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code.

[0013] 优选地,上述对并行输入的信息码进行预处理,并获得其有效数据位的步骤具体包括: [0013] Preferably, the above step information codes input in parallel preprocessing and obtain the valid data bits comprises:

[0014] 根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,将并行输入的信息码进行整形处理,获得数据块; [0014] CRC for shaping circuit and the maximum bit width parallel computing information codebook bit width parallel computations, the calculated parallel input in parallel, to obtain a data block;

[0015] 根据CRC并行计算电路最大并行计算位宽或者本次并行计算位宽对应的CRC并行计算逻辑关系式,从所述数据块中选出有效数据位。 [0015] The parallel CRC calculation circuit calculates the maximum bit width parallel or parallel computing this bit width corresponding to the CRC calculation logic in parallel relationship, from the selected data bits in the data block.

[0016] 优选地,上述整形处理包括: [0016] Preferably, the shaping process comprises:

[0017] 根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,对并行输入信息码高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn) ' b0, d[Vn-l:0]}数据块,其中η为最大并行计算位宽,Vn为本次并行计算位宽;尤其 [0017] CRC bit width parallel computing circuit and the maximum of this parallel bits of parallel computing, calculated on the parallel input information symbols high zero padding or cleared, shaping the parallel input information code bits for η {(n- Vn) 'b0, d [Vn-l: 0]} of data blocks, where η is the maximum bit width parallel computing, Vn oriented parallel computations bits wide; in particular,

[0018] 当并行输入信息码位宽等于最大并行计算位宽η时,整形处理也可以直接对并行输入信息码进行透传,则整形后的数据块仍为输入的信息码。 [0018] When the parallel input information code bit width parallel computing the maximum bit width is equal to η, shaping may be directly input information in parallel through transmission code information code, the data block is still shaping input.

[0019] 优选地,上述从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位的步骤具体为: [0019] Preferably, the step of computing a CRC parallel CRC code obtained by selecting the currently active CRC register bit to the specific:

[0020] 根据本次并行计算位宽所对应的寄存器位系数,从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位。 [0020] According to this bit wide parallel register bit corresponding to the coefficient calculation, is obtained from a parallel computing the CRC code CRC and CRC register bit selects the currently active.

[0021] 优选地,上述将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码的步骤之后还包括: After [0021] Preferably, the above-described data bits of the current and valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code further comprises the step of:

[0022] 判断所述并行输入的信息码是否为最后一次数据输入,是则将所述新的CRC码记为最终的CRC码;否则返回执行对并行输入的信息码进行预处理,并获得其有效数据位的步骤。 [0022] The parallel information determining whether the input code is the last data entry, a new CRC code is then referred to as the final CRC code; otherwise, execution code information input in parallel preprocessing and obtain the the step of valid data bits.

[0023] 本发明还提供了一种循环冗余校验CRC码的实现装置,包括: [0023] The present invention further provides an apparatus for implementing a cyclic redundancy check (CRC) code, comprising:

[0024] 数据位预处理模块,用于对并行输入的信息码进行预处理,并获得其有效数据位; [0024] Bit data pre-processing module, configured to code the information input in parallel preprocessing, and obtain the data bits;

[0025] CRC寄存器反馈选择模块,用于从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位; [0025] Feedback CRC register selection module for parallel computing CRC from the CRC code to obtain a selected current valid CRC register bit;

[0026] 异或运算模块,用于将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 [0026] XOR operation means for said data bits of the current and valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code.

[0027] 优选地,上述数据位预处理模块具体包括: [0027] Preferably, said data bits preprocessing module comprises:

[0028] 整形单元,用于根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽, 将并行输入的信息码进行整形处理,获得数据块; [0028] The shaping means for shaping the CRC processing circuit and the maximum bit width parallel computing information codebook bit width parallel computations, the calculated parallel input in parallel, to obtain a data block;

[0029] 选择单元,用于根据CRC并行计算电路最大并行计算位宽或者根据本次并行计算位宽对应的CRC并行计算逻辑关系式,从所述数据块中选出有效数据位。 [0029] a selecting unit, the parallel CRC computation circuit for computing the maximum bit width parallel relation or in parallel according to the calculation logic of parallel computations corresponding to CRC bits wide, valid data bits from the selected data block according to.

[0030] 优选地,上述整形单元进行整形处理具体为: [0030] Preferably, the shaping unit performs shaping is specifically:

[0031] 根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,对并行输入信息码高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn) ' b0, d[Vn-l:0]}数据块,其中η为最大并行计算位宽,Vn为本次并行计算位宽;尤其 [0031] CRC bit width parallel computing circuit and the maximum of this parallel bits of parallel computing, calculated on the parallel input information symbols high zero padding or cleared, shaping the parallel input information code bits for η {(n- Vn) 'b0, d [Vn-l: 0]} of data blocks, where η is the maximum bit width parallel computing, Vn oriented parallel computations bits wide; in particular,

[0032] 当并行输入信息码位宽等于电路最大并行计算位宽时,整形处理也可以直接对并行输入信息码进行透传,则整形后的数据块仍为输入的信息码。 [0032] When the bit width of the parallel input information symbols is equal to the maximum bit width parallel computing, shaping may be directly parallel input information symbols transmitted transparently, the data block is still shaping the input information code.

[0033] 优选地,上述CRC寄存器反馈选择模块具体用于:根据本次需要计算位宽所对应的寄存器位系数,从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位。 [0033] Preferably, the CRC register feedback selection module is configured to: according to this register bit coefficient is necessary to calculate the corresponding bit wide, parallel CRC calculation obtained from a CRC code CRC register select bits currently active.

[0034] 优选地,上述循环冗余校验CRC码的实现装置还包括: [0034] Preferably, the cyclic redundancy check CRC code implemented apparatus further comprising:

[0035] 循环模块,用于判断所述并行输入的信息码是否为最后一次数据输入,是则将所述新的CRC码记为最终的CRC码;否则返回执行对并行输入的信息码进行预处理,并获得其有效数据位的步骤。 [0035] The cycle module configured to determine a parallel information whether the input code is the last data input, then the new CRC code is referred to as the final CRC code; otherwise, execution code information input in parallel pre processing steps and obtains valid data bits.

[0036] 本发明循环冗余校验CRC码的实现方法及装置,通过数据位预处理和CRC寄存器位反馈处理,达到了可进行任意位宽信息码的并行CRC处理的效果,从而解决了现有技术串行电路每个时钟周期只能计算一位信息码,而并行电路计算位宽固定、逻辑大、控制复杂的问题。 [0036] The method and apparatus achieve a cyclic redundancy check CRC code of the present invention, by pre-processing the data bits and CRC register bit feedback process, to the effect of any bit width information code may be parallel CRC processing, thereby solving the current art serial circuit of each clock cycle calculating an information code only, whereas the parallel circuit calculates a fixed bit width, large logic, complex control problem. 而且,本发明还能够提高CRC生成、校验系统的运算性能,在满足高速CRC数据处理需求下,大大节省了逻辑资源,降低了实现成本,提高了灵活性、兼容性。 Further, the present invention also can improve operational performance of CRC generation, verification system, to meet the demand for high-speed data processing CRC, the logic resources saving, reduces the implementation costs, increase flexibility, compatibility.

附图说明 BRIEF DESCRIPTION

[0037] 图1是现有技术中CRC码的串行计算电路的结构示意图; [0037] FIG. 1 is a schematic structural diagram of a serial CRC code calculation circuit of the prior art;

[0038] 图2是现有技术中CRC码的典型并行计算电路的结构示意图; [0038] FIG. 2 is a schematic view of a typical parallel CRC code calculation circuit of the prior art;

[0039] 图3是本发明循环冗余校验CRC码的实现方法一实施例的流程示意图; [0039] FIG. 3 is a schematic flow diagram of the present invention, a cyclic redundancy check CRC code implementation of one embodiment;

[0040] 图4是本发明循环冗余校验CRC码的实现方法中数据位预处理的流程示意图; [0040] FIG. 4 is a schematic flow diagram of a method to achieve the present invention, cyclic redundancy check CRC code bits in the data preprocessing;

[0041] 图5是本发明循环冗余校验CRC码的实现方法另一实施例的流程示意图; [0041] FIG. 5 is a schematic flow diagram of the present invention, a cyclic redundancy check code CRC-implemented method according to another embodiment;

[0042] 图6是本发明循环冗余校验CRC码的实现装置一实施例的结构示意图; [0042] FIG. 6 is a schematic structural diagram of the present invention, a cyclic redundancy check CRC code of the apparatus for implementing an embodiment;

[0043] 图7是本发明循环冗余校验CRC码的实现装置一实施例中数据位预处理模块的结构示意图; [0043] FIG. 7 is a schematic structural diagram of the present invention, a cyclic redundancy check CRC code device for implementing an embodiment of the data bit preprocessing module embodiment;

[0044] 图8是本发明循环冗余校验CRC码的实现装置另一实施例的结构示意图。 [0044] FIG. 8 is a block diagram of another embodiment of apparatus for implementing the present invention, cyclic redundancy check CRC code.

[0045] 本发明目的的实现、功能特点及优点将结合实施例,参照附图做进一步说明。 The object of the invention is achieved [0045] The present, features and advantages of the embodiments in conjunction with embodiments, with reference to the drawings further described.

具体实施方式 Detailed ways

[0046] 以下结合说明书附图及具体实施例进一步说明本发明的技术方案。 [0046] The following further illustrate the technical solutions in conjunction with the accompanying drawings of the present invention and embodiments.

[0047] 应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 [0047] It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention.

[0048] 本发明提供了一种循环冗余校验CRC码的实现方法及装置,可以支持任意计算位宽的信息码的CRC码计算。 [0048] The present invention provides a method and apparatus for implementing a cyclic redundancy check CRC code, the CRC code information code can support an arbitrary bit width calculation calculation.

[0049] 图3是本发明循环冗余校验CRC码的实现方法一实施例的流程示意图。 [0049] FIG. 3 is a schematic flow diagram of a method to achieve a cyclic redundancy check CRC code according to an embodiment of the invention.

[0050] 本实施例循环冗余校验CRC码的实现方法,包括以下步骤: [0050] The method of the present embodiment to achieve a cyclic redundancy check CRC code comprising the steps of:

[0051] 步骤S10、对并行输入的信息码进行预处理,并获得其有效数据位; [0051] Step S10, the code information input in parallel preprocessing, and obtain the data bits;

[0052] 步骤S11、从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位; [0052] step S11, the parallel CRC calculated from the time obtained by selecting the currently active CRC code CRC register bit;

[0053] 步骤S12、将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 [0053] step S12, and the valid bit of the current active data and CRC register bit exclusive-OR operation at least once, to obtain the new CRC code. [0054] 本实施例循环冗余校验CRC码的实现方法,通过数据位预处理和CRC寄存器位反馈处理,达到了可进行任意位宽信息码的并行CRC处理的效果,从而解决了现有技术串行电路每个时钟周期只能计算一位信息码,而并行电路计算位宽固定、逻辑大、控制复杂的问题。 [0054] Example implementations cyclic redundancy check CRC code of the present embodiment, pre-processing the data bits and CRC register bit feedback process, can achieve the effect of any bit width parallel CRC processing information code, thereby solves technical serial circuit of each clock cycle calculating an information code only, whereas the parallel circuit calculates a fixed bit width, large logic, complex control problem. 而且,本发明还能够提高CRC生成、校验系统的运算性能,在满足高速CRC数据处理需求下,大大节省了逻辑资源,降低了实现成本,提高了灵活性、兼容性。 Further, the present invention also can improve operational performance of CRC generation, verification system, to meet the demand for high-speed data processing CRC, the logic resources saving, reduces the implementation costs, increase flexibility, compatibility.

[0055] 参照图4,上述步骤SlO具体包括: [0055] Referring to FIG. 4, the above step SlO comprises:

[0056] 步骤S101、根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,将并行输入的信息码进行整形处理,获得数据块; [0056] step S101, the CRC for shaping circuit and the maximum bit width parallel computing information codebook bit width parallel computations, the calculated parallel input in parallel, to obtain a data block;

[0057] 假设,信息码序列为(Uk-I : 0],且当次需要计算Vn比特信息码的CRC码,则当次输入信息码为d [Vn-1 : 0],将d [Vn-1 : 0]整形为位宽等于CRC并行计算电路最大计算位宽η的数据块。该数据块结构为低Vn比特为本次输入信息码,高(n-Vn)比特为0,即{(n-Vn)'bO, d[Vn-l:0]}。 [0057] Suppose, information code sequence (Uk-I: 0], and when the time necessary to calculate Vn bit information code CRC code, when the second input information code d [Vn-1: 0], the D [Vn -1: 0] is equal to the bit width shaping circuit block CRC calculated maximum bit width parallel η calculated data block structure is a low bit-oriented sub-Vn code input information, high (n-Vn) bit is 0, i.e., { (n-Vn) 'bO, d [Vn-l: 0]}.

[0058] 步骤S102、根据CRC并行计算电路并行计算位宽或者本次并行计算位宽对应的逻辑关系式,从数据块Kn-Vn) ' b0,d[Vn-l:0]}选出有效数据位。 [0058] Step S102, CRC calculation circuit according to the parallel or parallel computing this bit wide bit width parallel computing corresponding logical relationship, the data from the block Kn-Vn) 'b0, d [Vn-l: 0]} is selected effective data bits.

[0059] 上述整形处理主要包括以下两种实现方法: [0059] The shaping process includes the following two methods:

[0060] 第一种、若数据输入位宽为变化值,根据本次并行计算位宽Vn,对高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn) 'b0,d[Vn-l:0]}数据块,其中η为电路最大并行计算位宽,Vn为本次并行计算位宽;然后,根据最大计算位宽对应的数据位系数d_deX_n[nl:0]从整形后的数据块中选择有效数据位。 [0060] First, if the data input bit width change value, according to the bit width Vn of parallel computations, to high zero padding or cleared, shaping the parallel input information code bits for η {(n- Vn) 'b0, d [Vn-l: 0]} of data blocks, where η is a circuit calculating the maximum bit width parallel, Vn oriented parallel computations bits wide; then calculated according to the data bit width corresponding to the maximum coefficient of d_deX_n [ nl: 0] from the selected data bits in the data block shaping. 实现中选择单元可用选择器直接选出当前有效CRC寄存器位,也可将C_deX_Vn [r-1 : 0]作为滤波器系数,与crc [r-1 : 0] 进行点乘运算,或者其它方式最终选出当前有效CRC寄存器位。 Implementations selecting unit may select directly selecting the currently active register bit CRC, may also be C_deX_Vn [r-1: 0] as a filter coefficient, and crc [r-1: 0] for point multiplication, the final or otherwise select the currently active CRC register bit.

[0061] 第二种、若数据输入位宽等于电路最大并行计算位宽n,而当次计算位宽为VnJlJ 输入信息码也可以不进行补零或清零操作,直接作透传,整形后的数据块仍为输入的信息码d[nl:0];则根据当次计算位宽Vn对应的数据位系数d_deX_Vn[nl:0]从整形后的数据块中选择有效数据位。 After [0061] Second, if the input data bit width is equal to the maximum bit width parallel computing n, and when the bit width of calculations VnJlJ input information code may not be zero-padded or cleared, as a direct pass-through, shaping information code input data block is still d [nl: 0]; the coefficients according to the data bits when the bit width calculations Vn corresponding d_deX_Vn [nl: 0] from the selected data bits in the data block shaping.

[0062] 当然,若数据输入位宽为其他情况时,也可以通过其他方法将输入信息码整形为{(n-Vn) 'b0,d[Vn-l:0]}数据块,并根据最大计算位宽对应的数据位系数选择有效数据位。 [0062] Of course, if the input data bit width is the other case, the information code may be entered by another method of shaping {(n-Vn) 'b0, d [Vn-l: 0]} of data blocks, and in accordance with the maximum calculating the bit width corresponding to the coefficient data to select valid data bits. 若输入信息码进行透传方式的整形处理,则根据当次计算位宽Vn对应的数据位系数选择有效数据位。 If the input code information shaping transparent transmission of valid data bit is selected according to the data when the coefficient bit width Vn corresponding calculations.

[0063] 上述步骤Sll具体为:根据本次计算位宽Vn对应的寄存器位系数C_dex_ Vn [r-1 : 0],从上一输入数据的CRC计算结果的r位CRC码crc [r-1 : 0]中选出参与本次计算的当前有效CRC寄存器位。 [0063] Specifically above step Sll: Vn according to the bit width corresponding to the current calculated coefficient register C_dex_ Vn [r-1: 0], the CRC calculation result from the input data bit CRC code r crc [r-1 : currently active participation in this register bit CRC calculation 0] selected. 实现中选择单元可用选择器直接选出当前有效CRC寄存器位, 也可将C_dex_Vn[rl:0]作为滤波器系数,与crc [r-1:0]进行点乘运算,或者其它方式最终选出当前有效CRC寄存器位。 Implementations selecting unit may select directly selecting the currently active register bit CRC, may also be C_dex_Vn [rl: 0] as a filter coefficient, and crc [r-1: 0] for point multiplication, the final or otherwise selected currently valid CRC register bit.

[0064] 上述步骤S12中,将上述有效数据位与上述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码,并且将该新的CRC码更新至CRC寄存器。 [0064] In step S12, the data of the effective bits of the above-described current valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code, and updates the new CRC code to the CRC register. 本实施例中,可以将有效数据位和当前有效CRC寄存器位一起进行至少一次异或运算,获得新的CRC码;或者也可以先将有效数据位进行至少一次异或运算,获得有效数据位异或结果,再将该有效数据位异或结果与当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 In this embodiment, bits may be valid data and the currently active with at least one CRC register bit exclusive-OR operation to obtain the new CRC code; or may be at least one exclusive OR operation first valid data bit, valid data bits iso or the result, then the valid data bits with the currently active XOR result and CRC register bit exclusive-oR operation at least once, to obtain the new CRC code. 异或运算的次数可以根据具体情况而决定,在此就不做限定。 The number of exclusive-OR operation may be determined depending on the circumstances, this is not defined to do.

[0065] 图5是本发明循环冗余校验CRC码的实现方法另一实施例的流程示意图。 [0065] FIG. 5 is a schematic flow diagram of a method to achieve a cyclic redundancy check CRC code to another embodiment of the present invention.

[0066] 在上述实施例的基础上,本实施例循环冗余校验CRC码的实现方法在上述步骤S12之后还包括: [0066] Based on the foregoing embodiment, the present embodiment is a cyclic redundancy check code CRC-implemented method further comprising after said Step S12:

[0067] 步骤S13、判断上述并行输入的信息码是否为最后一次数据输入,是则执行步骤S14;否则返回执行步骤S10; [0067] step S13, the above information code input in parallel is determined whether the last data entry, step S14 is then executed; otherwise, returns to step SlO;

[0068] 步骤S14、将上述新的CRC码记为最终的CRC码,并结束流程。 [0068] step S14, the above-referred to as the new final CRC code CRC code, and the process ends.

[0069] 当判断上述并行输入的信息码不是最后一次数据输入时,返回执行步骤S10,循环进行CRC并行计算,直到当数据输入结束后,再将获得的CRC码记为最终的CRC码。 [0069] When the above-described determination information input in parallel when the code is not the last data input, execution returns step S10, the parallel CRC calculation cycle until the point when data input, and then obtain the final CRC code referred to as a CRC code.

[0070] 图6是本发明循环冗余校验CRC码的实现装置一实施例的结构示意图。 [0070] FIG. 6 is a schematic structural diagram of apparatus for implementing a cyclic redundancy check CRC code to an embodiment of the present invention.

[0071] 本实施例循环冗余校验CRC码的实现装置,包括: [0071] The apparatus of the present embodiment to achieve a cyclic redundancy check CRC code implemented, comprising:

[0072] 数据位预处理模块10,用于对并行输入的信息码进行预处理,并获得其有效数据位; [0072] 10 bits of data pre-processing module, configured to code the information input in parallel preprocessing, and obtain the data bits;

[0073] CRC寄存器反馈选择模块11,用于从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位; [0073] Feedback CRC register selection module 11, a parallel CRC calculation is obtained from a selected CRC code CRC register bit currently active;

[0074] 异或运算模块12,用于将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 [0074] XOR operation module 12 for the data bits of the current and valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code.

[0075] 参照图7,上述数据位预处理模块10具体包括: [0075] Referring to FIG. 7, the above-described pre-processing module 10 data bits comprises:

[0076] 整形单元101,用于根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,将并行输入的信息码进行整形处理,获得数据块; [0076] The shaping unit 101 for calculating the maximum bit width of the parallel circuit and the current bit width parallel computing, parallel information code inputted shaping process, parallel CRC calculation block is obtained according to;

[0077] 选择单元102,用于根据CRC并行计算电路最大计算位宽或者本次并行计算位宽对应的CRC并行计算逻辑关系式,从数据块中选出有效数据位。 [0077] The selecting unit 102, a parallel CRC calculation logic in parallel relationship is calculated according to the maximum bit width calculation circuit, or the current corresponding to the bit width of parallel CRC calculation, the selected valid data bits from the data block.

[0078] 假设,信息码序列为dDc-l:0],且当次需要计算Vn比特信息码的CRC码,则当次输入信息码为d[Vn-l:0],整形单元101将d[Vn-l:0]整形为位宽等于CRC并行计算电路最大计算位宽η的数据块。 [0078] Suppose, information code sequence dDc-l: 0], and when the time necessary to calculate Vn bit information code CRC code, when the second input information code d [Vn-l: 0], shaping unit 101 d [Vn-l: 0] bit width equal to the CRC for the shaping block calculated the maximum bit width parallel computing circuit η. 该数据块结构为低Vn比特为本次输入信息码,高(n-Vn)比特为0,即{(n-Vn),b0, d[Vn-l:0]}。 The data block structure is a low bit-oriented sub-Vn code input information, high (n-Vn) bit is 0, i.e., {(n-Vn), b0, d [Vn-l: 0]}. 选择单元102再根据最大计算位宽η对应的CRC并行计算逻辑关系式的数据位系数d_dex_n[nl:0]从整形后的η比特数据块{(n-Vn)' b0, d[Vn-l:0]}中选出参与异或计算的有效数据位。 The selection unit 102 then calculates the maximum bit width of the corresponding CRC η parallel calculation coefficient data according to the logical relation d_dex_n [nl: 0] bits from η shaping blocks {(n-Vn) 'b0, d [Vn-l : valid data bits involved in the exclusive oR calculation 0]} selected. 另一种方法,若输入信息码位宽等于电路最大并行计算位宽,输入信息码为d[nl:0],整形单元101透传输入信息码,即整形后的数据块为d[nl :0]。 Another method, if the code bit width equal to the maximum input information bit width parallel computing circuit, the input information code d [nl: 0], the shaping unit 101 through the input transmission information code, i.e., data block shaped to d [nl: 0]. 选择单元102再根据当次计算位宽Vn对应的CRC并行计算逻辑关系式的数据位系数d_deX_Vn[nl:0]从d[nl:0]中选出参与异或计算的有效数据位。 The selection unit 102 then parallel calculation coefficient data bits according logic d_deX_Vn formula Vn when the bit width corresponding to the current calculated CRC [nl: 0] [nl: 0] from the data bits d XOR elected participation.

[0079] 上述整形单元101进行整形处理主要包括以下两种实现方法: [0079] The shaping process shaping unit 101 mainly includes the following two methods:

[0080] 第一种、若数据输入位宽为变化值,根据本次并行计算位宽Vn,对高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn) 'b0,d[Vn-l:0]}数据块,其中η为CRC并行计算电路最大计算位宽,Vn为本次并行计算位宽;然后,根据最大计算位宽对应的数据位系数d_deX_n从整形后的数据块中选择有效数据位。 [0080] First, if the data input bit width change value, according to the bit width Vn of parallel computations, to high zero padding or cleared, shaping the parallel input information code bits for η {(n- Vn) 'b0, d [Vn-l: 0]} of data blocks, where η is the maximum calculation bits of parallel CRC calculation circuit, Vn oriented parallel computations bits wide; then, the data bit width calculation coefficient corresponding to the maximum d_deX_n selected data bits from the data block shaping. 实现中选择单元可用选择器直接选出当前有效CRC寄存器位,也可将C_dex_Vn[rl:0]作为滤波器系数,与crc[rl:0] 进行点乘运算,或者其它方式最终选出当前有效CRC寄存器位。 Implementations selecting unit may select directly selecting the currently active register bit CRC, may also be C_dex_Vn [rl: 0] as a filter coefficient, and crc [rl: 0] for point multiplication or otherwise effective current final selection CRC register bit.

[0081] 第二种、若数据输入位宽等于电路最大并行计算位宽n,而当次计算位宽为Vn,则输入信息码不进行补零或清零操作,直接作透传,整形后的数据块仍为输入的信息码d[nl:0];则根据当次计算位宽Vn对应的数据位系数d_deX_Vn[nl:0]从整形后的数据块中选择有效数据位。 [0081] Second, if the input data bit width is equal to the maximum bit width parallel computing n, and when the bit width of Vn of calculations, the input information code is not zero padding or cleared, as a direct pass-through, after shaping information code input data block is still d [nl: 0]; the coefficients according to the data bits when the bit width calculations Vn corresponding d_deX_Vn [nl: 0] from the selected data bits in the data block shaping.

[0082] 当然,若数据输入位宽为其他情况时,也可以通过其他方法将输入信息码整形为Kn-Vn) 'b0,d[Vn-l:0]}数据块,并根据最大计算位宽对应的数据位系数选择有效数据位。 [0082] Of course, if the input data bit width is the other case, the information code may be entered by other means of shaping Kn-Vn) 'b0, d [Vn-l: 0]} of data blocks, and calculates the maximum bit width corresponding to the selected coefficient data valid data bits. 若输入信息码进行透传方式的整形处理,则根据当次计算位宽Vn对应的数据位系数选择有效数据位。 If the input code information shaping transparent transmission of valid data bit is selected according to the data when the coefficient bit width Vn corresponding calculations.

[0083] 由于计算位宽为η时参与异或运算的有效数据比特包含了计算位宽为(1〜η-1) 时的所有有效数据比特。 [0083] Since the bit width is calculated η participating valid data bit exclusive-OR operation contains all valid data bits when the bit width is calculated (1~η-1). 计算位宽为Vn(VnSn)时的数据位系数为计算位宽为η时的数据位系数的低Vn 比特。 Calculated coefficient bit width of the data bits Vn (VnSn) is calculated as Vn-bit data bit width is low when the coefficient η. 即d_dex_n[nl:0] = {(n_Vn),b0,d_dex_Vn [Vn_l : 0]}。 I.e. d_dex_n [nl: 0] = {(n_Vn), b0, d_dex_Vn [Vn_l: 0]}. 因此,d_ deX_Vn的不同值可由最大计算位宽对应的数据位系数d_deX_n根据Vn获得,则数据位预处理模块10在数据处理过程中,只需保存d_deX_n值,而不用保存所有η个不同数据位系数d_dex_Vn,从而节省了存储空间。 Thus, different maximum values ​​may be calculated d_ deX_Vn bit width of data bits corresponding to coefficients obtained according Vn of d_deX_n, the preprocessing module 10 data bits in the data processing, simply save d_deX_n value, instead of saving all different data bits η coefficient d_dex_Vn, thus saving storage space.

[0084] CRC寄存器反馈选择模块11可以通过选择器直接选出其当前有效CRC寄存器位, 也可通过将c_dex_Vn[rl:0]作为滤波器系数,与crc[rl:0]进行点乘运算,或者其它方式最终选出当前有效CRC寄存器位。 [0084] Feedback CRC register selection module 11 may select a current valid CRC register bit which directly through the selector may by c_dex_Vn [rl: 0] as a filter coefficient, and crc [rl: 0] in point multiplication, or otherwise select the currently active final CRC register bit. 另外,由于计算位宽η大于等于CRC寄存器位宽r 时,CRC寄存器位系数c_dex[rl:0]等于数据位系数d_deX[nl:0]的最高r比特,即c_ dex [r-1 : 0] = d_dex [η-1:nr]。 Further, since the CRC register bit width equal to the bit width η r is greater than calculated, the CRC register coefficient c_dex [rl: 0] equal to the coefficient data d_deX [nl: 0] bits of the highest r, i.e. c_ dex [r-1: 0 ] = d_dex [η-1: nr]. 计算位宽η小于CRC寄存器位宽r时,CRC寄存器位系数c_ dex[rl:0]等于η 比特数据位系数补上(r-η)比特0,即c_dex [r_l : 0] = {d_dex [n_l : 0], (rn),b0}。 When calculating the CRC register bit width is smaller than [eta] R & lt bits wide, CRC register bit coefficients c_ dex [rl: 0] [eta] is equal to the bit fill coefficient (r-η) of bits 0, i.e. c_dex [r_l: 0] = {d_dex [ n_l: 0], (rn), b0}. 因此,c_dex_Vn的不同值可由最大计算位宽对应的数据位系数d_dex_n根据Vn值得到,则CRC寄存器反馈选择模块11在处理过程中只需保存d_deX_n值,无需保存所有η个不同寄存器位系数c_dex_Vn,进一步节省了存储空间。 Thus, different maximum values ​​may be calculated c_dex_Vn bit width corresponding to the coefficient data worth d_dex_n according to Vn, the CRC register selection module 11 only feedback values ​​stored d_deX_n process, without having to save all registers different coefficient η c_dex_Vn, further savings in storage space.

[0085] 异或运算模块12可以通过直接异或或者其他异或逻辑方法实现,将上述有效数据位与上述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码,并且将该新的CRC码更新至CRC寄存器。 [0085] The module 12 may be an exclusive OR operation XOR, or other method or implemented, the effective data bit with the above-described current valid CRC register bit exclusive-OR operation at least once, a new CRC code is obtained by direct isobutyl, and the new the updated CRC code to the CRC register. 本实施例中,可以将有效数据位和当前有效CRC寄存器位一起进行至少一次异或运算,获得新的CRC码;或者也可以先将有效数据位进行至少一次异或运算,获得有效数据位异或结果,再将该有效数据位异或结果与当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 In this embodiment, bits may be valid data and the currently active with at least one CRC register bit exclusive-OR operation to obtain the new CRC code; or may be at least one exclusive OR operation first valid data bit, valid data bits iso or the result, then the valid data bits with the currently active XOR result and CRC register bit exclusive-oR operation at least once, to obtain the new CRC code. 异或运算的次数可以根据具体情况而决定,在此就不做限定。 The number of exclusive-OR operation may be determined depending on the circumstances, this is not defined to do.

[0086] 本实施例循环冗余校验CRC码的实现装置,通过数据位预处理模块10和CRC寄存器位反馈选择模块11的处理,达到了可进行任意位宽信息码的并行CRC处理的效果,从而解决了现有技术串行电路每个时钟周期只能计算一位信息码,而并行电路计算位宽固定、 逻辑大、控制复杂的问题。 [0086] Effects of the present embodiment of apparatus for implementing a cyclic redundancy check CRC code embodiment, the preprocessing module 10 through the data bits and CRC register bit 11 in a feedback process selection module, to the parallel processing can be arbitrarily CRC code of the bit width information , thereby solving the prior art circuit of each serial clock cycle only one information code is calculated, and the parallel circuit calculates a fixed bit width, large logic, complex control problem. 而且,本发明还能够提高CRC生成、校验系统的运算性能,在满足高速CRC数据处理需求下,大大节省了逻辑资源,降低了实现成本,提高了灵活性、兼容性。 Further, the present invention also can improve operational performance of CRC generation, verification system, to meet the demand for high-speed data processing CRC, the logic resources saving, reduces the implementation costs, increase flexibility, compatibility.

[0087] 图8是本发明循环冗余校验CRC码的实现装置另一实施例的结构示意图。 [0087] FIG. 8 is a block diagram of another embodiment of apparatus for implementing the present invention, cyclic redundancy check CRC code.

[0088] 在上述实施例的基础上,本实施例循环冗余校验CRC码的实现装置,还包括: [0088] Based on the above embodiment, the apparatus of the present embodiment to achieve a cyclic redundancy check CRC code embodiment, further comprising:

[0089] 循环模块13,用于判断所述并行输入的信息码是否为最后一次数据输入,是则将所述新的CRC码记为最终的CRC码;否则通过数据位预处理模块10执行对并行输入的信息码进行预处理,并获得其有效数据位的步骤。 [0089] The circulation module 13, configured to determine whether or not the information code is inputted in parallel to the data input last time is then the new CRC code is referred to as the final CRC code; otherwise performing pre-processing module 10 via the data bits information code input in parallel preprocessing steps and obtaining valid data bits. [0090] 当循环模块13判断上述并行输入的信息码不是最后一次数据输入时,再通过上述数据位预处理模块10,循环进行CRC并行计算,直到当数据输入结束后,再将获得的CRC 码记为最终的CRC码。 [0090] When recycling module 13 determines the above information code input parallel data entry is not the last time, then a CRC calculated by the above parallel data bits preprocessing module 10, a loop until when the end of the data input, then the CRC code is obtained recorded as final CRC code.

[0091] 以上所述仅为本发明的优选实施例,并非因此限制其专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。 [0091] The above are only preferred embodiments of the present invention, not intended to limit the scope of their patent, any use of the specification and drawings of the present invention taken equivalent structures or equivalent process, directly or indirectly, to other related BACKGROUND shall also fall within the scope of protection of the present invention.

Claims (10)

1. 一种循环冗余校验CRC码的实现方法,其特征在于,包括以下步骤: 对并行输入的信息码进行预处理,并获得其有效数据位;从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位; 将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC 码。 A method to realize a cyclical redundancy check CRC code, characterized by comprising the steps of: parallel input information code preprocessing, and obtain the data bits; from the parallel CRC calculation to obtain a CRC code select the currently active CRC register bit; the data bits of the current and valid CRC register bit exclusive-oR operation at least once, to obtain the new CRC code.
2.根据权利要求1所述的方法,其特征在于,所述对并行输入的信息码进行预处理,并获得其有效数据位的步骤具体包括:根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,将并行输入的信息码进行整形处理,获得数据块;根据CRC并行计算电路最大并行计算位宽或者本次并行计算位宽对应的CRC并行计算逻辑关系式,从所述数据块中选出有效数据位。 Step 2. The method according to claim 1, wherein said pretreated information code input in parallel, and obtain the valid data bits comprises: parallel computing the CRC circuit according to the maximum bit width parallel computation and present bit width parallel computations, parallel information code inputted shaping process to obtain a data block; parallel CRC calculation logic in parallel relationship calculating circuit according to the maximum bit width parallel computing or calculating this parallel CRC corresponding to the bit width, the data from the block selected data bits.
3.根据权利要求2所述的方法,其特征在于,所述整形处理包括:根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,对并行输入信息码高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn),b0, d[Vn-l : 0]}数据块,其中η为最大并行计算位宽,Vn为本次并行计算位宽;尤其当并行输入信息码位宽等于最大并行计算位宽η时,整形处理也可以直接对并行输入信息码进行透传,则整形后的数据块仍为输入的信息码。 3. The method according to claim 2, wherein said shaping comprises: CRC parallel computing the maximum bit width parallel computing circuit and computing the current bit width parallel, the parallel input information symbols high zero padding or clear zero operation, shaping the parallel input of information code bits η {(n-Vn), b0, d [Vn-l: 0]} of data blocks, where η is the maximum bit width parallel computing, Vn oriented parallel computations bit width; especially when the parallel input information code bit width equal to the maximum information code bit width parallel computing [eta], may directly shaping the parallel input information symbols transmitted transparently, the data block is still shaping input.
4.根据权利要求1所述的方法,其特征在于,所述从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位的步骤具体为:根据本次并行计算位宽所对应的寄存器位系数,从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位。 4. The method according to claim 1, wherein the parallel computing a CRC from the CRC code obtained in the CRC register bit selects the currently active step specifically includes: according to the bit width of parallel computations corresponding register coefficient, calculated from the time obtained by parallel CRC code CRC and CRC register bit selects the currently active.
5.根据权利要求1至4中任一项所述的方法,其特征在于,所述将有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码的步骤之后还包括:判断所述并行输入的信息码是否为最后一次数据输入,是则将所述新的CRC码记为最终的CRC码;否则返回执行对并行输入的信息码进行预处理,并获得其有效数据位的步骤。 A method according to any one of claim 4 to claim, wherein said effective bit data of the current and valid CRC register bit exclusive-OR operation at least once, to obtain the new CRC code after step further comprising: determining the code input parallel information whether the last data entry, a new CRC code is then referred to as the final CRC code; otherwise, execution code information input in parallel preprocessing and obtain the the step of valid data bits.
6. 一种循环冗余校验CRC码的实现装置,其特征在于,包括:数据位预处理模块,用于对并行输入的信息码进行预处理,并获得其有效数据位; CRC寄存器反馈选择模块,用于从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位;异或运算模块,用于将所述有效数据位及所述当前有效CRC寄存器位进行至少一次异或运算,获得新的CRC码。 6. An apparatus for implementing a cyclic redundancy check CRC code, characterized by comprising: a data preprocessing module bits, for input in parallel preprocessing information code, and obtain the data bits; CRC register selection feedback means for calculating from the time obtained by parallel CRC code CRC CRC register bit selects the currently active; XOR operation means for said data bits of the current and valid CRC register bit exclusive-oR operation at least once, get a new CRC code.
7.根据权利要求6所述的装置,其特征在于,所述数据位预处理模块具体包括: 整形单元,用于根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,将并行输入的信息码进行整形处理,获得数据块;选择单元,用于根据CRC并行计算电路最大并行计算位宽或者本次并行计算位宽对应的CRC并行计算逻辑关系式,从所述数据块中选出有效数据位。 7. The device according to claim 6, wherein said data bit pre-processing module comprises: a shaping unit, for computing the maximum parallelism CRC bit width parallel computing circuit and the current calculated according to bits of parallel, parallel information code inputted shaping process to obtain a data block; selecting means for parallel CRC computation logic relationship parallel computing circuit according to the maximum bit width parallel computing or calculating this parallel CRC corresponding to the bit width, the data block selected from a valid data bit.
8.根据权利要求7所述的装置,其特征在于,所述整形单元进行整形处理具体为: 根据CRC并行计算电路最大并行计算位宽和本次并行计算位宽,对并行输入信息码高位进行补零或清零操作,将并行输入的信息码整形为η比特的{(n-Vn),b0, d[Vn-l : 0]}数据块,其中η为最大并行计算位宽,Vn为本次并行计算位宽;尤其当并行输入信息码位宽等于电路最大并行计算位宽时,整形处理也可以直接对并行输入信息码进行透传,则整形后的数据块仍为输入的信息码。 The maximum bit width parallel CRC calculation circuit and this parallel bits of parallel computing, calculated on the parallel input information for the upper code: 8. Specifically shaping apparatus according to claim 7, wherein said shaping unit zero padding or cleared, shaping the parallel input information code bits for η {(n-Vn), b0, d [Vn-l: 0]} of data blocks, where η is the maximum bit width parallel computing, Vn is the parallel computing bits wide; particularly when the bit width of the parallel input information symbols is equal to the maximum bit width parallel computing, shaping may be directly parallel input information symbols transmitted transparently, the data block is still shaping information input code .
9.根据权利要求6所述的装置,其特征在于,所述CRC寄存器反馈选择模块具体用于: 根据本次需要计算位宽所对应的寄存器位系数,从上一次CRC并行计算获得的CRC码中选择当前有效CRC寄存器位。 9. The apparatus according to claim 6, characterized in that, the CRC register selection module is used for feedback: The need to calculate the coefficient register corresponding to the bit width, the parallel CRC calculated from the time obtained according to the CRC select the currently active CRC register bit.
10.根据权利要求6至9中任一项所述的装置,其特征在于,还包括:循环模块,用于判断所述并行输入的信息码是否为最后一次数据输入,是则将所述新的CRC码记为最终的CRC码;否则返回执行对并行输入的信息码进行预处理,并获得其有效数据位的步骤。 10. The apparatus of one of claims 6-9 in any of the preceding claims, characterized in that, further comprising: circulating means for determining whether or not the information code is inputted in parallel to the data input last time is then the new otherwise performing step information codes input in parallel preprocessing and obtain the valid data bits; referred to as the final CRC code CRC code.
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