CN102130744B - Method and device for computing Cyclic Redundancy Check (CRC) code - Google Patents
Method and device for computing Cyclic Redundancy Check (CRC) code Download PDFInfo
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Abstract
The invention relates to a method and device for computing a Cyclic Redundancy Check (CRC) code. The method comprises the following steps of: computing the cyclic redundancy value of an entire beat datum through a first-stage stream or a multi-stage stream; computing the cyclic redundancy value of a last beat datum in a distributed computing mode of the multi-stage stream; and obtaining the cyclic redundancy value of a data frame according to the cyclic redundancy value of the entire beat datum and the cyclic redundancy value of the last beat datum. By adopting the method and device provided by the invention, the CRC value of a high-frequency data frame can be computed even though the CRC value of the data frame is computed under the condition of large data bit width, and the frequency bottleneck of the computation of the CRC value in high-speed Ethernet application is broken through. A small quantity of resources are occupied, and the method and the device can be popularized to data of any bit width.
Description
Technical field
The present invention relates to communication technical field, specifically the method and apparatus of calculating cyclic redundancy (Cyclic Redundancy Check, CRC) check code.
Background technology
Inner in data communication system, because Frame is comparatively large, is often divided into and claps parallel transmission more.Except last is clapped, other beats all transmit maximum data width.Last valid data width clapped changes between 1 byte to maximum byte.If Frame only has a beat, be equal to last bat of many beat of data.Because last data length clapped of Frame is not fixed, make in the process of calculated data frame CRC code, last CRC clapped of Frame calculates exists multiple possibility, and the calculating of CRC check code often becomes the frequency bottleneck in Fast Ethernet circuit design.As shown in Figure 1, maximum data width is M byte in the transmission of Frame, and last claps valid data width is N byte.Meanwhile, in data communication system, the transfer of data of Frame is often transmitted together along with other data frame information.
The algorithm of conventional crc value has serial method and parallel method two kinds.Serial approach each clock cycle can only process 1 Bit data, cannot meet big data quantity, the calculation requirement of high-frequency circuit.
The CRC algorithm that usual employing walks abreast is to improve the speed of the calculating of crc value check code.The derivation of the algorithm of major part Parallel CRC value check code is from serial encoding circuitry, release the matrix operation relation of encoder preceding state and next state, the matrix operation relation of N number of state and zero state can be obtained by recursion, realize this matrix by XOR gate, the crc value of N bit data can be calculated a clock cycle.
If the width of data is very wide, even if adopt parallel algorithm, chip or FPGA (Field-Programmable Gate Array, field programmable gate array) also cannot meet the requirements of frequency.Now can adopt the CRC algorithm of pipeline system: establish r=32, namely will calculate CRC32; If m=64, it is the data width of each parallel computation; If C is the input of previous stage CRC32; If { A, B} are the data wanting now parallel computation, and the bit wide of A, B is all 64.64 CRC32 parallel computation circuit can be adopted, calculate A, the value of the CRC32 of B; Adopt 32 CRC32 parallel computation circuit, calculate the value of the CRC32 of C; Acquired results XOR can be obtained { the value of the CRC32 of A, B, C}.
The CRC of last beat of data of Frame calculates: under Fast Ethernet 100Gbps applied environment, data width often will adopt wider 256bit, 512bit or 1024bit just can reach the rate request of data processing.Now calculated data frame crc value, because data bit width is comparatively large, also often will adopt pipelining algorithm just can reach frequency requirement even if the CRC of whole beat of data calculates; It is crucial that last of Frame is clapped, and the bit wide of valid data from 1byte to maximum bit wide, may have multiple situation, Frame last clap CRC and calculate needs and to use up a lot of resource, and be difficult to reach frequency requirement.
Consider that calculative data frame data width is 256bit, then the CRC for last beat of data calculates, and treatable situation can reach 32 kinds.Consider that the CRC of this last beat of data calculates to complete within a clock cycle, in prior art, need to realize 32 CRC computing modules, consume more resource, and due to the load of input signal comparatively large, which cannot reach higher frequency.
A crc value process difficult problem for larger data width and last beat of data, makes CRC computing module calculate the frequency bottleneck often become in Fast Ethernet circuit design.
Summary of the invention
Main purpose of the present invention is to provide a kind of method and apparatus of calculating cyclic redundancy check code, can obtain the calculating of higher operating frequency data frame, take resource less, and can be generalized to the data of any bit wide.
The technical solution adopted for the present invention to solve the technical problems is:
A method for calculating cyclic redundancy check code, it comprises:
By the cyclic redundancy value of one-level flowing water or the whole beat of data of multistage pipeline computing;
The cyclic redundancy value of last beat of data is calculated by the distribution account form of multistage flowing water;
The cyclic redundancy value of described Frame is obtained according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data.
Preferably, after the described cyclic redundancy value by whole beat of data described in one-level flowing water or multistage pipeline computing, comprise further: the cyclic redundancy value of preserving described whole beat of data.
Preferably, the described distribution account form by multistage flowing water calculates the cyclic redundancy value of last beat of data, specifically comprises:
Every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if the effective width of input data is less than the width that will calculate, then by described data penetration transmission to next stage flowing water.
Preferably, in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
The present invention also provides a kind of device of calculating cyclic redundancy check code, comprising:
Whole beat of data computing unit, for the cyclic redundancy value by one-level flowing water or the whole beat of data of multistage pipeline computing;
Last beat of data computing unit, for calculating the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
Cyclic redundancy computing unit, for obtaining the cyclic redundancy value of described Frame according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data.
Preferably, described whole beat of data computing unit, also for preserving the cyclic redundancy value of described whole beat of data.
Preferably, last beat of data computing unit described, also in computational process, every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if input data effective width be less than the width that will calculate, then by described data penetration transmission to next stage flowing water.
Preferably, last beat of data computing unit described or whole beat of data computing unit, also in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
Implement technical scheme of the present invention, there is following beneficial effect: even if the crc value of method and apparatus provided by the invention calculated data frame when data bit width is larger, also can realize the calculating of the crc value of the Frame of upper frequency, breach the frequency bottleneck that in Fast Ethernet application, crc value calculates.Take resource less, and can be generalized to the data of any bit wide.
Accompanying drawing explanation
The method flow diagram that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is the flow chart of the step S110 of the step S110 employing one-level flowing water of Fig. 1;
The implementation structure figure of first order flowing water when Fig. 3 is the step S110 employing one-level flowing water of Fig. 1;
The implementation structure figure of second level flowing water when Fig. 4 is the step S110 employing one-level flowing water of Fig. 1;
Fig. 5 is the flow chart of the step S110 of Fig. 1 step S110 when adopting multistage flowing water;
Fig. 6 is the flow chart of the step S110 of Fig. 1 step S120 when adopting multistage flowing water
Fig. 7 is the implementation structure figure of the step S110 of Fig. 1 first order flowing water when adopting multistage flowing water
Fig. 8 is the implementation structure figure of the step S110 of Fig. 1 second level flowing water when adopting multistage flowing water;
The structural representation of the device that Fig. 9 provides for the embodiment of the present invention.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The embodiment of the present invention provides a kind of method of calculating cyclic redundancy check code, and as shown in Figure 1, the method comprising the steps of:
S110, cyclic redundancy (CRC) value by whole beat of data described in one-level flowing water or multistage pipeline computing;
In this step S110, if meet frequency requirement, the crc value of the whole beat of data of one-level pipeline computing can be adopted; If frequency does not meet the demands, also can adopt multistage pipelining algorithm, what divides calculate the crc value of whole beat of data.The implementation of whole beat of data is flexible, can select according to device performance.In addition, in other examples, further, if adopt multistage flowing water computational process, then the progression of described flowing water is determined according to the width of input data.If adopt multistage pipelining algorithm, the crc value of point whole beat of data of what pipeline computing, then last beat of data is in this step S110, and last beat of data also having part is calculated.The width that this step S110 exports the data in step S110 to also will reduce, and can reduce the progression of flowing water in step S120 like this.In the case, the afterbody flowing water of this step S110 not only needs to preserve and calculates the crc value of whole beat of data, when also needing an in the end beat of data arrival, last beat of data is participated in this step 110 calculate together with the crc value of the data calculated and the crc value of whole beat of data before, calculate new crc value, and export in step S120 together with the data that last bat does not calculate.
In other examples, further, this step S110 also comprises: the cyclic redundancy value of preserving described whole beat of data.For this step, need to retain the crc value that upper claps whole beat of data, for calculating the crc value made new advances together with the whole beat of data of current input.Until last beat of data of Frame arrives, crc value before and last beat of data are all sent in step S120.If last beat of data of Frame is whole beat of data, then just can complete the calculating of the crc value of whole Frame in step S110, the flowing water at different levels of step S120 directly export the crc value of input.
S120, calculated the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
In every grade of flowing water (except afterbody) of step S120, the width of input data can be expressed as (2
n-8) bit, only gets 2 of an input data high position
n-1the crc value of bit data and input calculates the crc value made new advances, (2 of input data low level
n-1-8) bit data and new crc value export next stage flowing water to; If the valid data width of input data is less than 2
n-1, then flowing water at the corresponding levels does not calculate, (2 of an input data high position
n-1-8) crc value of bit data and input directly exports next stage flowing water to.
In the step s 120, input data are often through one-level flowing water, and data bit width will reduce.Data input to afterbody and only have 1byte data bit width, if these 1byte data are invalid, then the crc value of input directly exports by afterbody, obtains the crc value of Frame; If these 1byte data are effective, then calculate the crc value of Frame together with the crc value of input.
S130, obtain the cyclic redundancy value of described Frame according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data.Every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if the effective width of input data is less than the width that will calculate, then by described data penetration transmission to next stage flowing water, until calculate the cyclic redundancy value of this last beat of data.
The crc value of the method that above-described embodiment provides calculated data frame when data bit width is larger, can realize the calculating of the crc value of higher frequency data frame, breaches the frequency bottleneck that in Fast Ethernet application, crc value calculates.Take resource less, and can be generalized to the data of any bit wide.
The embodiment of the embody rule of said method is provided below:
As shown in Figure 2, step S110 adopts one-level pipeline computing to go out the crc value of whole beat of data, then the crc value counting circuit of Frame realizes as shown in Figure 2, comprises first order stream treatment (input 256bit data), second level stream treatment (input 248bit data and crc value), third level stream treatment (input 120bit data and crc value), fourth stage stream treatment (input 56bit data and crc value), level V stream treatment (input 24bit data and crc value), the 6th grade of stream treatment (input 8bit data and crc value).In Fig. 2, first empty frame table shows the step S120 that above-described embodiment provides, the whole beat of data of calculated data frame; Second empty frame table shows the step S130 that above-described embodiment provides, last beat of data of calculated data frame.
The implementation procedure of the first order stream treatment 256bit of step S110 as shown in Figure 3.In Fig. 3, ena represents that data frame data is effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is input or the output of module; Crc_pre represents the crc value that some beat of data that Frame has participated in CRC calculating calculate, when crc_init represents that Frame first count data start to calculate crc value, the initial value of input CRC counting circuit, crc256 concurrent operation circuit 301 represents: 256 CRC concurrent operation circuit.For the first count data of Frame, initial value 32 ' hffff_ffff is got in the calculating of crc value; For other whole bats of Frame, then get the crc value crc_pre that a bat calculates; For last bat of Frame, if valid data width is 256bit, then get final product the calculating of paired data frame crc value at this part crc256 concurrent operation circuit 301 and register 303; If last claps valid data width be less than 256bit, then directly export last beat of data and the crc value crc_pre that obtains before this to next stage flowing water (selector 304), therefore step S110 exports the bit wide of data to step S120, is 248bit.If Frame claps (namely sopin and eopin occurs at same period) for single, and valid data width is less than 256bit, then the crc value (CRC_OUT) that flowing water at the corresponding levels exports is 32 ' hffff_ffff.
In Fig. 4, ena represents that data frame data is effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is input or the output of module; CRC_IN represents that the crc value that upper level pipeline computing goes out, CRC_OUT represent that the crc value that pipeline computing at the corresponding levels goes out exports next stage to, and crc128 concurrent operation circuit 401 represents 128 CRC concurrent operation circuit.In the step s 120, the implementation procedure of second level flowing water " process 128bit " as shown in Figure 4.If the significance bit of input data is wider than equal 128bit, the high 128bit data then inputting data participate in crc value to crc128 concurrent operation circuit 401 and calculate, and the low 120bit of input data is exported to next stage flowing water (selector 402) with the crc value calculated; Otherwise the input high 120bit of data and the crc value of input are directly exported to next stage flowing water (selector 403).In step S120 in Fig. 2, the realization of every grade of flowing water is all consistent with the implementation of Fig. 4, and the width namely inputting data is (2
n-8) bit, if the effective width of input data is greater than 2
n-1, then high-order 2
n-1bit data participates in CRC computing, (2 of the crc value calculated and low level
n-1-8) bit data exports; If the effective width of input data is less than 2
n-1, then the crc value of input and the height (2 inputting data
n-1-8) bit data directly exports.
If the crc value that step S110 adopts multistage pipeline mode to realize the whole beat of data of Frame calculates, then the implementation procedure of step S110 as shown in Figure 5, now last bat has partial data and has just calculated crc value in step S110, so the implementation procedure of step S120 as shown in Figure 6.
In Fig. 5, the realization of the first order flowing water of step S120 as shown in Figure 7.In Fig. 7, ena represents that data frame data is effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is input or the output of module; Crc128 concurrent operation circuit 701 represents 128 CRC parallel computation circuit.First order flowing water (selector 703) only calculates the crc value of in input data high 128.If the valid data width of input data is less than 128bit, then high 128 of input data directly export by selector 703, and the crc value simultaneously exported is 0.Last beat of data is through this grade of flowing water, if the valid data width of input data is greater than 128bit, then the data of high 128bit also can by calculating crc value.
In Fig. 5, the second level flowing water of step S110 will complete the calculating of the crc value of whole beat of data, and its implementation as shown in Figure 8.In Fig. 8, ena represents that data frame data is effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is input or the output of module; CRC_IN represents the crc value that upper level pipeline computing goes out, CRC_OUT represents that the crc value that pipeline computing at the corresponding levels goes out exports next stage to, crc128 concurrent operation circuit 801 represents 128 CRC parallel computation circuit, and crc256 concurrent operation circuit 805 represents 256 CRC parallel computation circuit; Crc_pre represents the crc value that some beat of data that Frame has participated in CRC calculating calculate, crc_data represents the crc value that 128 input data and CRC_IN are calculated by crc128 parallel computation circuit (that is: computing circuit 803), crc_pre128 represents that the crc value that crc_pre calculates through crc128 concurrent operation circuit 801, crc_pre256 represent the crc value that crc_pre calculates through crc256 concurrent operation circuit 805.From pipelining algorithm, for the first count data (tentation data frame is made up of many beat of data) of Frame, the data inputted with higher level's flowing water and CRC_IN (input value of CRC) calculate the crc value of this beat of data, first the value of crc_pre is selected to be 32 ' hffff_ffff by selector 808, then crc_pre is used, CRC_IN and input data calculate the CRC_OUT (" other situations " corresponding in selector 806) of first count data, and are stored in register 807; For each whole beat of data afterwards, crc_pre is the CRC_OUT (being selected by selector 808) that a beat of data calculates, first calculate the crc value crc_data (computing circuit 803) of data, calculate the result of calculation crc_pre256 (by computing circuit 805 computing) of crc_pre simultaneously, then both XORs (by computing circuit 804 XOR), new CRC_OUT (being obtained by " other situations " corresponding in selector 806) can be obtained, be stored in register 807.When last beat of data arrives flowing water at the corresponding levels, if last beat of data is also whole beat of data, then processing mode is identical with other whole beat of data; If last beat of data effective width is less than 128bit, then last beat of data does not process in first order flowing water, directly exports crc_pre to register 807 (" 3 ' b110 " situation in corresponding selection device 806); If the effective width of last beat of data is more than or equal to 128bit and is less than 256bit, then last beat of data has 128bit in first order flowing water by calculated crc value, now want first crc_pre to be obtained crc_pre128 by crc128 concurrent operation circuit 801, then crc_pre128 and CRC_IN XOR (carrying out XOR by computing circuit 802), just can obtain new crc value (" 3 ' b101 " situation in corresponding selection device 806), be stored in register 807.
The implementation described in the implementation of flowing water at different levels and Fig. 4 in Fig. 6 is similar.
The embodiment of the present invention also provides a kind of device of calculating cyclic redundancy check code, and as shown in Figure 9, this device comprises:
Whole beat of data computing unit 210, for the cyclic redundancy value by whole beat of data described in one-level flowing water or multistage pipeline computing;
Last beat of data computing unit 220, for calculating the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
Cyclic redundancy computing unit 230, for obtaining the cyclic redundancy value of described Frame according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data.
In other examples, further, described whole beat of data computing unit 210, also for preserving the cyclic redundancy value of described whole beat of data.
In other examples, further, last beat of data computing unit 220 described, also in computational process, every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if input data effective width be less than the width that will calculate, then by described data penetration transmission to next stage flowing water.
In other examples, further, last beat of data computing unit 220 described or whole beat of data computing unit 210, also in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
The crc value of the device that above-described embodiment provides calculated data frame when data bit width is larger, can realize the calculating of the crc value of higher frequency data frame, breaches the frequency bottleneck that in Fast Ethernet application, crc value calculates.Take resource less, and can be generalized to the data of any bit wide.
These are only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a method for calculating cyclic redundancy check code, is characterized in that, comprising:
By the cyclic redundancy value of one-level flowing water or the whole beat of data of multistage pipeline computing; Preserve the cyclic redundancy value of described whole beat of data and clap the cyclic redundancy value of whole beat of data as upper one; The cyclic redundancy value made new advances is calculated together with the whole beat of data of current input according to the cyclic redundancy value that upper claps whole beat of data, and the cyclic redundancy value of whole beat of data is clapped as new upper one, cycle calculations draws the cyclic redundancy value of the whole beat of data of the last bat of last beat of data successively;
According to cyclic redundancy value and last beat of data of the whole beat of data of the last bat of last beat of data, calculated the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
The cyclic redundancy value of described Frame is obtained according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data; If last beat of data of Frame is whole beat of data, then completed the calculating of the cyclic redundancy value of whole Frame by one-level flowing water or multistage flowing water, by the distribution account form of multistage flowing water, the cyclic redundancy value of input is directly exported.
2. method as claimed in claim 1, it is characterized in that, the described distribution account form by multistage flowing water calculates the cyclic redundancy value of last beat of data, specifically comprises:
Every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if the effective width of input data is less than the width that will calculate, then by described data penetration transmission to next stage flowing water.
3. method as claimed in claim 1, is characterized in that, in multistage flowing water computational process, determines the progression of described flowing water according to the width of input data.
4. a device for calculating cyclic redundancy check code, is characterized in that, comprising:
Whole beat of data computing unit, for the cyclic redundancy value by whole beat of data described in one-level flowing water or multistage pipeline computing; Also for preserving the cyclic redundancy value of described whole beat of data and clapping the cyclic redundancy value of whole beat of data as upper one; The cyclic redundancy value made new advances is calculated together with the whole beat of data of current input according to the cyclic redundancy value that upper claps whole beat of data, and the cyclic redundancy value of whole beat of data is clapped as new upper one, cycle calculations draws the cyclic redundancy value of the whole beat of data of the last bat of last beat of data successively;
Last beat of data computing unit, for according to the cyclic redundancy value of the whole beat of data of the last bat of last beat of data and last beat of data, calculates the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
Cyclic redundancy computing unit, for obtaining the cyclic redundancy value of described Frame according to the cyclic redundancy value of described whole beat of data and the cyclic redundancy value of last beat of data, if last beat of data of Frame is whole beat of data, then completed the calculating of the cyclic redundancy value of whole Frame by one-level flowing water or multistage flowing water, by the distribution account form of multistage flowing water, the cyclic redundancy value of input is directly exported.
5. device as claimed in claim 4, it is characterized in that, last beat of data computing unit described, also in computational process, every one-level flowing water only calculates the cyclic redundancy value of input data fixed width, if input data effective width be less than the width that will calculate, then by described data penetration transmission to next stage flowing water.
6. device as claimed in claim 4, is characterized in that, last beat of data computing unit described or whole beat of data computing unit, also in multistage flowing water computational process, determines the progression of described flowing water according to the width of input data.
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| CN109462458B (en) * | 2019-01-11 | 2021-04-16 | 深圳市常茂信科技开发有限公司 | Method for realizing parallel CRC (cyclic redundancy check) by multistage pipeline circuit |
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| CN101803265A (en) * | 2007-09-18 | 2010-08-11 | 三星电子株式会社 | Methods and apparatus to generate multiple cyclic redundancy checks (crcs) |
| CN101847999A (en) * | 2010-05-28 | 2010-09-29 | 清华大学 | Method for performing parallel check by using cyclic redundancy check codes |
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| CN101803265A (en) * | 2007-09-18 | 2010-08-11 | 三星电子株式会社 | Methods and apparatus to generate multiple cyclic redundancy checks (crcs) |
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