CN102130744A - Method and device for computing Cyclic Redundancy Check (CRC) code - Google Patents
Method and device for computing Cyclic Redundancy Check (CRC) code Download PDFInfo
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Abstract
The invention relates to a method and device for computing a Cyclic Redundancy Check (CRC) code. The method comprises the following steps of: computing the cyclic redundancy value of an entire beat datum through a first-stage stream or a multi-stage stream; computing the cyclic redundancy value of a last beat datum in a distributed computing mode of the multi-stage stream; and obtaining the cyclic redundancy value of a data frame according to the cyclic redundancy value of the entire beat datum and the cyclic redundancy value of the last beat datum. By adopting the method and device provided by the invention, the CRC value of a high-frequency data frame can be computed even though the CRC value of the data frame is computed under the condition of large data bit width, and the frequency bottleneck of the computation of the CRC value in high-speed Ethernet application is broken through. A small quantity of resources are occupied, and the method and the device can be popularized to data of any bit width.
Description
Technical field
The present invention relates to communication technical field, specifically is calculating cyclic redundancy (Cyclic Redundancy Check, CRC) method and apparatus of check code.
Background technology
In data communication system inside,, often be divided into the parallel transmissions of clapping because Frame is bigger more.Except that last was clapped, other beats all transmitted the maximum data width.The valid data width of last bat changes between maximum byte in 1 byte.If Frame has only a beat, be equal to last bat of many beat of data.Because the data length of last bat of Frame is fixing, make in the process of calculated data frame CRC sign indicating number, the CRC of last bat of Frame calculate exist multiple may, the calculating of CRC check sign indicating number often becomes the frequency bottleneck in the Fast Ethernet circuit design.The transmission of Frame as shown in Figure 1, the maximum data width is the M byte, last claps valid data width is the N byte.Simultaneously, in data communication system, the transfer of data of Frame often is accompanied by other Frame information and transmits together.
The algorithm of crc value commonly used has two kinds of serial method and parallel methods.Each clock cycle of serial approach can only be handled 1 Bit data, can't satisfy big data quantity, the calculation requirement of high-frequency circuit.
Usually adopt parallel CRC algorithm to improve the speed of the calculating of crc value check code.The derivation of the algorithm of most of Parallel CRC value check code is from the serial code circuit, release the matrix operation relation of encoder preceding state and next state, can obtain the matrix operation relation of N state and zero state by recursion, realize this matrix with XOR gate, the crc value that can calculate the N bit data a clock cycle.
If the width of data is very wide, even adopt parallel algorithm, chip or FPGA (Field-Programmable Gate Array, field programmable gate array) also can't meet the requirements of frequency.Can adopt the CRC algorithm of pipeline system this moment: establish r=32, promptly will calculate CRC32; If m=64 is the data width of each parallel computation; If C is the input of previous stage CRC32; If { A, B} are the data of wanting parallel computation now, and the bit wide of A, B all is 64.Can adopt 64 CRC32 parallel computation circuit, calculate A, the value of the CRC32 of B; Adopt 32 CRC32 parallel computation circuit, calculate the value of the CRC32 of C; With gained as a result XOR can obtain { A, B, the value of the CRC32 of C}.
The CRC of last beat of data of Frame calculates: under Fast Ethernet 100Gbps applied environment, data width often will adopt the 256bit of broad, and 512bit or 1024bit just can reach the rate request of data processing.This moment, calculated data frame crc value because data bit width is bigger, also often will adopt pipelining algorithm just can reach frequency requirement even the CRC of whole beat of data calculates; Most critical be, last of Frame clapped, the bit wide of valid data may have multiple situation from 1byte to maximum bit wide, last claps Frame CRC and calculates a lot of resources of need using up, and is difficult to reach frequency requirement.
Consider that calculative Frame data width is 256bit, then the CRC for last beat of data calculates, and can treatable situation reach 32 kinds.The CRC that considers this last beat of data calculates and to finish in a clock cycle, in the prior art, needs to realize 32 CRC computing modules, consumes more resource, and owing to the load of input signal is bigger, this mode can't reach higher frequency.
The bigger data width and the crc value of last beat of data are handled a difficult problem, make the calculating of CRC computing module often become the frequency bottleneck in the Fast Ethernet circuit design.
Summary of the invention
Main purpose of the present invention provides a kind of method and apparatus of calculating cyclic redundancy check code, can obtain the calculating of higher operating frequency Frame, and it is less to take resource, and can be generalized to the data of any bit wide.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of method of calculating cyclic redundancy check code, it comprises:
Calculate the cyclic redundancy value of whole beat of data by one-level flowing water or multistage flowing water;
Calculate the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
Obtain the cyclic redundancy value of described Frame according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data.
Preferably, after the described cyclic redundancy value of calculating described whole beat of data by one-level flowing water or multistage flowing water, further comprise: the cyclic redundancy value of preserving described whole beat of data.
Preferably, described distribution account form by multistage flowing water calculates the cyclic redundancy value of last beat of data, specifically comprises:
Each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the effective width of input data less than the width that will calculate, then with described data penetration transmission to next stage flowing water.
Preferably, in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
The present invention also provides a kind of device of calculating cyclic redundancy check code, comprising:
Whole beat of data computing unit is used for calculating the cyclic redundancy value of putting in order beat of data by one-level flowing water or multistage flowing water;
Last beat of data computing unit is used for calculating by the distribution account form of multistage flowing water the cyclic redundancy value of last beat of data;
The cyclic redundancy computing unit is used for obtaining according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data the cyclic redundancy value of described Frame.
Preferably, described whole beat of data computing unit also is used to preserve the cyclic redundancy value of described whole beat of data.
Preferably, described last beat of data computing unit also is used in computational process, and each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the input data effective width less than the width that will calculate, then with described data penetration transmission to next stage flowing water.
Preferably, described last beat of data computing unit or whole beat of data computing unit also are used in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
Implement technical scheme of the present invention, has following beneficial effect: even the crc value of method and apparatus provided by the invention calculated data frame under the bigger situation of data bit width, also can realize the calculating of crc value of the Frame of upper frequency, break through the frequency bottleneck that crc value calculated during Fast Ethernet was used.It is less to take resource, and can be generalized to the data of any bit wide.
Description of drawings
The method flow diagram that Fig. 1 provides for the embodiment of the invention;
Fig. 2 is the flow chart that the step S110 of Fig. 1 adopts the step S110 of one-level flowing water;
Fig. 3 is the implementation structure figure of the first order flowing water of the step S110 of Fig. 1 when adopting one-level flowing water;
Fig. 4 is the implementation structure figure of the second level flowing water of the step S110 of Fig. 1 when adopting one-level flowing water;
The flow chart of Fig. 5 step S110 during multistage flowing water for the step S110 of Fig. 1 adopts;
The flow chart of Fig. 6 step S120 during multistage flowing water for the step S110 of Fig. 1 adopts
The implementation structure figure of Fig. 7 first order flowing water during multistage flowing water for the step S110 of Fig. 1 adopts
The implementation structure figure of Fig. 8 second level flowing water during multistage flowing water for the step S110 of Fig. 1 adopts;
The structural representation of the device that Fig. 9 provides for the embodiment of the invention.
The realization of the object of the invention, functional characteristics and advantage will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of method of calculating cyclic redundancy check code, and as shown in Figure 1, the method comprising the steps of:
S110, calculate cyclic redundancy (CRC) value of described whole beat of data by one-level flowing water or multistage flowing water;
Among this step S110,, can adopt one-level flowing water to calculate the crc value of whole beat of data if satisfy frequency requirement; If frequency does not meet the demands, also can adopt multistage flowing water algorithm, what divides calculate the crc value of whole beat of data.The implementation of whole beat of data is flexible, can select according to device performance.In addition, in other embodiment, further,, then determine the progression of described flowing water according to the width of input data if adopt multistage flowing water computational process.If adopt multistage flowing water algorithm, the crc value that divides what flowing water to calculate whole beat of data, then last beat of data is in this step S110, and last beat of data that also has part is calculated.The width that this step S110 exports the data among the step S110 to also will reduce, and can reduce the progression of flowing water among the step S120 like this.In the case, the afterbody flowing water of this step S110 not only needs to preserve and calculate the crc value of whole beat of data, when also needing beat of data arrival in the end, the crc value that last beat of data is participated in the data of calculating in this step 110 calculates with the crc value of putting in order beat of data before, calculate new crc value, and export among the step S120 together with last data of clapping not calculating.
In other embodiment, further, this step S110 also comprises: the cyclic redundancy value of preserving described whole beat of data.For this step, need to keep last one and clap the crc value of whole beat of data, be used for calculating the crc value that makes new advances with the whole beat of data of current input.Last beat of data until Frame arrives, and crc value and last beat of data before all sent among the step S120.If last beat of data of Frame then just can be finished the calculating of the crc value of whole Frame for whole beat of data at step S110, the flowing water at different levels of step S120 are directly exported the crc value of input and are got final product.
S120, calculate the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
At every grade of flowing water (except the afterbody) of step S120, the width of input data can be expressed as (2
n-8) bit only gets 2 of an input data high position
N-1The crc value of bit data and input calculates the crc value that makes new advances, (2 of input data low level
N-1-8) bit data and new crc value export next stage flowing water to; If the valid data width of input data is less than 2
N-1, flowing water then at the corresponding levels does not calculate, (2 of an input data high position
N-1-8) crc value of bit data and input directly exports next stage flowing water to.
In step S120, the input data are every through one-level flowing water, and data bit width will reduce.Data input to afterbody and have only the 1byte data bit width, and if these 1byte data are invalid, and then afterbody is directly exported the crc value of input, obtains the crc value of Frame; If these 1byte data then calculate the crc value of Frame effectively with the crc value of input.
S130, obtain the cyclic redundancy value of described Frame according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data.Each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the effective width of input data less than the width that will calculate, then with described data penetration transmission to next stage flowing water, until the cyclic redundancy value that calculates this last beat of data.
The crc value of the method that the foregoing description provides calculated data frame under the bigger situation of data bit width can be realized the calculating of the crc value of higher frequency data frame, has broken through the frequency bottleneck that crc value calculated during Fast Ethernet was used.It is less to take resource, and can be generalized to the data of any bit wide.
The embodiment of the concrete application of said method is provided below:
As shown in Figure 2, step S110 adopts one-level flowing water to calculate the crc value of whole beat of data, then the crc value counting circuit of Frame is realized as shown in Figure 2, comprises first order stream treatment (input 256bit data), second level stream treatment (input 248bit data and crc value), third level stream treatment (input 120bit data and crc value), fourth stage stream treatment (input 56bit data and crc value), level V stream treatment (input 24bit data and crc value), the 6th grade of stream treatment (input 8bit data and crc value).Among Fig. 2, first empty frame table shows the step S120 that the foregoing description provides, and the calculated data frame is put in order beat of data; Second empty frame table shows the step S130 that the foregoing description provides, last beat of data of calculated data frame.
The implementation procedure of the first order stream treatment 256bit of step S110 as shown in Figure 3.Among Fig. 3, ena represents that the Frame data are effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is the input or the output of module; Crc_pre represents that Frame has participated in the crc value that some beat of data that CRC calculates calculate, when crc_init represents that Frame first count data begin to calculate crc value, the initial value of input CRC counting circuit, crc256 concurrent operation circuit 301 expressions: 256 CRC concurrent operation circuit.For the first count data of Frame, initial value 32 ' hffff_ffff is got in the calculating of crc value; For other whole bats of Frame, then get one and clap the crc value crc_pre that calculates; For last bat of Frame,, then can finish calculating to the Frame crc value at this part crc256 concurrent operation circuit 301 and register 303 if the valid data width is 256bit; If last claps valid data width less than 256bit, then directly export last beat of data and the crc value crc_pre that obtains before this to next stage flowing water (selector 304), so step S110 is to the bit wide of step S120 dateout, for 248bit gets final product.If Frame is single the bat (being that sopin and eopin occurred with one-period), and the valid data width is less than 256bit, and the crc value (CRC_OUT) that flowing water then at the corresponding levels is exported is 32 ' hffff_ffff.
Among Fig. 4, ena represents that the Frame data are effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is the input or the output of module; CRC_IN represents the crc value that upper level flowing water calculates, and CRC_OUT represents that the crc value that flowing water at the corresponding levels calculates exports next stage to, 128 CRC concurrent operation circuit of crc128 concurrent operation circuit 401 expressions.In step S120, the implementation procedure that second level flowing water " is handled 128bit " as shown in Figure 4.If being wider than, the significance bit of input data equals 128bit, the high 128bit data of then importing data participate in crc value to crc128 concurrent operation circuit 401 and calculate, and the low 120bit of input data and the crc value of calculating are exported to next stage flowing water (selector 402); Otherwise the high 120bit of input data and the crc value of input are directly exported to next stage flowing water (selector 403).Among the step S120 among Fig. 2, the realization of the every grade of flowing water all implementation with Fig. 4 is consistent, and the width of promptly importing data is (2
n-8) bit is if the effective width of input data is greater than 2
N-1, then high-order 2
N-1Bit data participates in the CRC computing, (2 of crc value of calculating and low level
N-1-8) bit data output; If the effective width of input data is less than 2
N-1, then the height (2 of the crc value of input and input data
N-1-8) bit data is directly exported.
If step S110 adopts multistage pipeline mode to realize that the crc value of the whole beat of data of Frame calculates, then the implementation procedure of step S110 as shown in Figure 5, last bat this moment has partial data and has just calculated crc value at step S110, so the implementation procedure of step S120 as shown in Figure 6.
Among Fig. 5, the realization of the first order flowing water of step S120 as shown in Figure 7.Among Fig. 7, ena represents that the Frame data are effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is the input or the output of module; 128 CRC parallel computation circuit of crc128 concurrent operation circuit 701 expressions.First order flowing water (selector 703) only calculates high 128 crc value in the input data.If the valid data width of input data is less than 128bit, then selector 703 will be imported high 128 directly outputs of data, and Shu Chu crc value is 0 simultaneously.Last beat of data is through this grade flowing water, if the valid data width of input data greater than 128bit, then the data of high 128bit also can be calculated crc value.
Among Fig. 5, the second level flowing water of step S110 will be finished the calculating of the crc value of whole beat of data, and its implementation as shown in Figure 8.Among Fig. 8, ena represents that the Frame data are effective, and sop represents the beginning of Frame, and eop represents the end of Frame, and vldbyte represents the valid data number of last beat of data of Frame, and suffix in, out represent that corresponding signal is the input or the output of module; CRC_IN represents the crc value that upper level flowing water calculates, CRC_OUT represents that the crc value that flowing water at the corresponding levels calculates exports next stage to, 128 CRC parallel computation circuit of crc128 concurrent operation circuit 801 expressions, 256 CRC parallel computation circuit of crc256 concurrent operation circuit 805 expressions; Crc_pre represents that Frame has participated in the crc value that some beat of data that CRC calculates calculate, crc_data represents the crc value that 128 input data and CRC_IN calculate by crc128 parallel computation circuit (that is: computing circuit 803), crc_pre128 represents the crc value that crc_pre calculates through crc128 concurrent operation circuit 801, and crc_pre256 represents the crc value that crc_pre calculates through crc256 concurrent operation circuit 805.By pipelining algorithm as can be known, first count data (the tentation data frame is made up of many beat of data) for Frame, the crc value of calculating this beat of data with the data and the CRC_IN (input value of CRC) of higher level's flowing water input, selecting the value of crc_pre by selector 808 earlier is 32 ' hffff_ffff, use crc_pre then, CRC_IN and input data are calculated the CRC_OUT (in the selector 806 " other situations " of correspondence) of first count data, and are stored in register 807; For each whole beat of data afterwards, crc_pre is the CRC_OUT (selecting by selector 808) that a beat of data is calculated, calculate the crc value crc_data (computing circuit 803) of data earlier, calculate the result of calculation crc_pre256 (by computing circuit 805 computings) of crc_pre simultaneously, both XORs (by computing circuit 804 XORs) then, can obtain new CRC_OUT (obtaining), be stored in register 807 by " other situations " corresponding in the selector 806.When last beat of data arrived flowing water at the corresponding levels, if last beat of data also is whole beat of data, then processing mode was identical with other whole beat of data; If last beat of data effective width is less than 128bit, then last beat of data does not process in first order flowing water, directly exports crc_pre and gets final product to register 807 (" 3 ' b110 " situation in the corresponding selection device 806); If the effective width of last beat of data is more than or equal to 128bit and less than 256bit, then last beat of data has 128bit to be calculated crc value in first order flowing water, want this moment earlier crc_pre to be obtained crc_pre128 by crc128 concurrent operation circuit 801, then crc_pre128 and CRC_IN XOR (carrying out XOR) by computing circuit 802, just can obtain new crc value (" 3 ' b101 " situation in the corresponding selection device 806), be stored in register 807.
The implementation of describing among the implementation of flowing water at different levels and Fig. 4 among Fig. 6 is similar.
The embodiment of the invention also provides a kind of device of calculating cyclic redundancy check code, and as shown in Figure 9, this device comprises:
Put in order beat of data computing unit 210, be used for calculating the cyclic redundancy value of described whole beat of data by one-level flowing water or multistage flowing water;
Last beat of data computing unit 220 is used for calculating by the distribution account form of multistage flowing water the cyclic redundancy value of last beat of data;
Cyclic redundancy computing unit 230 is used for obtaining according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data the cyclic redundancy value of described Frame.
In other embodiment, further, described whole beat of data computing unit 210 also is used to preserve the cyclic redundancy value of described whole beat of data.
In other embodiment, further, described last beat of data computing unit 220, also be used in computational process, each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the input data effective width less than the width that will calculate, then with described data penetration transmission to next stage flowing water.
In other embodiment, further, described last beat of data computing unit 220 or whole beat of data computing unit 210 also are used in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
The crc value of the device that the foregoing description provides calculated data frame under the bigger situation of data bit width can be realized the calculating of the crc value of higher frequency data frame, has broken through the frequency bottleneck that crc value calculated during Fast Ethernet was used.It is less to take resource, and can be generalized to the data of any bit wide.
Below only be preferred embodiment of the present invention,, all any modifications of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention not in order to restriction the present invention.
Claims (8)
1. the method for a calculating cyclic redundancy check code is characterized in that, comprising:
Calculate the cyclic redundancy value of whole beat of data by one-level flowing water or multistage flowing water;
Calculate the cyclic redundancy value of last beat of data by the distribution account form of multistage flowing water;
Obtain the cyclic redundancy value of described Frame according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data.
2. method according to claim 1 is characterized in that, described calculate the cyclic redundancy value of whole beat of data by one-level flowing water or multistage flowing water after, further comprise: the cyclic redundancy value of preserving described whole beat of data.
3. method as claimed in claim 1 or 2 is characterized in that described distribution account form by multistage flowing water calculates the cyclic redundancy value of last beat of data, specifically comprises:
Each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the effective width of input data less than the width that will calculate, then with described data penetration transmission to next stage flowing water.
4. method according to claim 1 is characterized in that, in multistage flowing water computational process, determines the progression of described flowing water according to the width of input data.
5. the device of a calculating cyclic redundancy check code is characterized in that, comprising:
Put in order the beat of data computing unit, be used for calculating the cyclic redundancy value of described whole beat of data by one-level flowing water or multistage flowing water;
Last beat of data computing unit is used for calculating by the distribution account form of multistage flowing water the cyclic redundancy value of last beat of data;
The cyclic redundancy computing unit is used for obtaining according to the cyclic redundancy value of the cyclic redundancy value of described whole beat of data and last beat of data the cyclic redundancy value of described Frame.
6. as device as described in the claim 5, it is characterized in that described whole beat of data computing unit also is used to preserve the cyclic redundancy value of described whole beat of data.
7. as device as described in claim 5 or 6, it is characterized in that, described last beat of data computing unit, also be used in computational process, each grade flowing water only calculates the cyclic redundancy value of input data stationary width, if the input data effective width less than the width that will calculate, then with described data penetration transmission to next stage flowing water.
8. as device as described in the claim 5, it is characterized in that described last beat of data computing unit or whole beat of data computing unit also are used in multistage flowing water computational process, determine the progression of described flowing water according to the width of input data.
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| CN109462458A (en) * | 2019-01-11 | 2019-03-12 | 深圳市常茂信科技开发有限公司 | A kind of method that multilevel flow water circuit realizes Parallel CRC |
| CN109462458B (en) * | 2019-01-11 | 2021-04-16 | 深圳市常茂信科技开发有限公司 | Method for realizing parallel CRC (cyclic redundancy check) by multistage pipeline circuit |
| CN112306741A (en) * | 2020-11-19 | 2021-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | CRC (Cyclic redundancy check) method and related device |
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