CN201789500U - Train control transponder uplink signal simulating device - Google Patents
Train control transponder uplink signal simulating device Download PDFInfo
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- CN201789500U CN201789500U CN2010205274698U CN201020527469U CN201789500U CN 201789500 U CN201789500 U CN 201789500U CN 2010205274698 U CN2010205274698 U CN 2010205274698U CN 201020527469 U CN201020527469 U CN 201020527469U CN 201789500 U CN201789500 U CN 201789500U
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Abstract
The utility model discloses a train control transponder uplink signal simulating device, which soles the technical problem of testing receiving performance of a transponder transmission module in a high-speed application environment. The device consists of a coding and control unit, a digital signal synthesizing unit and a digital-analog signal conversion unit which are sequentially connected. Compared with the prior art, the simulating device generates simulation FSK modulating signals of digital signal synthesis to test the receiving performance of a BTM, various performance parameters of each simulation signals can be controlled and adjusted by the aid of program, the simulating device can meet various requirements of testing, is simple in circuit structure, low in cost and better in controllability, greatly reduces cost for testing the receiving performance of the BTM, improves testing efficiency, capability of being stored and replayed of digital signals, and guarantees consistency of testing results.
Description
Technical field
The utility model relates to a kind of testing equipment of transponder transport module of Chinese train control system, particularly a kind of signal imitation device of transponder transport module testing equipment.
Background technology
Transponder and transponder transport module are one of key equipments in the Chinese train control system CTCS system, and along with the fast development of domestic Line for Passenger Transportation in recent years, they will be used for domestic 160-350km/h rail track in a large number.Transponder is used for the information such as mobile unit wireless transmission locating information, line parameter circuit value and temporary speed limitation to train control system.The mobile unit of train control system receives these important informations by transponder transport module BTM.The receptivity of transponder transport module, particularly the receptivity when crossing point at a high speed will directly influence the speed of service of high ferro.Receptivity when how crossing point at a high speed by technological means checking BTM, testing its definite technical indicator has become this equipment and has further enlarged one of important difficult problem of using and must solving during production domesticization.Relative motion by 350km/h between the method simulation car-ground equipment that adopts matter emulation is one of method of checking high speed receptivity.But this method and technology difficulty is very big, and all very high to the demand of building place and fund input.And this method testing efficiency is low, can't satisfy the needs of BTM volume production test.
Summary of the invention
The purpose of this utility model provides a kind of row control transponder uplink signal analogue means, and the technical problem that solve is the receptivity of test transponder transport module under the high-speed applications environment.
The utility model is by the following technical solutions: a kind of row control transponder uplink signal analogue means, and described row control transponder uplink signal analogue means is connected and composed by the coding that is linked in sequence and control unit, digital signal synthesis unit and digital and analogue signals conversion unit; Described coding and control unit are used for the emulation transponder data information that the acceptance test system sends, and finish coding and generate message; Described digital signal synthesis unit is used to generate modulation rate reference signal and digital fsk signal; Described digital-to-analogue conversion unit is converted into analog electrical signal with the modulation rate reference signal, and after amplifying shaping, feed back to the digital signal synthesis unit as the modulation rate reference clock, the digital-to-analogue conversion unit is converted into analog electrical signal with digital fsk signal, exports to the canonical reference antenna.
Coding of the present utility model is connected test macro with control unit.
Digital-to-analogue conversion unit of the present utility model connects the canonical reference antenna.
Coding of the present utility model and control unit adopt digital signal processor TMS320C5509A.
Digital signal synthesis unit of the present utility model adopts field programmable gate array device EP3C40F484C8N.
Digital and analogue signals conversion unit of the present utility model adopts digital-to-analogue to transform chip AD9767.
The utility model compared with prior art, analogue means produces the synthetic emulation fsk modulated signal of digital signal, the receptivity of test b TM, and the various performance parameters of simulate signal can be adjustable by program controlled, can fully satisfy the various demands of test, circuit structure is simple, and is with low cost, has preferable controllability, reduce the cost of test b TM receptivity greatly, improve testing efficiency, digital signal can be stored playback, has guaranteed the consistency of test result.
Description of drawings
Fig. 1 is a circuit block diagram of the present utility model.
Fig. 2-the 1st, coding of the present utility model and control unit circuit schematic diagram.
Fig. 2-the 2nd, the usb circuit schematic diagram of coding of the present utility model and control unit circuit and test macro.
Fig. 2-the 3rd, coding of the present utility model and control unit external data bus circuit theory diagrams.
Fig. 2-the 4th, memory circuitry schematic diagram of the present utility model.
Fig. 3-the 1st, digital signal synthesis unit configuration circuit schematic diagram of the present utility model.
Fig. 3-the 2nd, digital signal synthesis unit clock imput output circuit schematic diagram of the present utility model.
Fig. 3-the 3rd, the interface circuit schematic diagram of digital signal synthesis unit of the present utility model and coding and control unit, digital-to-analogue conversion unit.
Fig. 4 is digital-to-analogue conversion unit circuit theory diagrams of the present utility model.
Single transponder up link simulate signal figure when Fig. 5 is putting excessively of the utility model embodiment generation.
Specific implementation method
Below in conjunction with drawings and Examples the utility model is described in further details.As shown in Figure 1, row control transponder uplink signal analogue means of the present utility model has coding and control unit, digital signal synthesis unit and digital-to-analogue conversion unit that order is connected.Coding and control unit and transponder transport module test macro lead to and connect, and the digital-to-analogue conversion unit connects the canonical reference antenna.
Coding is connected by usb bus with test macro with control unit.Described test macro is a computer, wherein moves Test Application software.The data message that needs the analog answer device that coding and control unit acceptance test system send is encoded, and generates up link and sends message.Coding and control unit are finished initialization operation by the I/O port controlling digital signal synthesis unit of oneself, visit digital signal synthesis unit by the external data bus of oneself, send message and carry out FSK modulation generation simulated digital signal to the digital signal synthesis unit.By coding and control unit, test macro is to digital signal synthesis unit signalization simulation duration, the two sections analog signal interval time parameters in front and back.
Generate two ways of digital signals by logical design in the digital signal synthesis unit: up link FSK simulated digital signal and modulation rate reference clock signal, and this two paths of signals exported to the digital-to-analogue conversion unit.
The digital-to-analogue conversion unit is converted into analog electrical signal with two ways of digital signals respectively, the analog electrical signal of modulation rate reference clock signal wherein, amplification is shaped as pulse signal through overdriving, and feeding back to the digital signal synthesis unit, this pulse signal is a up link fsk signal modulated symbol output reference clock.After the up link analog electrical signal that the digital-to-analogue conversion unit transforms carries out filtering, through canonical reference antenna output transponder up link emulation radio signal.
The digital signal synthesis unit adopts field programmable gate array device fpga chip EP3C40F484C8N, and the digital-to-analogue conversion unit is realized by high speed two-way analog-to-digital conversion chip AD9767.
Shown in Fig. 2-1, coding and control unit in the utility model adopt the digital signal processing chip TMS320VC5509A of TI company of Texas Instrument, provide 24MHz reference frequency by external crystal-controlled oscillation, obtain the high speed operation frequency of 192MHz after the inner frequency multiplication.Be integrated with USB interface in this device, test macro is connected communication with coding with control unit by this USB interface.TMS320VC5509A realizes two functions: the one, and the configuration information that the acceptance test system sends, fpga chip in the initialization digital signal synthesis unit, another is the analog answer device information for the treatment of that the acceptance test system sends, encode according to this information then and obtain the up link message, again message is sent to the digital signal synthesis unit at last and modulate output.
Shown in Fig. 2-2, be integrated with USB interface in the TMS320VC5509A, test macro is connected communication with coding with control unit by this USB interface.
Shown in Fig. 2-3, TMS320VC5509A extends out 16 bit wide data/address buss, and this bus is connected with the digital signal synthesis unit with external memory storage.
Shown in Fig. 2-4, TMS320VC5509A is connected to flash memories FLASH chip SST39VF040 and synchronous dynamic random access memory SDRAM chip MT48LC4M16A2.The SST39VF040 internal memory contains the startup working procedure of TMS320VC5509A.
Shown in Fig. 3-1, Fig. 3-2, Fig. 3-3, digital signal synthesis unit in the utility model adopts the fpga chip EP3C40F484C8 of ALTERA company on the structure.This device has 4 and independently simulates the frequency multiplication module, obtain the high speed operation frequency of 120MHz in the system after the reference frequency frequency multiplication of employing input 20MHz, this operating frequency is as the reference clock of EP3C40F484C8 internal digital signal generation and the conversion reference clock in the digital-to-analogue conversion unit.EP3C40F484C8 also has a plurality of built-in multiplier modules simultaneously, is convenient to the needs of Digital Signal Processing such as digital local oscillator NCO and FMAM.The integrated memory of M4K in EP3C40F484C8 can be realized the degree of depth storage of emulation message.Design by internal logic, can generate the uplink signal that meets the transponder technology standard in the EP3C40F484C8, this signal is that a centre frequency is that 4.23MHz ± 200KHz, frequency modulation are that 282.24KHz ± 14.12KHz, modulation rate are the fsk signal of 564.48 ± 14.12Kbit/s, synthetic by digital signal in EP3C40F484C8, can realize fsk signal very easily, and can guarantee that FSK when modulation phase place is continuous.The modulation rate reference clock 564.48 ± 14.12KHz of fsk signal, by generating by numerical frequency source NCO in the EP3C40F484C8, this reference signal feeds back to the modulation that EP3C40F484C8 participates in fsk signal become the pulse signal of 564.48 ± 14.12KHz by external circuit after again.The digital fsk signal of digital signal synthesis unit output can reach 1Hz in the isoparametric frequency change precision of centre frequency, frequency modulation and modulation rate.EP3C40F484C8 is connected with the external data bus of TMS320VC5509A, is equivalent to the peripheral hardware of TMS320VC5509A.U5 is an EP3C40F484C8 chip, and U5A, U5F, U5K, U5M, U5J are the part unit among the U5.
As shown in Figure 4, digital-to-analogue conversion unit in the utility model, the high-speed A/D converter chip AD9767 of the limited ADI of employing Ya De promise semiconductor technology on its structure.This chip has two independent digital-to-analogue converter DAC, and the FSK digital signal of the 4.23MHz of digital signal synthesis unit output and the modulation reference clock of 282.24KHz are converted to analog electrical signal.Wherein the analog passband signal of 282.24KHz feeds back to FPGA EP3C40F484C8 as FSK modulation rate reference clock after overdriving and being shaped as pulse signal.4.23MHz the FSK analog electrical signal by the high frequency images signal more than the 5 rank low pass filter filters out 10MHz that constitute by first inductance L 1, second inductance L 2, the 3rd inductance L 3, the 4th inductance L 4, the 3rd capacitor C 3, the 4th capacitor C 4 and the 5th capacitor C 5.The conversion precision of chip AD9767 is 14bit, and the highest conversion rate can reach 120MHz, is enough to guarantee to generate the fsk signal of high accuracy emulation.Last AD9767 generates fsk signal and becomes transponder uplink radio simulate signal by the canonical reference antenna, can test the receptivity of transponder transport module with this wireless signal.
As shown in Figure 5, be according to present embodiment generate cross some the time the single transponder up link simulated digital signal curve drawn, curve (a) is the energy size variation relation curve in time of up link simulate signal, and curve (b) is a up link emulation signal of telecommunication variation relation curve in time.
The utility model produces non-matter emulation signal, and analog answer device uplink signal comes test b TM receptivity.Test macro can carry out regulating and controlling to the various performance parameters of simulate signal by USB interface, satisfy the various demands of test, circuit structure is simple, with low cost, reduce the cost of test b TM receptivity greatly, improve testing efficiency, digital signal can be stored playback, guaranteeing the consistency of test result, is a kind of efficient ways.。
Claims (6)
1. row are controlled transponder uplink signal analogue means, and it is characterized in that: described row control transponder uplink signal analogue means is connected and composed by the coding that is linked in sequence and control unit, digital signal synthesis unit and digital and analogue signals conversion unit; Described coding and control unit are used for the emulation transponder data information that the acceptance test system sends, and finish coding and generate message; Described digital signal synthesis unit is used to generate modulation rate reference signal and digital fsk signal; Described digital-to-analogue conversion unit is converted into analog electrical signal with the modulation rate reference signal, and after amplifying shaping, feed back to the digital signal synthesis unit as the modulation rate reference clock, the digital-to-analogue conversion unit is converted into analog electrical signal with digital fsk signal, exports to the canonical reference antenna.
2. row control transponder uplink signal analogue means according to claim 1, it is characterized in that: described coding is connected test macro with control unit.
3. row control transponder uplink signal analogue means according to claim 2 is characterized in that: described digital-to-analogue conversion unit connects the canonical reference antenna.
4. row control transponder uplink signal analogue means according to claim 3 is characterized in that: described coding and control unit adopt digital signal processor TMS320C5509A.
5. row control transponder uplink signal analogue means according to claim 4 is characterized in that: described digital signal synthesis unit adopts field programmable gate array device EP3C40F484C8N.
6. row control transponder uplink signal analogue means according to claim 5 is characterized in that: described digital and analogue signals conversion unit adopts digital-to-analogue to transform chip AD9767.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205274698U CN201789500U (en) | 2010-09-14 | 2010-09-14 | Train control transponder uplink signal simulating device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010205274698U CN201789500U (en) | 2010-09-14 | 2010-09-14 | Train control transponder uplink signal simulating device |
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| CN201789500U true CN201789500U (en) | 2011-04-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011144095A2 (en) * | 2011-05-26 | 2011-11-24 | 华为技术有限公司 | Responder detection method and responder detection system |
| CN104219012A (en) * | 2014-10-09 | 2014-12-17 | 北京交大思诺科技有限公司 | EMC test system and EMC test method for transponder transmission module |
| CN104993807A (en) * | 2015-07-16 | 2015-10-21 | 北京交大思诺科技股份有限公司 | Filtering method for processing transponder uplink signal |
| CN114448534A (en) * | 2021-12-24 | 2022-05-06 | 北京联合大学 | Rail transit transponder interference test system |
-
2010
- 2010-09-14 CN CN2010205274698U patent/CN201789500U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011144095A2 (en) * | 2011-05-26 | 2011-11-24 | 华为技术有限公司 | Responder detection method and responder detection system |
| WO2011144095A3 (en) * | 2011-05-26 | 2012-04-26 | 华为技术有限公司 | Balise detection method and balise detection system |
| CN102754355A (en) * | 2011-05-26 | 2012-10-24 | 华为技术有限公司 | Responder detection method and responder detection system |
| CN102754355B (en) * | 2011-05-26 | 2014-04-30 | 华为技术有限公司 | Responder detection method and responder detection system |
| CN104219012A (en) * | 2014-10-09 | 2014-12-17 | 北京交大思诺科技有限公司 | EMC test system and EMC test method for transponder transmission module |
| CN104993807A (en) * | 2015-07-16 | 2015-10-21 | 北京交大思诺科技股份有限公司 | Filtering method for processing transponder uplink signal |
| CN104993807B (en) * | 2015-07-16 | 2017-10-27 | 北京交大思诺科技股份有限公司 | A kind of filtering method handled for transponder uplink signal |
| CN114448534A (en) * | 2021-12-24 | 2022-05-06 | 北京联合大学 | Rail transit transponder interference test system |
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Granted publication date: 20110406 |
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