CN205038478U - IP kernel takes place to use for wave form based on UART interface - Google Patents
IP kernel takes place to use for wave form based on UART interface Download PDFInfo
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Abstract
The utility model relates to a IP kernel takes place to use for wave form based on UART interface belongs to the applied IP kernel technical field that FPGA configure the system, including UART interface, FIFO buffer unit, UART data processor, wave form emergence module, logic control top layer and output interface, UART interface connection FIFO buffer unit, UART data processor is connected to the FIFO buffer unit, and UART data processor connects the wave form and takes place the module, and the logic control top layer is connected with UART data processor and wave form emergence module, and the output interface is connected to the output of wave form emergence module. The utility model provides a problem that wave form signal real time control in -process debugging is complicated, the required time is long, the utility model discloses sine wave, sawtooth wave and the triangular wave that can produce interior arbitrary frequency of threshold range and arbitrary phase have, the advantage of the PWM ripples of arbitrary frequency, arbitrary phase and arbitrary duty cycle.
Description
Technical field
The utility model belongs to the application IP kernel technical field of FPGA architecture system, is specifically related to a kind of waveform based on UART interface and application IP kernel occurs.
Background technology
FPGA as a kind of programmable logic device (PLD), because its process data speed is fast, flexible configuration, often by core processor that first-selection is in various system.Vast use FPGA is carried out to the user of development, want to shorten the research and development of products time, resource on the plate realizing product required function and saving FPGA as much as possible as early as possible, existing special function IP kernel is used to become a kind of inevitable trend, if research staff from bottom a little knock code to complete the design of whole system, so not only can waste the time of a large amount of research and development, the release time of product can by seriously delayed, and also be a kind of waste to resource on the plate of FPGA.In measurement, the communications field, often need to use some specific waveform signal sources carry out completion system design or realize certain function, and in some particular conditions, engineering staff wishes to carry out the waveform signal occurred controlling with debugging to meet design requirement in real time, UART interface is a kind of serial communication interface of standard, its be widely used in data communication, computer network and distributed industrial systems exchanges data with communicate, completed on-line debugging and the generation of required waveform signal by UART interface, the object of simplification work can be reached.Therefore, UART interface and waveform generating function module are combined and makes IP kernel, be supplied to research staff or engineering staff and use there is very strong practical significance.
Summary of the invention
According to above the deficiencies in the prior art, technical problem to be solved in the utility model proposes a kind of waveform based on UART interface application IP kernel occurs, by repacking UART data processor and waveform generating module into application IP kernel, solve the problem that in the real-time control procedure of waveform signal, debugging is complicated, required time is long, the utility model has sine wave, sawtooth wave and the triangular wave that can produce optional frequency and arbitrary phase in threshold range; The PWM ripple of optional frequency, arbitrary phase and any dutycycle; And debug out characteristic frequency, the advantage of the SPWM ripple of dutycycle.
In order to solve the problems of the technologies described above, the technical solution adopted in the utility model is: application IP kernel occurs a kind of waveform based on UART interface, there is application IP kernel and comprise UART interface in described waveform, FIFO buffer cell, UART data processor, waveform generating module, logic control top layer and output interface, the input end of UART interface receives the command packet of holding host computer from PC, the output terminal of UART interface connects FIFO buffer cell, the output terminal of FIFO buffer cell connects the input end of UART data processor, the output terminal of UART data processor connects the input end of waveform generating module, logic control top layer is connected with waveform generating module with UART data processor, the output terminal of waveform generating module connects output interface, waveform needed for waveform generating module is produced by output interface.
Above-mentioned waveform occurs in application IP kernel, described UART data processor comprises UART controller, signal detector, data comparator, Baud rate generator, shift register and ROM command parameter table, the input end of signal detector connects FIFO buffer cell, the signal detector of Real-Time Monitoring input signal connects UART controller, data comparator connects UART controller and compares data according to the instruction of UART controller, the input end of Baud rate generator connects UART controller and produces baud rate clock according to the instruction of UART controller, the output terminal of Baud rate generator connects shift register, shift register connects UART controller and FIFO buffer cell, ROM command parameter list catenation data comparator and UART controller.Described UART data processor also comprises RAM buffer, the command packet that RAM buffer connection data comparer and UART controller receive in order to deposit UART controller, data comparator compares the command packet in ROM command parameter table and RAM buffer under the instruction of UART controller.Described UART data processor also comprises data register, the effective data packets that the input end connection data comparer of data register exports in order to temporal data comparer, and the output terminal of data register connects waveform generating module.Described UART data processor also comprises bus selector and parity checker, bus selector and parity checker are connected on UART controller, and the input end of parity checker connects bus selector in order to check that parity checker receives the parity check bit of data.Described UART data processor also comprises record serial number according to the counter sending or receive number, and the input end of counter connects Baud rate generator, and the output terminal of counter connects UART controller and notifies the count value that UART controller is current.Above-mentioned waveform occurs in application IP kernel, described waveform generating module comprises DDS controller, mode selector, phase register, data buffering divider, ROM waveform table and Wave data divider, mode selector connects DDS controller, data buffering divider receives the effective data packets in UART data processor and carries out deconsolidation process to the command parameter in effective data packets, the output terminal of data buffering divider connects DDS controller, the output terminal of data buffering divider connects phase register, the output terminal of phase register connects mode selector, ROM waveform table connects DDS controller and mode selector, Wave data divider connects ROM waveform table and DDS controller simultaneously, the output terminal of Wave data divider connects output interface.Described command parameter comprises Waveform Control word, phase control words and frequency control word, frequency control word constantly adds up and is stored in phase register, the value that phase register overflows is input in mode selector with phase control words phase adduction, and Waveform Control word is input in mode selector.Described ROM waveform table comprises sinusoidal wave question blank, sawtooth wave question blank and triangular wave question blank, ROM waveform table output waveform data is to Wave data divider, waveform generating module also comprises comparer, comparer is connected between Wave data divider and output interface, Wave data divider connects output interface by comparer, and Wave data divider directly connects output interface simultaneously.Described waveform generating module also comprises PWM generator, the input end of PWM generator connects DDS controller, the output terminal of PWM generator connects output interface, PWM generator comprises PWM data distributor, initial phase register, duty cycle register, frequency word register, PWM counter and Dead band controller, and the information that PWM generator receives exports PWM data through the process of PWM data distributor, initial phase register, duty cycle register, frequency word register, PWM counter and Dead band controller.
The utility model beneficial effect is: the utility model is based on FPGA architecture system, there is the design of application IP kernel in the waveform realizing band UART interface, its hardware design is flexible, configuration operation is simple, portable strong, by adding UART interface on waveform generating function basis, make user can the generation of control waveform in real time, and complete the on-line debugging that waveform occurs, the utility model is made to use easily like this, thus greatly reduce the workload of user, by UART interface and waveform generating function are packaged into IP kernel, make user directly can use this IP kernel complete design when using FPGA development or realize certain design, this makes it possible to reduce greatly the wasting of resources of FPGA and bring convenience to User Exploitation or design.
Accompanying drawing explanation
Below the content expressed by this Figure of description and the mark in figure are briefly described:
Fig. 1 is the system chart of embodiment of the present utility model;
Fig. 2 is the UART data processor theory diagram of embodiment of the present utility model;
Fig. 3 is the waveform generating module theory diagram of embodiment of the present utility model;
Fig. 4 is the PWM generator theory diagram of embodiment of the present utility model;
Fig. 5 is that the UART interface of embodiment of the present utility model and the Verilog language of output interface describe schematic diagram;
Fig. 6 is the order data packet format schematic diagram of embodiment of the present utility model;
Fig. 7 is the construction method FB(flow block) of embodiment of the present utility model.
Embodiment
Contrast accompanying drawing below, by the description to embodiment, embodiment of the present utility model is as the effect of the mutual alignment between the shape of involved each component, structure, each several part and annexation, each several part and principle of work, manufacturing process and operation using method etc., be described in further detail, have more complete, accurate and deep understanding to help those skilled in the art to inventive concept of the present utility model, technical scheme.
As shown in Figures 1 to 6, there is application IP kernel in a kind of waveform based on UART interface, there is application IP kernel and comprise UART interface in waveform, FIFO buffer cell, UART data processor, waveform generating module, logic control top layer and output interface, the input end of UART interface receives the command packet of holding host computer from PC, the output terminal of UART interface connects FIFO buffer cell, the output terminal of FIFO buffer cell connects the input end of UART data processor, the output terminal of UART data processor connects the input end of waveform generating module, logic control top layer is connected with waveform generating module with UART data processor, the output terminal of waveform generating module connects output interface.UART interface receives the command packet of holding host computer from PC, be transferred to FIFO buffer cell, command packet is transferred to UART data processor and processes by FIFO buffer cell, command packet after process is transferred to waveform generating module, and described waveform generating module exports the required waveform produced by the output interface connected.
As shown in Figure 2, UART data processor comprises UART controller, signal detector, data comparator, Baud rate generator, shift register, ROM command parameter table, RAM buffer, data register, bus selector, parity checker sum counter, the input end of signal detector connects FIFO buffer cell, the signal detector of Real-Time Monitoring input signal connects UART controller, data comparator connects UART controller and compares data according to the instruction of UART controller, the input end of Baud rate generator connects UART controller and produces baud rate clock according to the instruction of UART controller, the output terminal of Baud rate generator connects shift register, shift register connects UART controller and FIFO buffer cell, the output terminal of shift register connects Baud rate generator, ROM command parameter list catenation data comparator and UART controller.Signal detector Real-Time Monitoring input signal, if find, new data notifies UART controller immediately, Baud rate generator produces baud rate clock under the control of UART controller, shift register synchronously receives the command packet of FIFO buffer cell input under the driving of baud rate clock, and be transferred to UART controller, or by UART controller internal data by shift register output to FIFO buffer cell, the order data of reception leaves in connected RAM buffer by UART controller.
The director data that RAM buffer connection data comparer and UART controller receive in order to deposit UART controller, data comparator compares the command packet in ROM command parameter table and RAM buffer under the instruction of UART controller.Data comparator compares the command packet in ROM command parameter table and RAM buffer at the enable lower of UART controller, if the command parameter that the command packet nonsystematic received is preset, RAM buffer removes this order data of buffer memory, if meet the command parameter of systemic presupposition, the effective data packets after examination is transferred to data register by data comparator.
The effective data packets that the input end connection data comparer of data register exports in order to temporal data comparer, the output terminal of data register connects waveform generating module.Bus selector and parity checker are connected on UART controller, and the input end of parity checker connects bus selector in order to check that parity checker receives the parity check bit of data.Bus selector selects the input data of parity checker to be send bus or data receiver bus, parity checker is when data receiver, check that whether the parity check bit of data accepted is correct, after generation parity check bit is additional to data to be sent when data send.Counter in order to record serial number according to sending or receiving number, the input end of counter connects Baud rate generator, the output terminal of counter connects UART controller and notifies the count value of the counter of UART controller, notifies UART controller when namely counting down to certain value.
As shown in Figure 3, waveform generating module comprises DDS controller, mode selector, phase register, data buffering divider, ROM waveform table, Wave data divider and PWM generator, mode selector connects DDS controller, data buffering divider receives the effective data packets in UART data processor and carries out deconsolidation process to the command parameter in effective data packets, the output terminal of data buffering divider connects DDS controller, the output terminal of data buffering divider connects phase register, the output terminal of phase register connects mode selector, ROM waveform table connects DDS controller and mode selector, Wave data divider connects ROM waveform table and DDS controller simultaneously, the output terminal of Wave data divider connects output interface.
Mentioned order parameter comprises Waveform Control word, phase control words and frequency control word, described frequency control word constantly adds up and is stored in phase register under the driving of clock, the value that phase register overflows is with phase control words phase adduction input waveform selector switch, Waveform Control word is input in mode selector, and mode selector is connected with ROM waveform table.ROM waveform table comprises sinusoidal wave question blank, sawtooth wave question blank and triangular wave question blank, ROM waveform table output waveform data is to Wave data divider, waveform generating module also comprises comparer, comparer is connected between Wave data divider and output interface, Wave data divider connects output interface by comparer, Wave data divider directly connects output interface simultaneously, and Wave data divider exports after the Wave data of reception access comparer or directly exported by output interface under the control of DDS controller.
As shown in Figure 4, the input end of PWM generator connects DDS controller, the output terminal of PWM generator connects output interface, PWM generator comprises PWM data distributor, initial phase register, duty cycle register, frequency word register and PWM counter, the output terminal of DDS controller connects PWM data distributor, DDS controller connects PWM counter and Dead band controller simultaneously, PWM data distributor connects initial phase register simultaneously, duty cycle register and frequency word register, initial phase register, duty cycle register and frequency word register are connected to PWM counter, PWM counter connects Dead band controller, Dead band controller connects output interface.The information that PWM generator receives exports PWM data through the process of PWM data distributor, initial phase register, duty cycle register, frequency word register and PWM counter, concrete data procedures is: PWM generator receives the effective data packets that data buffering divider is transferred to DDS controller, split and distributed to above-mentioned register, PWM counter is connected with Dead band controller, it receives the value of above-mentioned register and exports PWM data after doing computing under the control of DDS controller, and PWM data are exported by output interface after Dead band controller.
The utility model adopts Verilog hardware language based on FPGA architecture system, receive command packet by UART interface to complete waveform and occur and the function of on-line debugging, it can produce the sine wave of optional frequency and arbitrary phase in threshold range, sawtooth wave and triangular wave; The PWM ripple of optional frequency, arbitrary phase and any dutycycle; And debug out characteristic frequency, the SPWM ripple of dutycycle.
Specific implementation principle is: UART interface and UART Universal Asynchronous Receiver Transmitter transmitter interfaces, as shown in Figure 5, it comprises clock line (clk), data receiver line (rs232_rx), data transmission line (rs232_tx), user is when using this IP kernel, on the basis depending on fpga chip, programmed by Verilog hardware language, the UART interface of this IP kernel of exampleization and output interface in top layer, the host computer that so just can realize holding with PC communicates, certainly, this communication also need by means of the hardware device of TTL RS 232 level, to realize the level match that FPGA and PC holds transmission line, user will realize the generation of waveform and debug function need by means of the host computer input of control commands of PC end, control command is packaged into command packet by the host computer of PC end automatically, FPGA is sent to by UART interface, FPGA has processed the required function realized to control command after receiving this command packet again.
The form of host computer packing command packet has two kinds, whether input generation PWM ripple according to user to distinguish, when not producing PWM ripple, as shown in Figure 6, its form is made up of 1Byte start signal+1Byte waveform parameter+1Byte phase parameter+10Byte frequency parameter+3Byte phase parameter+1Byte end signal, when producing PWM, its form is same as described above, just after 3Byte phase parameter with before 1Byte end signal, insert the duty cycle parameters of 3Byte, start signal is capitalization " A ", waveform parameter has 5 kinds, capitalization " S " represents sine wave, " T " represents triangular wave, capitalization " W " represents sawtooth wave, " P " represents PWM ripple, " M " represents SPWM ripple, that is each data are surrounded by 16 bytes or 19 bytes, each command packet can be distinguished or be processed to FPGA receiving end by detection start signal and end signal, the packing of command packet has host computer automatically to complete, user only need select to input corresponding parameter on host computer panel, the input range of frequency parameter is the integer of 0 to 1000000000, and the rate-adaptive pacemaker that namely the utility model can realize is 0Hz to 1MHz, phase parameter is the integer of 0 to 360, and the computing formula between the phase parameter X of input and phase value Y is: Y=2 π * (X/360), the input range of duty cycle parameters is the integer of 0 to 100, and 0 to represent dutycycle be that 0%, 100 to represent dutycycle be 100%, the like, in proportionate relationship between the duty cycle parameters value of input and dutycycle, end signal is capitalization " E ", and FPGA termination receives orders after packet, is carried out deconsolidation process, according to above-mentioned parameter form, just can translate the control command that user sends.
Command packet is transferred to UART data processor after being transferred to FIFO by data receiver line (rs232_rx) again, signal detector monitors the input of command packet, notice UART controller, UART controller controls Baud rate generator and shift register, make shift register under the driving of baud rate clock, synchronously receive serial data on rs232_rx, and transfer data to UART controller, UART transfers data to RAM buffer again, under the control of UART controller, the command parameter data of RAM buffer and ROM command parameter table are read out, feeding comparer compares, if FPGA receives correct command parameter, the packet header of command packet and bag tail are just removed by data comparator, namely start signal and end signal are removed, again by command packet stored in data register, at this moment packet is called as valid data packet, if the data in the command parameter that FPGA receives and ROM command parameter table are not inconsistent, system just gives up this command packet, the function of counter module is that record serial number is according to the number sent or receive, UART controller is notified when counting down to certain numerical value, the function of parity checker calculates corresponding parity check bit according to the setting of parity checking and input data, it is realized by pure combinational logic, serial ports needs when transmitting 1Byte data to add parity check bit after 8Bit data, such accuracy that can improve data transmission, bus selector is that data send bus or data receiver bus for selecting the input of parity checker, when receiving data, data receiver bus is connected to the input end of parity checker by bus selector, check that whether the parity check bit of data accepted is correct, and when sending data, data are sent the input end that bus is connected to parity checker by bus selector, UART controller just can obtain and preserve the parity check bit needed for sequence to be sent, when the data that FPGA receives not meet in command packet perhaps form time, UART data processor just sends character string " Waring! by data transmission line (rs232_tx) " the host computer held to PC of warning message.
Effective data packets in waveform generating module read data register, in input data buffering divider, data buffering divider splits after distinguishing effective data packets, if first character effective data packets being detected for " P ", when namely receiving the order producing PWM ripple, then do not split effective data packets, by DDS controller, effective data packets is transferred to PWM generator process, if first character is other waveform parameter character, then fractionation conversion is carried out to the command parameter in effective data packets, split and change out corresponding Waveform Control word, frequency control word and phase control words, we utilize DDS and Direct Digital Synthesizer technology to realize the generation of waveform, its principle is: in waveform generating module, build a phase accumulator, it is made up of a totalizer and phase register, its effect carries out linear superposition under the effect in reference clock source, just one-period is completed when producing and overflowing, an i.e. frequency cycle of DDS, wherein the bit wide of frequency control word is K position, as an input of totalizer, another input end bit wide of totalizer is N position (N>K), often carry out a clock, another of frequency word and totalizer inputs the result that is added stored in phase register, feed back to totalizer again, this is equivalent to often carry out a clock, the output of phase register just accumulates once, the output valve of phase register is added with phase control words, and in this, as the address of ROM waveform table, whenever the value of totalizer is overflowed once, the value of input summer just adds one, accordingly, address as ROM waveform table just adds one, and in the address of ROM waveform table, preserve the range value of waveform, these discrete range values are just reducible through DAC and PLF is analog waveform.
The address value that phase accumulator obtains will could be sent in ROM waveform table through mode selector and read data, address value is sent in the question blank in corresponding ROM waveform table by the Waveform Control word received by mode selector, ROM waveform table is by sinusoidal wave question blank, sawtooth wave question blank and triangular wave question blank form, it is separate, sine wave is deposited respectively in inside, the digitized wave graphic data of sawtooth wave and triangular wave, under the clock of DDS controller output is enable, the address value of required generation waveform is sent in corresponding question blank and read Wave data, Wave data is exported by output interface by Wave data divider, so just digitized waveform can be produced, when namely the waveform parameter that mode selector receives will produce SPWM ripple for " M ", waveform occurring principle is different from above-mentioned, now, DDS controller is enable sinusoidal wave question blank and sawtooth wave question blank simultaneously, and address value is sent into sinusoidal wave question blank and sawtooth wave question blank by mode selector simultaneously, the data read from sinusoidal wave question blank and sawtooth wave question blank import Wave data divider into, sinusoidal wave data and triangular wave data are sent into comparer and are compared by Wave data divider under the effect of DDS controller, when the amplitude of triangular wave is greater than sine wave, comparer exports high level " 1 ", when the amplitude of triangular wave is less than sine wave, comparer output low level " 0 ", directly accesses output interface by comparer, just can realize the output of SPWM ripple.
The generation principle of PWM ripple is similar to the above, it is also split the command parameter in effective data packets by means of PWM data distributor, split out corresponding frequency parameter, phase parameter and duty cycle parameters, then frequency word register is sent into respectively, in duty cycle register and initial phase register, PWM counter receives these data and calculates, thus export PWM ripple, the PWM ripple exported is by accessing output interface after Dead band controller, the effect of Dead band controller prevents the PWM Wave data exported from occurring exceptional value, exceed set threshold range.
The Verilog hardware language of output interface describes as shown in Figure 4, and wave_sin represents sinewave output data line; Wave_tri represents triangular wave output data line; Wave_saw represents sawtooth wave output data line; Wave_pwm represents PWM ripple output data line; Wave_spwm represents SPWM ripple output data line, the Wave data that waveform generating module produces is the digitized signal of series of discrete, its Wave data produced exports from the wave form output data line of correspondence, user will expect that respective mode intends waveform signal, only need input digitized Wave data to D/A converter part to complete digital-to-analog conversion from the output interface of this IP kernel, so just can arrive corresponding analog waveform signal.
Logic control top layer is the control core of whole system, and it is by exampleization UART controller and DDS controller, and the running and the data between the two that control them are transmitted.In sum, the utility model is based on FPGA architecture system utilizing Verilog hardware description language complete the exploitation of IP kernel, this IP kernel provides the output interface that a UART interface communicated with host computer and export digitized wave graphic data, it receives the command packet of holding host computer from PC, then corresponding wave form output is completed according to parameter command, user can carry out the exploitation of finished item or realize required function design by this IP kernel of exampleization in FPGA development and Design, and due to the output of waveform be controlled in real time, user can complete by means of this IP kernel the on-line debugging that waveform occurs.
By reference to the accompanying drawings the utility model is exemplarily described above; obvious the utility model specific implementation is not subject to the restrictions described above; as long as have employed the improvement of the various unsubstantialities that method of the present utility model is conceived and technical scheme is carried out; or design of the present utility model and technical scheme directly applied to other occasion, all within protection domain of the present utility model without to improve.The protection domain that protection domain of the present utility model should limit with claims is as the criterion.
Claims (10)
1. there is application IP kernel in the waveform based on UART interface, it is characterized in that, there is application IP kernel and comprise UART interface in described waveform, FIFO buffer cell, UART data processor, waveform generating module, logic control top layer and output interface, the input end of UART interface receives the command packet of holding host computer from PC, the output terminal of UART interface connects FIFO buffer cell, the output terminal of FIFO buffer cell connects the input end of UART data processor, the output terminal of UART data processor connects the input end of waveform generating module, logic control top layer is connected with waveform generating module with UART data processor, the output terminal of waveform generating module connects output interface, waveform needed for waveform generating module is produced by output interface.
2. there is application IP kernel in the waveform based on UART interface according to claim 1, it is characterized in that, described UART data processor comprises UART controller, signal detector, data comparator, Baud rate generator, shift register and ROM command parameter table, the input end of signal detector connects FIFO buffer cell, the signal detector of Real-Time Monitoring input signal connects UART controller, data comparator connects UART controller and compares data according to the instruction of UART controller, the input end of Baud rate generator connects UART controller and produces baud rate clock according to the instruction of UART controller, the output terminal of Baud rate generator connects shift register, shift register connects UART controller and FIFO buffer cell, ROM command parameter list catenation data comparator and UART controller.
3. there is application IP kernel in the waveform based on UART interface according to claim 2, it is characterized in that, described UART data processor also comprises RAM buffer, the command packet that RAM buffer connection data comparer and UART controller receive in order to deposit UART controller, data comparator compares the command packet in ROM command parameter table and RAM buffer under the instruction of UART controller.
4. there is application IP kernel in the waveform based on UART interface according to claim 2, it is characterized in that, described UART data processor also comprises data register, the effective data packets that the input end connection data comparer of data register exports in order to temporal data comparer, the output terminal of data register connects waveform generating module.
5. there is application IP kernel in the waveform based on UART interface according to claim 2, it is characterized in that, described UART data processor also comprises bus selector and parity checker, bus selector and parity checker are connected on UART controller, and the input end of parity checker connects bus selector in order to check that parity checker receives the parity check bit of data.
6. there is application IP kernel in the waveform based on UART interface according to claim 2, it is characterized in that, described UART data processor also comprises record serial number according to the counter sending or receive number, the input end of counter connects Baud rate generator, and the output terminal of counter connects UART controller and notifies the count value that UART controller is current.
7. there is application IP kernel in the waveform based on UART interface according to claim 1, it is characterized in that, described waveform generating module comprises DDS controller, mode selector, phase register, data buffering divider, ROM waveform table and Wave data divider, mode selector connects DDS controller, data buffering divider receives the effective data packets in UART data processor and carries out deconsolidation process to the command parameter in effective data packets, the output terminal of data buffering divider connects DDS controller, the output terminal of data buffering divider connects phase register, the output terminal of phase register connects mode selector, ROM waveform table connects DDS controller and mode selector, Wave data divider connects ROM waveform table and DDS controller simultaneously, the output terminal of Wave data divider connects output interface.
8. there is application IP kernel in the waveform based on UART interface according to claim 7, it is characterized in that, described command parameter comprises Waveform Control word, phase control words and frequency control word, frequency control word constantly adds up and is stored in phase register, the value that phase register overflows is input in mode selector with phase control words phase adduction, and Waveform Control word is input in mode selector.
9. there is application IP kernel in the waveform based on UART interface according to claim 7, it is characterized in that, described ROM waveform table comprises sinusoidal wave question blank, sawtooth wave question blank and triangular wave question blank, ROM waveform table output waveform data is to Wave data divider, waveform generating module also comprises comparer, comparer is connected between Wave data divider and output interface, and Wave data divider connects output interface by comparer, and Wave data divider directly connects output interface simultaneously.
10. there is application IP kernel in the waveform based on UART interface according to claim 7, it is characterized in that, described waveform generating module also comprises PWM generator, the input end of PWM generator connects DDS controller, the output terminal of PWM generator connects output interface, PWM generator comprises PWM data distributor, initial phase register, duty cycle register, frequency word register, PWM counter and Dead band controller, the information that PWM generator receives is through PWM data distributor, initial phase register, duty cycle register, frequency word register, the process of PWM counter and Dead band controller exports PWM data.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059536A (en) * | 2016-07-14 | 2016-10-26 | 深圳市鼎阳科技有限公司 | Square wave signal generator |
| CN112731843A (en) * | 2020-12-28 | 2021-04-30 | 珠海巨晟科技股份有限公司 | Multifunctional multiplexing communication module and control method and MCU thereof |
| CN113778920A (en) * | 2021-11-12 | 2021-12-10 | 湖南双菱电子科技有限公司 | Embedded processor serial port communication method and software development kit |
-
2015
- 2015-09-25 CN CN201520754944.8U patent/CN205038478U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106059536A (en) * | 2016-07-14 | 2016-10-26 | 深圳市鼎阳科技有限公司 | Square wave signal generator |
| CN106059536B (en) * | 2016-07-14 | 2024-03-01 | 深圳市鼎阳科技股份有限公司 | Square wave signal generator |
| CN112731843A (en) * | 2020-12-28 | 2021-04-30 | 珠海巨晟科技股份有限公司 | Multifunctional multiplexing communication module and control method and MCU thereof |
| CN113778920A (en) * | 2021-11-12 | 2021-12-10 | 湖南双菱电子科技有限公司 | Embedded processor serial port communication method and software development kit |
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