CN106302460A - Process layer point-to-point SV sending method and system - Google Patents
Process layer point-to-point SV sending method and system Download PDFInfo
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- CN106302460A CN106302460A CN201610676720.9A CN201610676720A CN106302460A CN 106302460 A CN106302460 A CN 106302460A CN 201610676720 A CN201610676720 A CN 201610676720A CN 106302460 A CN106302460 A CN 106302460A
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- point
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- process layer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/168—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP] specially adapted for link layer protocols, e.g. asynchronous transfer mode [ATM], synchronous optical network [SONET] or point-to-point protocol [PPP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
Abstract
The invention belongs to the relay protection automatic field of power engineering, be specifically related to process layer point-to-point SV sending method and system.System includes CPU, FPGA and PHY ethernet controller, and CPU is connected with FPGA by data/address bus, and described CPU with FPGA is Tong Bu；FPGA design is realized multiple MAC module and is connected with PHY ethernet transceiver by corresponding interface；The analog data collected is packaged into SV message by CPU；SV message includes the pre-transmission timestamp of correspondence；FPGA reads SV message, reads SV message content and corresponding pre-transmission time, treats that system time coincide with the pre-transmission time, controls to send SV message to PHY.Send timestamp in advance by SV message is added, improve the uniformity that point-to-point SV sends.
Description
Technical field
The invention belongs to the relay protection automatic field of power engineering, be specifically related to process layer point-to-point SV sending method
And system.
Background technology
Process layer has been used for the real-time electrical quantities measurement of operation power, has run the state parameter detection of equipment, operation control
Make, perform and drive, including analog quantity, switch acquisition and execution.Propose in the latest specification of national grid 35kV and
Following protection device increases All-in-One type of device, it is desirable to All-in-One device supports process layer SV output and GOOSE input and output.
SV message is widely used a kind of Ethernet message in intelligent substation.Traditional Ethernet also exists network delay, network
The various unstable factors such as obstruction, in order to improve the reliability of intelligent substation line protection system, use between protection device
Point-to-point connection.
The MAC layer Ethernet chip that the current many employings of All-in-One device are special, it is achieved Ethernet point-to-point packet sending and receiving merit
Energy.Device hardware structure typically uses microprocessor to control to come data transmit-receive and the inside of too network interface as Logical processing unit
The process of logic.Microprocessor is to meet to require to the speed that data process, but uncertain by himself instruction execution cycle
Property impact, the discreteness of sequencing contro is poor, in the cycle SV send there is bigger discreteness, with group SV multichannel send one
Cause property is the most poor, it is impossible to meet related specifications requirement；Increase multiple point-to-point network interface, also make the hardware structure of core mainboard become
Too fat to move must can't bear, be unfavorable for hardware development.
So, while realizing the transmission of point-to-point message SV message, how to improve the concordance of SV packet sending and receiving with equal
Even property becomes particularly urgent and important, and the construction to New Generation of Intelligent transformer station has great significance.
Summary of the invention
The present invention proposes process layer point-to-point SV sending method and system, in order to solve current process layer point-to-point SV message
The uniformity sent and the highest problem of concordance.
For solving above-mentioned technical problem, the present invention proposes a kind of process layer point-to-point SV sending method, and step is as follows:
1) for the analog data collected, add and send timestamp in advance；
2) treat that system time coincide with the pre-transmission time in described pre-transmission timestamp, control to send SV message.
The present invention also proposes a kind of process layer point-to-point SV sending method, and step is as follows:
1) for the analog data collected, it is packaged into SV message；SV message includes the pre-transmission timestamp of correspondence；
2) read SV message, read SV message content and corresponding pre-transmission time；
3) treat that system time and pre-transmission time coincide, control to send SV message.
The present invention also proposes a kind of point-to-point SV of process layer and sends system, and system includes CPU, FPGA and PHY ether network control
Device processed, CPU is connected with FPGA by data/address bus, CPU with FPGA is Tong Bu；The analog data collected is packaged into by CPU
SV message, SV message includes the pre-transmission timestamp of correspondence；FPGA reads the pre-of SV message, reading SV message content and correspondence
The transmission time, treat that system time coincide with the pre-transmission time, control to send SV message to PHY.
Further, above-mentioned FPGA design realizes multiple MAC module by corresponding interface and PHY ethernet transceiver phase
Even.
Further, above-mentioned FPGA design realizes dma controller and mac controller, dma controller and mac controller phase
Connecting, mac controller controls described MAC module.
Further, above-mentioned data/address bus is PCIE.
Further, above-mentioned CPU is MPC8377.
Further, above-mentioned FPGA is XC6SLX45T.
Further, above-mentioned PHY ethernet controller is 88E3082.
Further, above-mentioned interface is RMII.
The invention has the beneficial effects as follows:
The present invention propose process layer point-to-point SV sending method, to SV message add timestamp, accurate SV delivery time,
Improve the uniformity that SV sends.
The point-to-point SV of process layer that the present invention proposes sends system, uses the mode of CPU+FPGA+PHY ethernet controller
Realize the transmission of SV message, use FPGA design to realize multiple MAC module and communicate for multichannel Ethernet SV, parallel based on FPGA
Treatment characteristic, can control multichannel Ethernet and realize SV transmission simultaneously, improve the concordance that SV message sends.
Accompanying drawing explanation
Fig. 1 is the hardware structure diagram of the present invention；
Fig. 2 is that SV of the present invention sends buffer queue；
Fig. 3 is SV message transmission timing of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical solution of the present invention is carried out in detail, clearly describes.
The present invention provides a kind of point-to-point SV of process layer to send system embodiment.
As it is shown in figure 1, the hardware system structure of the present invention includes CPU, FPGA and PHY ethernet controller, CPU and FPGA
Data interaction is carried out by data/address bus；FPGA design realizes multiple MAC module by corresponding interface and PHY ethernet transceiver
It is connected.
Wherein, the MPC8377, FPGA of CPU processor employing Freescale uses the Spantan-6 series of Xilinx
XC6SLX45T.Using VHDL language to realize dma controller at FPGA design, SV data are real at CPU and FPGA design by PCIE
Transmit between existing dma controller.PCIE is high-speed high-performance universal serial bus, improve transmission in SV database efficiency and can
By property；And FPGA is internally integrated PCIE IP stone, program is easily achieved, and shortens the solution development cycle.
PHY ethernet controller uses the 88E3082 of Marvell, and it has been internally integrated 8 tunnel PHY layer 10/100M Ethernets
Transceiver.Using FPGA to realize ethernet mac layer function, example metaplasia becomes 8 MAC module, by RMII interface and corresponding PHY layer
Ethernet transceiver is connected.
First, it is achieved the clock of CPU and FPGA synchronizes, it is to ensure that SV sends precision and the premise of system reliability.Pass through
FPGA and CPU use at the same time a reference source to realize the time synchronized of CPU and FPGA.Use 25MHz constant-temperature crystal oscillator, for being
System provides reliable and stable clock source, and clock is by FPGA internal DC M frequency multiplication to 100MHz.FPGA internal build one 32
Bit timing device, the minimum resolution of timer can reach 10ns, CPU and FPGA and all read this timer count value as self
Reference time, it is achieved CPU and FPGA time synchronized.
Secondly, utilize operational capability powerful for CPU to SV message of packing, by the analog data that collects according to
IEC61850 stipulations are packaged into SV message frame form.SV only transmits the sampled data of analog quantity, and its message format is fixing, report
Literary composition length is only corresponding with the analog quantity sampling channel number of configuration.CPU not only to complete the work of above-mentioned framing, also will be to passing through
The high-resolution timer of above-mentioned structure sends timestamp in advance to the interpolation of SV message, generates corresponding descriptor and is supplied to FPGA,
FPGA controls the transmission to SV message by this descriptor.
Then, CPU builds one section of memory headroom and is used for caching multiframe SV data and its descriptor, if this relief area less than
CPU can fill SV data always, improves the execution efficiency of CPU, and the safety and reliability of data transmission.
It is illustrated in figure 2 SV and sends buffer queue.Define two pointer variables Head_ptr and Tail_ptr manages this SV
Buffer area, Head_ptr and Tail_ptr is two circle pointers, and CPU often stores a frame SV message owner pointer Head_ptr and adds 1,
FPGA often reads to walk a frame SV message trailer Tail_ptr and adds 1, and the SV message between Head_ptr and Tail_ptr is effective message.Just
In the case of Chang, Head_ptr is before Tail_ptr, and Head_ptr can not catch up with Tail_ptr from behind, otherwise can cause caching
SV message be capped, loss of data.
Then, dma controller directly accesses memory read data by PCIE bus, decreases CPU and participates in link, improves
The efficiency of transmission of SV data.During Idle state, between dma controller detection tail pointer Tail_ptr and owner pointer Head_ptr
There are SV data to be sent, first read descriptor message, obtain the timestamp that SV sends；Then SV data message is read, describing
Symbol and SV message are stored in the Block Ram within FPGA, update tail pointer Tail_ptr simultaneously and add one, and to MAC control
Module produces SV and sends request command.
Finally, when the SV of system time and acquisition send in advance timestamp coincide time, utilize the parallel processing capability of FPGA,
SV message is sent by 8 MAC module of mac controller management simultaneously, it is ensured that the concordance that 8 road SV data send.
For above example, FPGA generates multiple MAC module, communicates for multichannel Ethernet SV, it is achieved multichannel ether
Net sends SV simultaneously, improves SV message and sends concordance；As other embodiments, discounting for consistency problem, it is possible to
Only to generate a MAC module.
In the embodiment above, CPU realizes encapsulation SV message and also adds timestamp, be buffered in one section of memory headroom by
FPGA reads, and SV message is sent to PHY by FPGA.As other embodiments, if not using FPGA, it is possible to realized by CPU
The encapsulation of SV message also sends.
The foregoing is only the preferred embodiments of the present invention, and the scope of the claims of the unrestricted present invention, every utilize this
Equivalent structure or flow process that bright book and accompanying drawing content are made convert, or are directly or indirectly used in other relevant technical fields,
The most in like manner it is included in the scope of patent protection of the present invention.
Claims (10)
1. a process layer point-to-point SV sending method, it is characterised in that step is as follows:
1) for the analog data collected, add and send timestamp in advance；
2) treat that system time coincide with the pre-transmission time in described pre-transmission timestamp, control to send SV message.
2. a process layer point-to-point SV sending method, it is characterised in that step is as follows:
1) for the analog data collected, it is packaged into SV message；SV message includes the pre-transmission timestamp of correspondence；
2) read SV message, read SV message content and corresponding pre-transmission time；
3) treat that system time and pre-transmission time coincide, control to send SV message.
3. the point-to-point SV of process layer sends system, it is characterised in that include CPU, FPGA and PHY ethernet controller, CPU
Being connected with FPGA by data/address bus, described CPU with FPGA is Tong Bu；
The analog data collected is packaged into SV message by CPU, and SV message includes the pre-transmission timestamp of correspondence；
FPGA reads SV message, reads SV message content and corresponding pre-transmission time, treats that system time was kissed with the pre-transmission time
Close, control to send SV message to PHY.
4. the point-to-point SV of process layer sends system, it is characterised in that FPGA design is realized multiple MAC module and connect by correspondence
Mouth is connected with PHY ethernet transceiver.
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that described FPGA design realizes
Dma controller and mac controller, dma controller is connected with mac controller, and mac controller controls described MAC module.
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that described data/address bus is
PCIE。
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that described CPU is MPC8377.
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that: described FPGA is
XC6SLX45T。
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that: described PHY Ethernet controls
Device is 88E3082.
The point-to-point SV of process layer the most according to claim 3 sends system, it is characterised in that: described interface is RMII.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610676720.9A CN106302460A (en) | 2016-08-16 | 2016-08-16 | Process layer point-to-point SV sending method and system |
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| CN201610676720.9A CN106302460A (en) | 2016-08-16 | 2016-08-16 | Process layer point-to-point SV sending method and system |
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Cited By (3)
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| CN108667852A (en) * | 2018-05-22 | 2018-10-16 | 广州穗华能源科技有限公司 | A method of SV messages framing and transmission are realized by FPGA |
| CN111641484A (en) * | 2020-04-17 | 2020-09-08 | 许继集团有限公司 | SV and GOOSE common port transmission method for process layer equipment |
| CN117111539A (en) * | 2023-10-24 | 2023-11-24 | 杭州康吉森自动化科技有限公司 | Control method and device for Ethernet physical layer chip |
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Cited By (5)
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|---|---|---|---|---|
| CN108667852A (en) * | 2018-05-22 | 2018-10-16 | 广州穗华能源科技有限公司 | A method of SV messages framing and transmission are realized by FPGA |
| CN108667852B (en) * | 2018-05-22 | 2021-02-12 | 广州穗华能源科技有限公司 | Method for framing and sending SV message by FPGA |
| CN111641484A (en) * | 2020-04-17 | 2020-09-08 | 许继集团有限公司 | SV and GOOSE common port transmission method for process layer equipment |
| CN117111539A (en) * | 2023-10-24 | 2023-11-24 | 杭州康吉森自动化科技有限公司 | Control method and device for Ethernet physical layer chip |
| CN117111539B (en) * | 2023-10-24 | 2024-02-02 | 杭州康吉森自动化科技有限公司 | Control method and device for Ethernet physical layer chip |
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