CN108667852A - A method of SV messages framing and transmission are realized by FPGA - Google Patents
A method of SV messages framing and transmission are realized by FPGA Download PDFInfo
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- CN108667852A CN108667852A CN201810496312.4A CN201810496312A CN108667852A CN 108667852 A CN108667852 A CN 108667852A CN 201810496312 A CN201810496312 A CN 201810496312A CN 108667852 A CN108667852 A CN 108667852A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
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Abstract
The present invention provides a kind of method for realizing SV messages framing and transmission by FPGA, including step：1) configuration information that software issues is received；2) it selects sendaisle and carries out operation；3) SV messages framing；4) SV messages are sent；Wherein, channel unit, multiplier unit, except counting unit, sampling threshold unit, quality unit, SV frame head units be the configuration information that software is issued to FPGA internal storage units.The method provided by the invention for realizing SV messages framing and transmission by FPGA realizes that SV framings, threshold value comparison, quality position obtains and the multiplication and division operation of two sub-values a to sub-value using the method for FPGA, more efficient for CPU；Framing flexible form can carry out SV framings to the analog data of AD acquisitions with any selector channel.
Description
Technical field
The present invention relates to technical field of power systems, SV messages framing and transmission are realized by FPGA more particularly to a kind of
Method.
Background technology
Currently, IEC61850 standards propose the concept of electric substation automation system functional stratification.Substation equipment is pressed
It is divided into three layers according to function：That is process layer, wall, station level.
Process layer major function is that ac analog, DC analogue quantity, quantity of state are converted into digital signal and are supplied on the spot
Upper layer, and receive and execute the control command that upper layer issues.Process layer devices include primary equipment and its intelligent assembly.
Wall major function is to acquire the signal of this interval primary equipment, control operation primary equipment, and correlation is believed
Station level equipment is given on breath and receives the order of station level equipment.Bay device by each interval control, protection, monitoring
Device forms.
Station level major function be realize it is primary to whole station, secondary device is monitored, control and with a distant place control in
The heart communicates.Station level equipment includes monitoring host computer, remote station, operation element station, time synchronization system etc..
SV (Sampled Vaule) message is also the communication structure using publisher/subscriber.SV messages are a kind of time
The communication mode of driving sends a sampled value every a set time.Its most important transmission requirement is real-time, fast
Speed.When causing message transmissions to be lost due to network, publisher's (electric current, voltage sensor) is simultaneously not serious, should continue
Acquire newest electric current, information of voltage.And subscriber's (such as protective device) allows for detected.This can be reported by SV
Sample counter parameter SmpCnt in text is solved.
The prior art is using the stronger operational capabilities of CPU come when carrying out the packing of SV messages, and being sent for SV messages are specified
Between, SV messages are sent to the transmission buffering area of FPGA, FPGA, which is periodically inquired, sends whether buffering area has message, if there is message,
The sending time for parsing outgoing packet, sending time is compared with the high accurate calculagraph time in FPGA, in SV messages
SV messages are sent when sending time point.It is related to the operation of SV messages, organizes to wrap and all be completed by CPU, FPGA is only responsible for SV
Timing send.
The prior art requires collection value to give CPU on first, and then CPU handles collection value, obtains quality information, into
Then two sub-value of row is packaged as SV messages, and specified sending time, such processing procedure cause to the multiplication and division operation of a sub-value
It is delayed processing time that is long and increasing CPU, and message sending time needs to correct repeatedly and minimum prolong to reach maximum
When and accurate send.
Accordingly, it is desirable to provide a kind of realizing the method for SV messages framing and transmission to solve the above technical problems by FPGA.
Invention content
The invention mainly solves the technical problem of providing a kind of methods for realizing SV messages framing and transmission by FPGA, adopt
Realize that SV framings, threshold value comparison, quality position obtains and the multiplication and division operation of two sub-values a to sub-value with the method for FPGA, compared to
It is more efficient for CPU；Group packet form is flexible, and SV framings can be carried out with any selector channel to the analog data of AD acquisitions.
In order to solve the above technical problems, one aspect of the present invention is to provide one kind realizing SV messages by FPGA
Framing and the method for transmission, including step：
1) configuration information that software issues is received：
Receive the channel selecting of gathered data；
Receive the multiplier of the corresponding channel multiplying to be carried out；
Receive the divisor of the corresponding channel division arithmetic to be carried out；
Receive the sampling threshold values in corresponding channel；
Receive the quality in corresponding channel；
Receive SV headings；
AD acquires analog data；
2) it selects sendaisle and carries out operation：
The analog data is subjected to threshold value comparison with corresponding sampling threshold values, obtains the invalid bit information in quality domain；
Multiplication and division operation is carried out to selected channel according to channel selection information；
Quality domain amendment is carried out to selected channel according to channel selection information；
3) SV messages framing：
SV headings, channel multiplication and division result, quality domain correction result are subjected to framing；
And adding purpose address, source address, verification domain；
Group SV frame timings update sample count values and sample-synchronous domain information every time；
4) SV messages are sent：
SV messages are sent by Ethernet.
It is preferred that in the step 3), group SV frames are carried out with the frequency of 4KHz each second, and count value is 0 at second head, counts model
Enclose is 0~3999.
It is preferred that the reception of the configuration information of the step 1) can only be configured in the case where not enabled SV messages are sent
Or modification.
The beneficial effects of the invention are as follows：A kind of method that SV messages framing and transmission are realized by FPGA provided by the invention,
Realize that SV framings, threshold value comparison, quality position obtains and the multiplication and division operation of two sub-values a to sub-value, compares using the method for FPGA
It is more efficient for CPU；Framing flexible form can carry out SV groups to the analog data of AD acquisitions with any selector channel
Frame.
Description of the drawings
Fig. 1 is a kind of stream of the first preferred embodiment of method for realizing SV messages framing and transmission by FPGA of the present invention
Journey schematic diagram；
Fig. 2 is a kind of original of the first preferred embodiment of method for realizing SV messages framing and transmission by FPGA of the present invention
Manage schematic diagram.
Specific implementation mode
Technical scheme of the present invention is described in detail with reference to diagram.
It refers to shown in Fig. 1 and Fig. 2, the method that SV messages framing and transmission are realized by FPGA of the present embodiment, including step
Suddenly：
1) configuration information 212 that software issues is received：
Receive the channel selecting (channel unit 21) of gathered data；
Receive the multiplier (multiplier unit 22) of the corresponding channel multiplying to be carried out；
Receive the divisor (removing counting unit 23) of the corresponding channel division arithmetic to be carried out；
Receive the sampling threshold values (threshold unit 25) in corresponding channel；
Receive the quality (quality unit 26) in corresponding channel；
Receive SV headings (SV frame heads unit 24)；
AD acquires analog data (analog data 213 of AD acquisitions)；
2) it selects sendaisle 27 and carries out operation：
The analog data is subjected to threshold value comparison 28 with corresponding sampling threshold values, obtains the invalid bit information in quality domain；
Multiplication and division operation (two sub-values are converted to a sub-value 29) is carried out to selected channel according to channel selection information；
Quality domain is carried out to selected channel according to channel selection information and corrects 210；
3) SV messages framing 211：
SV headings, channel multiplication and division result, quality domain correction result are subjected to framing；
And adding purpose address, source address, verification domain；
Group SV frame timings update sample count values and sample-synchronous domain information every time；
4) SV messages 215 are sent：
SV messages are sent by Ethernet；
Wherein, channel unit 21, multiplier unit 22, except counting unit 23, sampling threshold unit 25, quality unit 26,
SV frame heads unit 24 is the configuration information that software is issued to FPGA internal storage units.
In the present embodiment, the analog data 213 of AD acquisitions is not that software issues, and is that FPGA is acquired, at this
The advantages of be exactly that AD gathered datas need not move through software layer, and AD gathered datas are directly carried out SV framing transmissions by hardware, from
And improve data transmission efficiency.
The method provided by the invention for realizing SV messages framing and transmission by FPGA realizes SV message groups using fpga chip
Frame, threshold value comparison, quality position obtain and two sub-values a to sub-value multiplication and division operation, compared to use traditional cpu chip into
It is more efficient for row SV messages framing and transmission；And framing form is more flexible, can appoint to the analog data of AD acquisitions
What selector channel carries out SV message framings.
In the present embodiment, framing format is as shown in the table：
In a preferred embodiment of the invention, in the step 3), group SV frames are carried out with the frequency of 4KHz each second,
Count value is 0 at second head, and count range is 0~3999.Certainly, the concrete numerical value of the frequency in the present embodiment is not limited to 4KHz,
The selection of specific numerical value, needs to be selected according to design requirement, without limitation.
In one embodiment of the invention, it is preferable that the reception of the configuration information of the step 1) can only not enable SV
Message is configured or is changed in the case of sending.
Example the above is only the implementation of the present invention is not intended to limit the scope of the invention, every to utilize this hair
Equivalent structure made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant technical fields, similarly
It is included within the scope of the present invention.
Claims (3)
1. a kind of method for realizing SV messages framing and transmission by FPGA, it is characterised in that：Including step：
1) configuration information that software issues is received：
Receive the channel selecting of gathered data；
Receive the multiplier of the corresponding channel multiplying to be carried out；
Receive the divisor of the corresponding channel division arithmetic to be carried out；
Receive the sampling threshold values in corresponding channel；
Receive the quality in corresponding channel；
Receive SV headings；
AD acquires analog data；
2) it selects sendaisle and carries out operation：
The analog data is subjected to threshold value comparison with corresponding sampling threshold values, obtains the invalid bit information in quality domain；
Multiplication and division operation is carried out to selected channel according to channel selection information；
Quality domain amendment is carried out to selected channel according to channel selection information；
3) SV messages framing：
SV headings, channel multiplication and division result, quality domain correction result are subjected to framing；
And adding purpose address, source address, verification domain；
Group SV frame timings update sample count values and sample-synchronous domain information every time；
4) SV messages are sent：
SV messages are sent by Ethernet.
2. the method according to claim 1 for realizing SV messages framing and transmission by FPGA, it is characterised in that：Step 3)
In, group SV frames are carried out with the frequency of 4KHz each second, and count value is 0 at second head, and count range is 0~3999.
3. the method according to claim 1 for realizing SV messages framing and transmission by FPGA, it is characterised in that：Step 1)
The reception of configuration information can only be configured or be changed in the case where not enabled SV messages are sent.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810496312.4A CN108667852B (en) | 2018-05-22 | 2018-05-22 | Method for framing and sending SV message by FPGA |
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| CN201810496312.4A CN108667852B (en) | 2018-05-22 | 2018-05-22 | Method for framing and sending SV message by FPGA |
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